Re: IRA: matches insn even though !reload_in_progress

[Georg-Johann Lay]

Bernd Schmidt wrote:
> On 07/11/11 13:27, Georg-Johann Lay wrote:
>>>> IRA now propagates insn 7 into insn 8 so that in insn-output gcc runs
>>>> into the gcc_unreachable() even though !reload_in_progress etc should
>>>> keep IRA/reload from generating the insn.
> 
> That can't work because reload_in_progress isn't set during IRA.

Ok, thanks.

I always wondered how to test for these thinks like ire_in_progress or
combine_completed.

Using current_pass->static_pass_number or ->name is nor really a good
idea...

I managed now to do a pre-reload split like so:

(define_insn_and_split "*mulhi3.uconst"
  [(set (match_operand:HI 0 "register_operand"         "=&r")
        (mult:HI (match_operand:HI 1 "register_operand"  "r")
                 (match_operand:HI 2 "u8_operand"        "n")))
   (clobber (match_scratch:QI 3                        "=&d"))]
  "AVR_HAVE_MUL"
  "#"
  "&& 1"
  [(set (match_dup 3)
        (match_dup 2))
   ; "*muluqihi3"
   (set (match_dup 0)
        (mult:HI (zero_extend:HI (match_dup 3))
                 (match_dup 1)))]
  {
    operands[2] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]),
                                               QImode));

    if (SCRATCH == GET_CODE (operands[3]))
      operands[3] = gen_reg_rtx (QImode);
  })

The dumps show that the split actually is done pre-reload :-)

However, suppose a test case like that:

int y15;

int ymul8_15 (int x, int y)
{
    y15 = y * 15;
    return x * 15;
}

The intention of the split is to do it as early as possible in order
for constants like 15 to be CSEd.  However, the compile reads:

ymul8_15:
        ldi r20,lo8(15)  ;  32  *movqi/2        [length = 1]
        mul  r20,r22     ;  33  *muluqihi3      [length = 5]
        movw r18,r0
        mul  r20,r23
        add  r19,r0
        clr  __zero_reg__
        sts y15+1,r19    ;  9   *movhi/3        [length = 4]
        sts y15,r18
        movw r18,r24     ;  31  *movhi/1        [length = 1]
        ldi r20,lo8(15)  ;  34  *movqi/2        [length = 1]
        mul  r20,r18     ;  35  *muluqihi3      [length = 5]
        movw r24,r0
        mul  r20,r19
        add  r25,r0
        clr  __zero_reg__
        ret      ;  38  return  [length = 1]

Note insn 32 and insn 34.

Both get 15 in r20 and r20 is not clobbered anywhere. Yet, r20 is
loaded two times with 15.

The reason is that IRA (or reload, don't see it from the dumps)
combines the insns again to:

(insn 29 31 24 2 (parallel [
            (set (reg:HI 24 r24 [49])
                (mult:HI (reg:HI 18 r18)
                    (const_int 15 [0xf])))
            (clobber (reg:QI 20 r20))
        ]) wmul.c:71 46 {*mulhi3.uconst}
     (nil))

And then post-reload split splits again, giving the two sets.

Ideas?

I need the *insn so that combine can synthesize it, but IRA/reload
does mess up the nice code and undo the split.

Johann