Got it! That even answers my second round of questions.
Thank you!
Dan
On Tue, 2016-04-05 at 01:24 +0200, Eric Botcazou wrote:
> > I took a quick look at Visium, and noticed arithmetic instructions in
> > the .md file doing a lot of clobbering of the condition codes register.
> > This doesn't
On 04/04/2016 08:55 AM, Umesh Kalappa wrote:
We are in process of changing the gcc compiler for aarch64 abi ,w.r.t
varargs function arguments handling.
default(LP64) ,where 1,2,4 bytes args are promoted to word size i.e 4
bytes ,we need to change these behaviour to 8 bytes (double word).
we a
> I took a quick look at Visium, and noticed arithmetic instructions in
> the .md file doing a lot of clobbering of the condition codes register.
> This doesn't seem very efficient, since it prevents the arithmetic
> instructions from being able to set the CC register and have that value
> be used.
On 04/04/16 10:55, Ilya Enkovich wrote:
> 2016-04-02 3:32 GMT+03:00 David Guillen Fandos :
>> Hello there!
>>
>> I'm trying to add some vector registers to a MIPS arch (32 bit). This
>> arch has 32 x 128 bit registers that can essentially be seen as V4SF.
>> So far I'm using this test:
>>
>> vola
I like this position--with good kind natured folks arguing over the best
way to help me. ;P
Thank you both.
I took a quick look at Visium, and noticed arithmetic instructions in
the .md file doing a lot of clobbering of the condition codes register.
This doesn't seem very efficient, since it pre
On 04/04/2016 04:20 PM, Eric Botcazou wrote:
From a 30 second view of your ISA, it appears that most
arithmetic/logicals unconditionally set the condition codes.
I would suggest modeling condition code handling similar to how it's
done on the x86 port.
No advertisement intended, but the Visi
> From a 30 second view of your ISA, it appears that most
> arithmetic/logicals unconditionally set the condition codes.
>
> I would suggest modeling condition code handling similar to how it's
> done on the x86 port.
No advertisement intended, but the Visium architecture is the typical 32-bit
On 04/04/2016 03:13 PM, Dan wrote:
Jeff,
Thank you for your quick response!
Yes, I have a custom ISA. I am building a custom back end. The
project, in its current state, can be found at:
http://opencores.com/project,zipcpu
Can you tell me whether the difference between CC0 processing and
no
Jeff,
Thank you for your quick response!
Yes, I have a custom ISA. I am building a custom back end. The
project, in its current state, can be found at:
http://opencores.com/project,zipcpu
Can you tell me whether the difference between CC0 processing and
non-CC0 processing is a GCC difference
On 04/04/2016 06:36 AM, Andrew Bennett wrote:
Hi,
In MIPS (and similarly for other RISC architectures) to load an absolute
address of an object
requires a two instruction sequence: one instruction to load the high part of
the object's address,
and one instruction to load the low part of the ob
On 04/04/2016 02:19 PM, Dan wrote:
Greetings!
GCC is usually so perfect, that I hate to write, but ... I think I'm
chasing down quite the bug in it and would appreciate some thought to
the following.
The code that causes the bug looks like:
if (ptr) {
*ptr = 1;
}
This code evaluates, in th
Greetings!
GCC is usually so perfect, that I hate to write, but ... I think I'm
chasing down quite the bug in it and would appreciate some thought to
the following.
The code that causes the bug looks like:
if (ptr) {
*ptr = 1;
}
This code evaluates, in the instruction set I am working with, i
On 04/03/2016 09:12 PM, Woon yung Liu wrote:
I can't figure out how to implement comparison operations (specifically,
equals and the greater than operators). The GCC documentation mentions that
the pattern for comparison (==) should be vec_cmp, but I don't understand
why it has 4 operands and wha
On 04/04/2016 05:36 AM, Andrew Bennett wrote:
Hi,
In MIPS (and similarly for other RISC architectures) to load an absolute
address of an object
requires a two instruction sequence: one instruction to load the high part of
the object's address,
and one instruction to load the low part of the ob
Hi All,
We are in process of changing the gcc compiler for aarch64 abi ,w.r.t
varargs function arguments handling.
default(LP64) ,where 1,2,4 bytes args are promoted to word size i.e 4
bytes ,we need to change these behaviour to 8 bytes (double word).
we are looking both hooks like PROMOTE_MO
Hi all,
Since BZ#67877 [1] does not have much information on it, I would like
to ask for some inputs of which is the requirement of implementing
split-stack on aarch64 besides 'feature parity'.
I am asking it because on PR it states the main use it gccgo and
afaik there is some usage in other pro
Hi,
In MIPS (and similarly for other RISC architectures) to load an absolute
address of an object
requires a two instruction sequence: one instruction to load the high part of
the object's address,
and one instruction to load the low part of the object's address. Typically
the result from the
2016-04-02 3:32 GMT+03:00 David Guillen Fandos :
> Hello there!
>
> I'm trying to add some vector registers to a MIPS arch (32 bit). This
> arch has 32 x 128 bit registers that can essentially be seen as V4SF.
> So far I'm using this test:
>
> volatile float foo __attribute__ ((vector_size (16)));
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