> From a 30 second view of your ISA, it appears that most > arithmetic/logicals unconditionally set the condition codes. > > I would suggest modeling condition code handling similar to how it's > done on the x86 port.
No advertisement intended, but the Visium architecture is the typical 32-bit RISC where every single arithmetic/logical unconditionally sets the condition code. Moreover, the port was very recently converted from CC0 to CCmode (with uniform post-reload splitters and define_substs tailored for the postreload compare elimination pass), so it could be a good model. -- Eric Botcazou
