I have a gcc 4.6.1 port that has the same sort of problems. I tried
selectively porting some patches from later 4.6 releases, but they didn't seem
to actually address the issue. I haven't looked at the trunk to see if there
are patches that are more apropos.
On Oct 10, 2013, at 12:33 PM, Jef
On Thu, 2013-10-10 at 09:56 -0400, David Edelsohn wrote:
> On Wed, Oct 9, 2013 at 5:31 PM, David Malcolm wrote:
>
> > Some questions for the GCC steering committee:
> >
> > * is this JIT work a good thing? (I think so, obviously, but can I go
> > ahead and e.g. add it to the wiki under "Curren
On 10/10/13 07:31, BELBACHIR Selim wrote:
Why GCC doesn't see, in this case, that it's not safe to fill the delay slot
with my compare insn (which is a parallel RTX which clobber one register used
in fallthrough branch) ?
Is a processor 'annuled jump strategy' mandatory to handle delay slot of
> Hi,
>
> I have found an ICE reported as (PR 58682) and I have a fix.
Cool :)
> However the testcase involved:
> * compiling a 5 .i files with -fprofile-generate=
> * running the executable
> * compiling the same 5 .i files with -fprofile-use=, and only then getting
> the ICE.
>
> Is there any
Hi,
I have found an ICE reported as (PR 58682) and I have a fix.
However the testcase involved:
* compiling a 5 .i files with -fprofile-generate=
* running the executable
* compiling the same 5 .i files with -fprofile-use=, and only then getting the
ICE.
Is there anything in the GCC testing fram
> Here is a sample of erroneous code :
>
>
> sub 0,$R5,$R1 #compare $R5 to 0 ($R1 is clobbered)
> jmpd.ifCC .L0#conditionnal delayed branch followed by 1
> delay slot sub $R0,$R4,$R0 #compare $R4 to $R0 ($R0 is clobbered)
> problem ..
> -Original Message-
> From: gcc-ow...@gcc.gnu.org [mailto:gcc-ow...@gcc.gnu.org] On Behalf Of David
> Malcolm
> Sent: 09 October 2013 22:32
> To: gcc@gcc.gnu.org
> Subject: libgccjit.so: an embeddable JIT-compilation library based on GCC
>
> As some may have seen I posted a patch to gcc-
On Wed, Oct 9, 2013 at 5:31 PM, David Malcolm wrote:
> Some questions for the GCC steering committee:
>
> * is this JIT work a good thing? (I think so, obviously, but can I go
> ahead and e.g. add it to the wiki under "Current Projects"?)
>
> * do you like the general approach? I'm choosing t
Hi.
As a learning project I have tried to implement "fastcall" for m68k
target. I have largely sneak peeked at the i386 code to do this.
My "fastcall" convention uses d0-d2, a0-a1 and fp0-fp2 for arguments.
This also means that d2 is clubbed by calls to functions using the
"fastcall" ABI. I updat
> -Original Message-
> From: Aldy Hernandez [mailto:al...@redhat.com]
> Sent: Thursday, October 10, 2013 9:19 AM
> To: Iyer, Balaji V
> Cc: Jeff Law; gcc@gcc.gnu.org; r...@redhat.com; Jason Merrill
> (ja...@redhat.com)
> Subject: Re: Cilk Library
>
> On 10/09/13 13:32, Iyer, Balaji V wro
Hi,
I'm porting gcc 4.5.2 on a private processor.
I encountered a problem concerning delay slots of conditionnal branch
instructions (Note : the processor has no 'annuled jump strategy')
Here is my delay slot definition :
(define_delay (eq_attr "type" "jump")
[(and (eq_attr "delaya
On 10/09/13 13:32, Iyer, Balaji V wrote:
Is it OK for trunk?
I would prefer that a consumer of this library be in place before you
commit. That is, until cilk_spawn/sync/etc go in.
On Thu, Oct 10, 2013 at 04:48:05PM +0530, Umesh Kalappa wrote:
> where A has value oxff and B has value 0xee.
If the 16-bit registers overlap the 8-bit ones, then IMNSHO you don't
want to use different register numbers for the pairs, instead you just tell
GCC that HImode values must be put into
Dear Paul ,
Thanks for the inputs and yeah i looked on them and my basic query remains as
Target we are porting has registers like A and B of 8 bits and used in asm as
ld A,0xff
ld B,0xff
where A and B has value 0xff and AB can be used as pair like 16 bits as
ld AB,0xeeff
where A has val
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