delay slot of conditionnal branch with no annuled jump strategy

[BELBACHIR Selim]

Hi,

I'm porting gcc 4.5.2 on a private processor.
I encountered a problem concerning delay slots of conditionnal branch 
instructions (Note : the processor has no 'annuled jump strategy')

Here is my delay slot definition :

     (define_delay (eq_attr "type" "jump")
       [(and (eq_attr "delayable" "yes") (eq_attr "length" "1")) (nil) (nil)])



Here is a sample of erroneous code :


        sub 0,$R5,$R1           #compare $R5 to 0 ($R1 is clobbered)
        jmpd.ifCC .L0            #conditionnal delayed branch followed by 1 
delay slot
        sub $R0,$R4,$R0      #compare $R4 to $R0 ($R0 is clobbered)             
   <<<< problem
       ...
        addk 1,$R0,$R0        #increment $R0,   but $R0 was modified by 'sub 
$R0,$R4,$R0' !!!
       ...
   .L0:
        bra.ifLS __chk_fail    #conditionnal call symbol_ref
        

GCC put my compare insn 'sub $R0,$R4,$R0' into the delay slot knowing that $R0 
was clobbered by the compare insn (see the definition below).
It's ok if 'jmpd.ifCC .L7' jumps otherwize it's ko because $R0 is used in the 
fall-through path by 'addk 1,$R0,$R0'.



Here is my compare insn :

     (define_insn "compare"
       [(set (reg:CC CCI_REG)
             (compare:CC
               (match_operand:SI 1 "general_operand"    "g ")
               (match_operand:SI 2 "general_operand"    "g")))
        (clobber (match_operand:SI 0 "register_operand" "=r "))]
       "sub %2,%1,%0"
      [(set_attr "length" "1")
      (set_attr " delayable " "yes")]
     )


I was expecting 'instruction reorganization pass' to produce the following code 
:

        sub 0,$R5,$R1           #compare $R5 to 0 ($R1 is clobbered)
        jmp.ifCC .L0              #conditionnal delayed branch (with 0 delay 
slot)
        ...
        addk 1,$R0,$R0        #increment $R0
        ...
   .L0:
        sub $R0,$R4,$R0       #compare $R4 to $R0 ($R0 is clobbered)
        bra.ifLS __chk_fail    #conditionnal call symbol_ref



Why GCC doesn't see, in this case, that it's not safe to fill the delay slot 
with my compare insn (which is a parallel RTX which clobber one register used 
in fallthrough branch) ?
Is a processor 'annuled jump strategy' mandatory to handle delay slot of 
conditionnal jump instructions ?


   Regards,


Selim Belbachir