Dear Paul ,
Thanks for the inputs and yeah i looked on them and my basic query remains as
Target we are porting has registers like A and B of 8 bits and used in asm as
ld A,0xff
ld B,0xff
where A and B has value 0xff and AB can be used as pair like 16 bits as
ld AB,0xeeff
where A has value oxff and B has value 0xee.
I model the above registers as
enum reg_class { NO_REGS,A_REGS, B_REGS, AB_REGS, GEN_REGS, ALL_REGS,
LIM_REG_CLASSES };
#define REG_CLASS_CONTENTS {{0}, {0x1}, {0x2}, {0x3}, {0x3}, {0x3}}
#define REG_CLASS_NAMES {"NO_REGS",
"A_REGS", /* for A 8 bit register */
"B_REGS", /* for B 8 bit register */
"AB_REGS", /* for AB pair 16 bit register */
"GEN_REGS", /* for A , B 8 bits or AB pair16 bit registers */
"ALL_REGS" } /*for A , B 8 bits or AB pair16 bit registers*/
#define N_REG_CLASSES (int) LIM_REG_CLASSES
#define REGISTER_NAMES \
{"a", "b", "ab" }
i'm not sure i can model reg names like a,b and ab ,where my target
has only 2 register but i named them with names as a,b and ab
,Please correct me and i'm really pardon me for bothering you guys
here.
Thanks and waiting for someone from expert group to through some lights here
~Umesh
On Wed, Oct 9, 2013 at 7:40 PM, <paul_kon...@dell.com> wrote:
>
>
> On Oct 9, 2013, at 5:24 AM, Umesh Kalappa <umesh.kalap...@gmail.com> wrote:
>
> > Dear Group ,
> >
> > We are re-targeting the GCC to the CISC target ,which has the eight
> > 8-bit registers and same register set can used as pair register for
> > 16 bit computation i.e four 16-bits .
> >
> > Any one in the group tell me ,How do i model this requirement using
> > the target macros like
> >
> > REG_CLASS_NAMES and REG_CLASS_CONTENTS etc.
> >
> >
> > Thanks
> > ~Umesh
>
> There probably are other examples, but one you could look at is pdp11, which
> has 16 bit registers that also can be used in even/odd pairs for 32 bit
> operations.
>
> paul
