Link DSPP_2 to the LM_2 and DSPP_3 to the LM_3 mixer blocks.
Fixes: b94747f7d8c7 ("drm/msm/dpu: add support for SM8650 DPU")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/
Link DSPP_2 to the LM_2 and DSPP_3 to the LM_3 mixer blocks.
Fixes: e3b1f369db5a ("drm/msm/dpu: Add X1E80100 support")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/
/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 2 +
8 files changed, 66 insertions(+), 2 deletions(-)
---
base-commit: 4172e9bbb583a2af5f1a3db437caf72a90714ad9
change-id: 20241216-dpu-fix-catalog-63a3bc0db31e
Best regards,
--
Dmitry Baryshkov
Link DSPP_2 to the LM_2 and DSPP_3 to the LM_3 mixer blocks.
Fixes: 05ae91d960fd ("drm/msm/dpu: enable DSPP support on SM8[12]50")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/msm/
Link DSPP_2 to the LM_2 and DSPP_3 to the LM_3 mixer blocks.
Fixes: f5abecfe339e ("drm/msm/dpu: enable DSPP and DSC on sc8180x")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/msm/d
On SDM670 the DPU has two DSPP blocks compared to 4 DSPP blocks on
SDM845. Currently SDM670 just reuses LMs and DSPPs from SDM845. Define
platform-specific configuration for those blocks.
Fixes: e140b7e496b7 ("drm/msm/dpu: Add hw revision 4.1 (SDM670)")
Signed-off-by: Dmitry Baryshkov
---
.../gp
Link DSPP_2 to the LM_2 and DSPP_3 to the LM_3 mixer blocks.
Fixes: 0e91bcbb0016 ("drm/msm/dpu: Add SM8350 to hw catalog")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu
Link DSPP_2 to the LM_2 and DSPP_3 to the LM_3 mixer blocks.
Fixes: 05ae91d960fd ("drm/msm/dpu: enable DSPP support on SM8[12]50")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/msm/
Link DSPP_2 to the LM_2 and DSPP_3 to the LM_3 mixer blocks.
Fixes: efcd0107727c ("drm/msm/dpu: add support for SM8550")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/
On 2024/12/15 21:10, Dmitry Baryshkov wrote:
On Tue, 10 Dec 2024 14:53:51 +0800, Fange Zhang wrote:
This series aims to enable display on the QCS615 platform
1.Add MDSS & DPU support for QCS615
2.Add DSI support for QCS615
QCS615 platform supports DisplayPort, and this feature will be adde
= LM_0,
},
};
---
base-commit: a3d570eace66b4016f2692a6f1045742ee70c6b1
change-id: 20241216-dpu-fix-sm6150-17f0739f8fe0
Best regards,
--
Dmitry Baryshkov
On Fri, Dec 13, 2024 at 05:01:03PM +0530, Akhil P Oommen wrote:
> A612 GPU requires an additional smmu_vote clock. Update the bindings to
> reflect this.
>
> Signed-off-by: Akhil P Oommen
> ---
> .../devicetree/bindings/display/msm/gpu.yaml | 36
> ++
> 1 file changed,
On Fri, Dec 13, 2024 at 05:01:04PM +0530, Akhil P Oommen wrote:
> RGMU a.k.a Reduced Graphics Management Unit is a small state machine
> with the sole purpose of providing IFPC support. Compared to GMU, it
What is IFPC?
> doesn't manage GPU clock, voltage scaling, bw voting or any other
> functio
On 14/12/2024 00:46, Konrad Dybcio wrote:
On 13.12.2024 5:55 PM, Akhil P Oommen wrote:
On 12/13/2024 10:10 PM, neil.armstr...@linaro.org wrote:
On 13/12/2024 17:31, Konrad Dybcio wrote:
On 13.12.2024 5:28 PM, neil.armstr...@linaro.org wrote:
On 13/12/2024 16:37, Konrad Dybcio wrote:
On 13.12
On Fri, 06 Dec 2024 11:43:03 +0200, Dmitry Baryshkov wrote:
> The connector->eld is accessed by the .get_eld() callback. This access
> can collide with the drm_edid_to_eld() updating the data at the same
> time. Add drm_connector.eld_mutex to protect the data from concurrenct
> access.
>
> The ind
From: Rob Clark
On mmu-500, stall-on-fault seems to stall all context banks, causing the
GMU to misbehave. So limit this feature to smmu-v2 for now.
This fixes an issue with an older mesa bug taking outo the system
because of GMU going off into the year.
Signed-off-by: Rob Clark
---
drivers/
On Mon, Dec 16, 2024 at 8:59 AM Connor Abbott wrote:
>
> On Mon, Dec 16, 2024 at 11:55 AM Akhil P Oommen
> wrote:
> >
> > On 12/13/2024 10:40 PM, Antonino Maniscalco wrote:
> > > On 12/13/24 5:50 PM, Akhil P Oommen wrote:
> > >> On 12/12/2024 9:44 PM, Antonino Maniscalco wrote:
> > >>> On 12/12/2
On 12/16/2024 12:33 AM, Arnd Bergmann wrote:
From: Arnd Bergmann
Passing a variable string as a printf style format is potentially
dangerous that -Wformat-security can warn about if enabled. A new
instance just got added:
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c: In function 'dpu_kms_mdp_sna
On 12/13/2024 11:20 PM, Rob Clark wrote:
> On Fri, Dec 13, 2024 at 8:47 AM Akhil P Oommen
> wrote:
>>
>> On 12/12/2024 10:42 PM, Rob Clark wrote:
>>> On Thu, Dec 12, 2024 at 9:08 AM Rob Clark wrote:
On Thu, Dec 12, 2024 at 7:59 AM Akhil P Oommen
wrote:
>
> On 12/5/2024 1
Quoting Dmitry Baryshkov (2024-12-15 14:44:07)
> Use msm_dp_utils_pack_sdp_header() and call msm_dp_write_link() directly
> to program audio packet data. Use 0 as Packet ID, as it was not
> programmed earlier.
>
> Signed-off-by: Dmitry Baryshkov
> ---
Reviewed-by: Stephen Boyd
Tested-by: Stephen
Quoting Dmitry Baryshkov (2024-12-15 14:44:11)
> It's the dp_panel's duty to clear the MMSS_DP_DSC_DTO register. Once DP
> driver gets DSC support, it will handle that register in other places
> too. Split a call to write 0x0 to that register to a separate function.
>
> Signed-off-by: Dmitry Barysh
Quoting Dmitry Baryshkov (2024-12-15 14:44:10)
> The dp_audio module doesn't make any use of the passed DP panel
> instance. Drop the argument.
>
> Signed-off-by: Dmitry Baryshkov
> ---
Reviewed-by: Stephen Boyd
Tested-by: Stephen Boyd # sc7180-trogdor
Quoting Dmitry Baryshkov (2024-12-15 14:44:21)
> Now as the msm_dp_catalog module became nearly empty, drop it, accessing
> registers directly from the corresponding submodules.
>
> Signed-off-by: Dmitry Baryshkov
> ---
Reviewed-by: Stephen Boyd
Tested-by: Stephen Boyd # sc7180-trogdor
On Mon, Dec 16, 2024 at 12:28 PM Akhil P Oommen
wrote:
>
> On 12/16/2024 10:40 PM, Rob Clark wrote:
> > From: Rob Clark
> >
> > On mmu-500, stall-on-fault seems to stall all context banks, causing the
> > GMU to misbehave. So limit this feature to smmu-v2 for now.
> >
> > This fixes an issue wit
On 12/16/2024 12:27 AM, Dmitry Baryshkov wrote:
Link DSPP_2 to the LM_2 and DSPP_3 to the LM_3 mixer blocks.
Fixes: 05ae91d960fd ("drm/msm/dpu: enable DSPP support on SM8[12]50")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 2 ++
1 file chan
On 12/16/2024 12:27 AM, Dmitry Baryshkov wrote:
Link DSPP_2 to the LM_2 and DSPP_3 to the LM_3 mixer blocks.
Fixes: f5abecfe339e ("drm/msm/dpu: enable DSPP and DSC on sc8180x")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 2 ++
1 file chang
For the nouveau portions:
Reviewed-by: Lyude Paul
On Sat, 2024-12-14 at 15:37 +0200, Dmitry Baryshkov wrote:
> The mode_valid() callbacks of drm_encoder, drm_crtc and drm_bridge
> take a const struct drm_display_mode argument. Change the mode_valid
> callback of drm_connector to also take a cons
On 12/16/2024 10:28 PM, Connor Abbott wrote:
> On Mon, Dec 16, 2024 at 11:55 AM Akhil P Oommen
> wrote:
>>
>> On 12/13/2024 10:40 PM, Antonino Maniscalco wrote:
>>> On 12/13/24 5:50 PM, Akhil P Oommen wrote:
On 12/12/2024 9:44 PM, Antonino Maniscalco wrote:
> On 12/12/24 4:58 PM, Akhil P
Reviewed-by: Lyude Paul
On Sat, 2024-12-14 at 15:37 +0200, Dmitry Baryshkov wrote:
> The mode_valid() callbacks of drm_encoder, drm_crtc and drm_bridge
> accept const struct drm_display_mode argument. Change the mode_valid
> callback of drm_encoder_slave to also accept const argument.
>
> Review
On 12/16/2024 10:40 PM, Rob Clark wrote:
> From: Rob Clark
>
> On mmu-500, stall-on-fault seems to stall all context banks, causing the
> GMU to misbehave. So limit this feature to smmu-v2 for now.
>
> This fixes an issue with an older mesa bug taking outo the system
> because of GMU going off
On Mon, Dec 16, 2024 at 12:25 PM Akhil P Oommen
wrote:
>
> On 12/16/2024 10:28 PM, Connor Abbott wrote:
> > On Mon, Dec 16, 2024 at 11:55 AM Akhil P Oommen
> > wrote:
> >>
> >> On 12/13/2024 10:40 PM, Antonino Maniscalco wrote:
> >>> On 12/13/24 5:50 PM, Akhil P Oommen wrote:
> On 12/12/2024
On 12/15/2024 2:44 PM, Dmitry Baryshkov wrote:
There is little point in rereading DP controller revision over and over
again. Read it once, after the first software reset and propagate it to
the dp_panel module.
Good idea, can be posted even separately in front of the catalog rework
as it
On 12/14/2024 2:05 PM, Dmitry Baryshkov wrote:
On Sat, 14 Dec 2024 at 22:53, Abhinav Kumar wrote:
Hi Dmitry
On 12/12/2024 3:09 PM, Dmitry Baryshkov wrote:
On Thu, 12 Dec 2024 at 21:15, Abhinav Kumar wrote:
On 12/12/2024 12:52 AM, Dmitry Baryshkov wrote:
On Thu, 12 Dec 2024 at 04:59,
Reviewed-by: Lyude Paul
On Wed, 2024-12-11 at 15:04 +0200, Abel Vesa wrote:
> LTTPRs operating modes are defined by the DisplayPort standard and the
> generic framework now provides a helper to switch between them, which
> is handling the explicit disabling of non-transparent mode and its
> disab
On 12/16/2024 12:27 AM, Dmitry Baryshkov wrote:
Link DSPP_2 to the LM_2 and DSPP_3 to the LM_3 mixer blocks.
Fixes: 0e91bcbb0016 ("drm/msm/dpu: Add SM8350 to hw catalog")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 2 ++
1 file changed, 2 i
On 12/16/2024 12:27 AM, Dmitry Baryshkov wrote:
Link DSPP_2 to the LM_2 and DSPP_3 to the LM_3 mixer blocks.
Fixes: 05ae91d960fd ("drm/msm/dpu: enable DSPP support on SM8[12]50")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 2 ++
1 file chan
On Mon, Dec 16, 2024 at 01:11:35PM -0800, Abhinav Kumar wrote:
>
>
> On 12/16/2024 12:27 AM, Dmitry Baryshkov wrote:
> > Link DSPP_2 to the LM_2 and DSPP_3 to the LM_3 mixer blocks.
> >
> > Fixes: 05ae91d960fd ("drm/msm/dpu: enable DSPP support on SM8[12]50")
> > Signed-off-by: Dmitry Baryshkov
implementation for lm_pair, its used even to
> decide the LM pair for CWB mux. Upstream has a simpler implementation of
> just doing that in the code of using ODD LMs for ODD CWB muxes and even LMs
> for even CWB muxes. So fix is okay but not needed.
So which topology is supposed to work with LM_0 / LM_2 pair?
I'd still prefer to land the fix for the sake of catalog having the
correct data.
>
> >
> > ---
> > base-commit: a3d570eace66b4016f2692a6f1045742ee70c6b1
> > change-id: 20241216-dpu-fix-sm6150-17f0739f8fe0
> >
> > Best regards,
--
With best wishes
Dmitry
On Mon, Dec 16, 2024 at 11:32:57AM -0800, Abhinav Kumar wrote:
>
>
> On 12/15/2024 2:44 PM, Dmitry Baryshkov wrote:
> > Use msm_dp_utils_pack_sdp_header() and call msm_dp_write_link() directly
> > to program audio packet data. Use 0 as Packet ID, as it was not
> > programmed earlier.
> >
> > Sig
On Mon, Dec 16, 2024 at 11:46:21AM -0800, Abhinav Kumar wrote:
>
>
> On 12/15/2024 2:44 PM, Dmitry Baryshkov wrote:
> > It's the dp_panel's duty to clear the MMSS_DP_DSC_DTO register. Once DP
> > driver gets DSC support, it will handle that register in other places
> > too. Split a call to write
On 12/16/2024 12:27 AM, Dmitry Baryshkov wrote:
Link DSPP_2 to the LM_2 and DSPP_3 to the LM_3 mixer blocks.
Fixes: efcd0107727c ("drm/msm/dpu: add support for SM8550")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 2 ++
1 file changed, 2 ins
On 12/16/2024 12:27 AM, Dmitry Baryshkov wrote:
Link DSPP_2 to the LM_2 and DSPP_3 to the LM_3 mixer blocks.
Fixes: b94747f7d8c7 ("drm/msm/dpu: add support for SM8650 DPU")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 2 ++
1 file changed,
On 12/16/2024 2:21 PM, Dmitry Baryshkov wrote:
On Mon, Dec 16, 2024 at 01:11:35PM -0800, Abhinav Kumar wrote:
On 12/16/2024 12:27 AM, Dmitry Baryshkov wrote:
Link DSPP_2 to the LM_2 and DSPP_3 to the LM_3 mixer blocks.
Fixes: 05ae91d960fd ("drm/msm/dpu: enable DSPP support on SM8[12]50")
On 12/16/2024 12:27 AM, Dmitry Baryshkov wrote:
Link DSPP_2 to the LM_2 and DSPP_3 to the LM_3 mixer blocks.
Fixes: e3b1f369db5a ("drm/msm/dpu: Add X1E80100 support")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 2 ++
1 file changed, 2 ins
On Mon, Dec 16, 2024 at 11:16:11AM -0800, Abhinav Kumar wrote:
>
>
> On 12/13/2024 12:38 PM, Dmitry Baryshkov wrote:
> > On Fri, 13 Dec 2024 at 21:15, Abhinav Kumar
> > wrote:
> > >
> > >
> > >
> > > On 12/12/2024 5:05 PM, Dmitry Baryshkov wrote:
> > > > On Thu, Dec 12, 2024 at 11:11:54AM -0
On Mon, Dec 16, 2024 at 12:45:13PM -0800, Abhinav Kumar wrote:
>
>
> On 12/14/2024 2:05 PM, Dmitry Baryshkov wrote:
> > On Sat, 14 Dec 2024 at 22:53, Abhinav Kumar
> > wrote:
> > >
> > > Hi Dmitry
> > >
> > > On 12/12/2024 3:09 PM, Dmitry Baryshkov wrote:
> > > > On Thu, 12 Dec 2024 at 21:15,
On 12/16/2024 2:24 PM, Dmitry Baryshkov wrote:
On Mon, Dec 16, 2024 at 11:32:57AM -0800, Abhinav Kumar wrote:
On 12/15/2024 2:44 PM, Dmitry Baryshkov wrote:
Use msm_dp_utils_pack_sdp_header() and call msm_dp_write_link() directly
to program audio packet data. Use 0 as Packet ID, as it was
On 12/16/2024 12:27 AM, Dmitry Baryshkov wrote:
On SDM670 the DPU has two DSPP blocks compared to 4 DSPP blocks on
SDM845. Currently SDM670 just reuses LMs and DSPPs from SDM845. Define
platform-specific configuration for those blocks.
Fixes: e140b7e496b7 ("drm/msm/dpu: Add hw revision 4.1 (S
change-id: 20241216-dpu-fix-catalog-63a3bc0db31e
Best regards,
On 12/16/2024 2:24 PM, Dmitry Baryshkov wrote:
On Mon, Dec 16, 2024 at 11:46:21AM -0800, Abhinav Kumar wrote:
On 12/15/2024 2:44 PM, Dmitry Baryshkov wrote:
It's the dp_panel's duty to clear the MMSS_DP_DSC_DTO register. Once DP
driver gets DSC support, it will handle that register in othe
On Mon, Dec 16, 2024 at 10:12 AM Dmitry Baryshkov
wrote:
>
> On Mon, 16 Dec 2024 at 16:53, Harry Wentland wrote:
> >
> >
> >
> > On 2024-12-10 16:20, Dmitry Baryshkov wrote:
> > > On Fri, Dec 06, 2024 at 11:43:07AM +0200, Dmitry Baryshkov wrote:
> > >> Reading access to connector->eld can happen
On Mon, Dec 16, 2024 at 01:24:29PM +0200, Dmitry Baryshkov wrote:
> On Fri, Dec 06, 2024 at 11:43:03AM +0200, Dmitry Baryshkov wrote:
> > The connector->eld is accessed by the .get_eld() callback. This access
> > can collide with the drm_edid_to_eld() updating the data at the same
> > time. Add drm
On Fri, Dec 06, 2024 at 04:48:43PM -0800, Jessica Zhang wrote:
> On 9/25/2024 12:23 AM, Maxime Ripard wrote:
> > On Tue, Sep 24, 2024 at 03:59:18PM GMT, Jessica Zhang wrote:
> > > Check that all encoders attached to a given CRTC are valid
> > > possible_clones of each other.
> > >
> > > Signed-off
On 2024-12-10 16:20, Dmitry Baryshkov wrote:
> On Fri, Dec 06, 2024 at 11:43:07AM +0200, Dmitry Baryshkov wrote:
>> Reading access to connector->eld can happen at the same time the
>> drm_edid_to_eld() updates the data. Take the newly added eld_mutex in
>> order to protect connector->eld from co
On Mon, 16 Dec 2024 at 16:53, Harry Wentland wrote:
>
>
>
> On 2024-12-10 16:20, Dmitry Baryshkov wrote:
> > On Fri, Dec 06, 2024 at 11:43:07AM +0200, Dmitry Baryshkov wrote:
> >> Reading access to connector->eld can happen at the same time the
> >> drm_edid_to_eld() updates the data. Take the new
On Mon, 16 Dec 2024 at 17:32, Alex Deucher wrote:
>
> On Mon, Dec 16, 2024 at 10:12 AM Dmitry Baryshkov
> wrote:
> >
> > On Mon, 16 Dec 2024 at 16:53, Harry Wentland wrote:
> > >
> > >
> > >
> > > On 2024-12-10 16:20, Dmitry Baryshkov wrote:
> > > > On Fri, Dec 06, 2024 at 11:43:07AM +0200, Dmit
From: Arnd Bergmann
Passing a variable string as a printf style format is potentially
dangerous that -Wformat-security can warn about if enabled. A new
instance just got added:
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c: In function 'dpu_kms_mdp_snapshot':
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c:10
On Mon, Dec 16, 2024 at 09:33:13AM +0100, Arnd Bergmann wrote:
> From: Arnd Bergmann
>
> Passing a variable string as a printf style format is potentially
> dangerous that -Wformat-security can warn about if enabled. A new
> instance just got added:
>
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c: I
On 16/12/2024 11:40, Akhil P Oommen wrote:
On 12/16/2024 3:13 PM, neil.armstr...@linaro.org wrote:
On 14/12/2024 00:46, Konrad Dybcio wrote:
On 13.12.2024 5:55 PM, Akhil P Oommen wrote:
On 12/13/2024 10:10 PM, neil.armstr...@linaro.org wrote:
On 13/12/2024 17:31, Konrad Dybcio wrote:
On 13.1
On 12/16/2024 3:13 PM, neil.armstr...@linaro.org wrote:
> On 14/12/2024 00:46, Konrad Dybcio wrote:
>> On 13.12.2024 5:55 PM, Akhil P Oommen wrote:
>>> On 12/13/2024 10:10 PM, neil.armstr...@linaro.org wrote:
On 13/12/2024 17:31, Konrad Dybcio wrote:
> On 13.12.2024 5:28 PM, neil.armstr...
On Fri, Dec 06, 2024 at 11:43:03AM +0200, Dmitry Baryshkov wrote:
> The connector->eld is accessed by the .get_eld() callback. This access
> can collide with the drm_edid_to_eld() updating the data at the same
> time. Add drm_connector.eld_mutex to protect the data from concurrenct
> access.
>
> T
On 12/13/2024 10:40 PM, Antonino Maniscalco wrote:
> On 12/13/24 5:50 PM, Akhil P Oommen wrote:
>> On 12/12/2024 9:44 PM, Antonino Maniscalco wrote:
>>> On 12/12/24 4:58 PM, Akhil P Oommen wrote:
On 12/5/2024 10:24 PM, Rob Clark wrote:
> From: Rob Clark
>
> Performance counter usa
On Mon, Dec 16, 2024 at 11:55 AM Akhil P Oommen
wrote:
>
> On 12/13/2024 10:40 PM, Antonino Maniscalco wrote:
> > On 12/13/24 5:50 PM, Akhil P Oommen wrote:
> >> On 12/12/2024 9:44 PM, Antonino Maniscalco wrote:
> >>> On 12/12/24 4:58 PM, Akhil P Oommen wrote:
> On 12/5/2024 10:24 PM, Rob Cla
Quoting Dmitry Baryshkov (2024-12-15 14:44:20)
> There is little point in rereading DP controller revision over and over
> again. Read it once, after the first software reset and propagate it to
> the dp_panel module.
>
> Signed-off-by: Dmitry Baryshkov
> ---
Reviewed-by: Stephen Boyd
Tested-by:
On 12/13/2024 12:38 PM, Dmitry Baryshkov wrote:
On Fri, 13 Dec 2024 at 21:15, Abhinav Kumar wrote:
On 12/12/2024 5:05 PM, Dmitry Baryshkov wrote:
On Thu, Dec 12, 2024 at 11:11:54AM -0800, Jessica Zhang wrote:
Filter out modes that have a clock rate greater than the max core clock
rate w
just doing that in the code of using ODD LMs for ODD CWB muxes and even
LMs for even CWB muxes. So fix is okay but not needed.
---
base-commit: a3d570eace66b4016f2692a6f1045742ee70c6b1
change-id: 20241216-dpu-fix-sm6150-17f0739f8fe0
Best regards,
On 12/15/2024 2:44 PM, Dmitry Baryshkov wrote:
Use msm_dp_utils_pack_sdp_header() and call msm_dp_write_link() directly
to program audio packet data. Use 0 as Packet ID, as it was not
programmed earlier.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dp/dp_audio.c | 268 ++--
On 2024-12-16 10:31, Alex Deucher wrote:
> On Mon, Dec 16, 2024 at 10:12 AM Dmitry Baryshkov
> wrote:
>>
>> On Mon, 16 Dec 2024 at 16:53, Harry Wentland wrote:
>>>
>>>
>>>
>>> On 2024-12-10 16:20, Dmitry Baryshkov wrote:
On Fri, Dec 06, 2024 at 11:43:07AM +0200, Dmitry Baryshkov wrote:
>>
On 12/15/2024 2:44 PM, Dmitry Baryshkov wrote:
Drop obsolete functions to access audio packet headers. The dp_audio.c
now writes them using msm_dp_write_link() directly.
Reviewed-by: Stephen Boyd
Tested-by: Stephen Boyd # sc7180-trogdor
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm
On 12/15/2024 2:44 PM, Dmitry Baryshkov wrote:
It's the dp_panel's duty to clear the MMSS_DP_DSC_DTO register. Once DP
driver gets DSC support, it will handle that register in other places
too. Split a call to write 0x0 to that register to a separate function.
Signed-off-by: Dmitry Baryshkov
On 12/16/2024 6:47 AM, Maxime Ripard wrote:
On Fri, Dec 06, 2024 at 04:48:43PM -0800, Jessica Zhang wrote:
On 9/25/2024 12:23 AM, Maxime Ripard wrote:
On Tue, Sep 24, 2024 at 03:59:18PM GMT, Jessica Zhang wrote:
Check that all encoders attached to a given CRTC are valid
possible_clones of e
On 12/15/2024 2:44 PM, Dmitry Baryshkov wrote:
The dp_audio module doesn't make any use of the passed DP panel
instance. Drop the argument.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dp/dp_audio.c | 3 +--
drivers/gpu/drm/msm/dp/dp_audio.h | 3 ---
drivers/gpu/drm/msm/dp
On 12/16/2024 6:27 AM, Simona Vetter wrote:
On Sun, Dec 15, 2024 at 06:19:08PM -0800, Abhinav Kumar wrote:
Hi Maxime
Gentle reminder on this one.
We are looking for some advice on how to go about KUnit for this static
function.
Please help with our question below.
Thanks
Abhinav
On 12/6
On 12/15/2024 2:44 PM, Dmitry Baryshkov wrote:
Having I/O regions inside a msm_dp_catalog_private() results in extra
layers of one-line wrappers for accessing the data. Move I/O region base
and size to the globally visible struct msm_dp_catalog.
Reviewed-by: Stephen Boyd
Tested-by: Stephen B
On 12/16/2024 4:43 PM, Jessica Zhang wrote:
From: Dmitry Baryshkov
Stop poking into CRTC state from dpu_encoder.c, fill CRTC HW resources
from dpu_crtc_assign_resources().
Signed-off-by: Dmitry Baryshkov
[quic_abhin...@quicinc.com: cleaned up formatting]
Signed-off-by: Abhinav Kumar
Signe
On 12/16/2024 4:43 PM, Jessica Zhang wrote:
From: Dmitry Baryshkov
All resource allocation is centered around the LMs. Then other blocks
(except DSCs) are allocated basing on the LMs that was selected, and LM
powers up the CRTC rather than the encoder.
Moreover if at some point the driver s
On 12/16/2024 4:43 PM, Jessica Zhang wrote:
Add a common helper to check if the given CRTC state is in clone mode.
This can be used by drivers to help detect if a CRTC is being shared by
multiple encoders
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/drm_crtc.c | 20
The CWB mux has a pending flush bit and *_active register.
Add support for configuring them within the dpu_hw_ctl layer.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 13 ++
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys
On Mon, Dec 16, 2024 at 04:43:16PM -0800, Jessica Zhang wrote:
> From: Dmitry Baryshkov
>
> The struct dpu_rm_requirements was used to wrap display topology and
> hw resources, which meant INTF indices. As of commit ef58e0ad3436
> ("drm/msm/dpu: get INTF blocks directly rather than through RM") t
On 12/16/2024 4:43 PM, Jessica Zhang wrote:
Add kunit test to validate drm_crtc_in_clone_mode() helper
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/tests/drm_atomic_state_test.c | 62 ++-
1 file changed, 61 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu
On 12/16/2024 5:26 PM, Dmitry Baryshkov wrote:
On Mon, Dec 16, 2024 at 04:43:16PM -0800, Jessica Zhang wrote:
From: Dmitry Baryshkov
The struct dpu_rm_requirements was used to wrap display topology and
hw resources, which meant INTF indices. As of commit ef58e0ad3436
("drm/msm/dpu: get INTF
;has_3d_merge)
topology.num_lm = 1;
---
base-commit: a3d570eace66b4016f2692a6f1045742ee70c6b1
change-id: 20241216-dpu-fix-sm6150-17f0739f8fe0
Best regards,
Starting the frame done timer before the encoder is finished kicking off
can lead to unnecessary frame done timeouts when the device is
experiencing heavy load (ex. when debug logs are enabled).
Thus, create a separate API for starting the encoder frame done timer and
call it after the encoder kic
Cache the CWB block mask in the DPU virtual encoder and configure CWB
according to the CWB block mask within the writeback phys encoder
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 75 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.
From: Esha Bharadwaj
Adjust the WB_MUX configuration to account for using dedicated CWB
pingpong blocks.
Signed-off-by: Esha Bharadwaj
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletio
From: Dmitry Baryshkov
Stop poking into CRTC state from dpu_encoder.c, fill CRTC HW resources
from dpu_crtc_assign_resources().
Signed-off-by: Dmitry Baryshkov
[quic_abhin...@quicinc.com: cleaned up formatting]
Signed-off-by: Abhinav Kumar
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm
Add kunit test to validate drm_crtc_in_clone_mode() helper
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/tests/drm_atomic_state_test.c | 62 ++-
1 file changed, 61 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/tests/drm_atomic_state_test.c
b/drivers/gpu/d
We cannot support both CWB and CDM simultaneously as this would require
2 CDM blocks and currently our hardware only supports 1 CDM block at
most.
Thus return an error if both CWB and CDM are enabled.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 4
1 file cha
If the clone mode enabled status is changing, a modeset needs to happen
so that the resources can be reassigned
Signed-off-by: Jessica Zhang
---
NOTE: As noted by Sima in the v1 [1], the DPU driver doesn't handle
crtc_state->mode_changed correctly. However, fixing this is out of the
scope of thi
From: Esha Bharadwaj
Implement instance of snapshot function to dump new registers used
for cwb
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Esha Bharadwaj
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/driver
For concurrent writeback, the real time encoder is responsible for
trigger flush and trigger start. Return early for trigger start and
trigger flush for the concurrent writeback encoders.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
From: Dmitry Baryshkov
All resource allocation is centered around the LMs. Then other blocks
(except DSCs) are allocated basing on the LMs that was selected, and LM
powers up the CRTC rather than the encoder.
Moreover if at some point the driver supports encoder cloning,
allocating resources fro
Add support for allocating the concurrent writeback mux as part of the
WB allocation
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 16 +++-
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 2 ++
2 files changed, 17 insertions(+), 1
Adjust QoS remapper, OT limit, and CDP parameters to account for
concurrent writeback
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/dr
Add the cwb_enabled flag to msm_display topology and adjust the toplogy
to account for concurrent writeback
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 11 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 10 --
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
DPU supports a single writeback session running concurrently with primary
display when the CWB mux is configured properly. This series enables
clone mode for DPU driver and adds support for programming the CWB mux
in cases where the hardware has dedicated CWB pingpong blocks. Currently,
the CWB har
Add a common helper to check if the given CRTC state is in clone mode.
This can be used by drivers to help detect if a CRTC is being shared by
multiple encoders
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/drm_crtc.c | 20
include/drm/drm_crtc.h | 2 +-
2 files chan
From: Esha Bharadwaj
Add a new block for concurrent writeback mux to the SM8650 HW catalog
Signed-off-by: Esha Bharadwaj
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 21 +
drivers/gpu/drm/msm/disp/dpu
Check that all encoders attached to a given CRTC are valid
possible_clones of each other.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/drm_atomic_helper.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic_helper.c
b/drivers/gpu/drm/
Add a test for drm_atomic_check_modeset() specifically to validate
drm_atomic_check_valid_clones() helper
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/tests/drm_atomic_state_test.c | 71 +++
1 file changed, 71 insertions(+)
diff --git a/drivers/gpu/drm/tests/drm_atom
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