[PATCH v4 09/25] drm/msm/dpu: Add CWB entry to catalog for SM8650

[Jessica Zhang]

From: Esha Bharadwaj <quic_ebhar...@quicinc.com>

Add a new block for concurrent writeback mux to the SM8650 HW catalog

Signed-off-by: Esha Bharadwaj <quic_ebhar...@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.barysh...@linaro.org>
Signed-off-by: Jessica Zhang <quic_jessz...@quicinc.com>
---
 .../gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 21 +++++++++++++++++++++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h      | 13 +++++++++++++
 2 files changed, 34 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h 
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
index 
eb5dfff2ec4f48d793f9d83aafed592d0947f04b..33f5faf4833f7534a1403ccec560fffe8ea0bb1f
 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
@@ -350,6 +350,25 @@ static const struct dpu_wb_cfg sm8650_wb[] = {
        },
 };
 
+static const struct dpu_cwb_cfg sm8650_cwb[] = {
+       {
+               .name = "cwb_0", .id = CWB_0,
+               .base = 0x66200, .len = 0x8,
+       },
+       {
+               .name = "cwb_1", .id = CWB_1,
+               .base = 0x66600, .len = 0x8,
+       },
+       {
+               .name = "cwb_2", .id = CWB_2,
+               .base = 0x7E200, .len = 0x8,
+       },
+       {
+               .name = "cwb_3", .id = CWB_3,
+               .base = 0x7E600, .len = 0x8,
+       },
+};
+
 static const struct dpu_intf_cfg sm8650_intf[] = {
        {
                .name = "intf_0", .id = INTF_0,
@@ -447,6 +466,8 @@ const struct dpu_mdss_cfg dpu_sm8650_cfg = {
        .merge_3d = sm8650_merge_3d,
        .wb_count = ARRAY_SIZE(sm8650_wb),
        .wb = sm8650_wb,
+       .cwb_count = ARRAY_SIZE(sm8650_cwb),
+       .cwb = sm8650_cwb,
        .intf_count = ARRAY_SIZE(sm8650_intf),
        .intf = sm8650_intf,
        .vbif_count = ARRAY_SIZE(sm8650_vbif),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 
c701d18c3522393b7d18d085d6554119f27f737b..a407b522282bf07a12cd3af8febff8d91f52b8da
 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -613,6 +613,16 @@ struct dpu_wb_cfg {
        enum dpu_clk_ctrl_type clk_ctrl;
 };
 
+/*
+ * struct dpu_cwb_cfg : MDP CWB mux instance info
+ * @id:                enum identifying this block
+ * @base:              register base offset to mdss
+ * @features           bit mask identifying sub-blocks/features
+ */
+struct dpu_cwb_cfg {
+       DPU_HW_BLK_INFO;
+};
+
 /**
  * struct dpu_vbif_dynamic_ot_cfg - dynamic OT setting
  * @pps                pixel per seconds
@@ -815,6 +825,9 @@ struct dpu_mdss_cfg {
        u32 dspp_count;
        const struct dpu_dspp_cfg *dspp;
 
+       u32 cwb_count;
+       const struct dpu_cwb_cfg *cwb;
+
        /* Add additional block data structures here */
 
        const struct dpu_perf_cfg *perf;

-- 
2.34.1