Continue migration to the MDSS-revision based checks and replace
DPU_INTF_INPUT_CTRL feature bit with the core_major_ver >= 5 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h |
Continue migration to the MDSS-revision based checks and replace
DPU_DATA_HCTL_EN feature bit with the core_major_ver >= 5 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 ---
drivers/gpu/drm/ms
Continue migration to the MDSS-revision based checks and replace
DPU_CTL_HAS_LAYER_EXT4 feature bit with the core_major_ver >= 9 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 12 ++--
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm
The SM8450 and later chips have DPU_MDP_PERIPH_0_REMOVED feature bit
set, which means that those platforms have dropped some of the
registers, including the WD TIMER-related ones. Stop providing the
callback to program WD timer on those platforms.
Fixes: 100d7ef6995d ("drm/msm/dpu: add support for
Inline the _setup_dsc_ops() function, it makes it easier to handle
different conditions involving DSC configuration.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 17 ++---
1 file changed, 6 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/d
The INTF_SC7280_MASK is equal to the INTF_SC7180_MASK. Stop defining a
separate symbol and use the INTF_SC7180_MASK instead.
Signed-off-by: Dmitry Baryshkov
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h| 8
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 8 -
| 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 4 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 17 ++-
50 files changed, 295 insertions(+), 836 deletions(-)
---
base-commit: 789384eb1437aed94155dc0eac8a8a6ba1baf578
change-id: 20241213-dpu-drop-features-7603dc3ee1
Several DPU 5.x platforms are supposed to be using DPU_WB_INPUT_CTRL,
to bind WB and PINGPONG blocks, but they do not. Change those platforms
to use WB_SM8250_MASK, which includes that bit.
Fixes: 1f5bcc4316b3 ("drm/msm/dpu: enable writeback on SC8108X")
Fixes: ab2b03d73a66 ("drm/msm/dpu: enable w
Continue migration to the MDSS-revision based checks and replace
DPU_DSC_HW_REV_1_2 feature bit with the core_major_ver >= 7 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 10 --
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
Stop declaring DPU_DSPP_PCC as a part of the DSPP features, use the
presence of the PCC sblk to check whether PCC is present in the hardware
or not.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_
Inline the _setup_mixer_ops() function, it makes it easier to handle
different conditions involving LM configuration.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 24 +---
1 file changed, 9 insertions(+), 15 deletions(-)
diff --git a/driver
Continue migration to the MDSS-revision based checks and replace
DPU_CTL_FETCH_ACTIVE feature bit with the core_major_ver >= 7 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 --
drivers/gpu/drm
Continue migration to the MDSS-revision based checks and replace
DPU_CTL_VM_CFG feature bit with the core_major_ver >= 7 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 8 ++--
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 8
Continue migration to the MDSS-revision based checks and replace
DPU_INTF_STATUS_SUPPORTED feature bit with the core_major_ver >= 5
check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 --
drivers/gp
Inline the _setup_dspp_ops() function, it makes it easier to handle
different conditions involving DSPP configuration.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c | 10 ++
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/ms
Continue migration to the MDSS-revision based checks and replace
DPU_CTL_DSPP_SUB_BLOCK_FLUSH feature bit with the core_major_ver >= 7
check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 --
drivers
Continue migration to the MDSS-revision based checks and replace
DPU_CTL_ACTIVE_CFG feature bit with the core_major_ver >= 5 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 8 ++--
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h |
Continue cleanup of the feature flags and replace the last remaining CTL
feature with a bitfield flag, simplifying corresponding data structures
and access.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 6 +++---
drivers/gpu/drm/msm/disp/dpu1/cat
Only SSPP, WB and VBIF still have feature bits remaining, all other
hardware blocks don't have feature bits anymore. Remove the 'features'
from the DPU_HW_BLK_INFO so that it doesn't get included into hw info
structures by default and only include it when necessary.
Signed-off-by: Dmitry Baryshkov
Continue cleanup of the feature flags and replace the last remaining LM
feature with a bitfield flag, simplifying corresponding data structures
and access.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 8
drivers/gpu/drm/msm/disp/dpu1/ca
Continue cleanup of the feature flags and replace the last remaining LM
feature with a bitfield flag, simplifying corresponding data structures
and access.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 12 ++--
drivers/gpu/drm/msm/disp/dpu
Continue migration to the MDSS-revision based checks and replace
DPU_SSPP_QOS_8LVL feature bit with the core_major_ver >= 4 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 6 +++---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 --
drivers/gpu/drm
Continue migration to the MDSS-revision based checks and replace
DPU_DSC_OUTPUT_CTRL feature bit with the core_major_ver >= 5 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 6 -
The DPU_PINGPONG_TE2 is unused by the current code (and can further be
replaced by the checking for the te2 sblk presense). Other feature bits
are completely unused. Drop them from the current codebase.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h |
Continue migration to the MDSS-revision based checks and replace
DPU_MDP_AUDIO_SELECT feature bit with the core_major_ver == 8 ||
core_major_ver == 5 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dp
Continue migration to the MDSS-revision based checks and replace
DPU_MIXER_COMBINED_ALPHA feature bit with the core_major_ver >= 4 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 4 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 --
drivers/gp
Drop unused LM features from the current codebase.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw
Drop unused MDP TOP features from the current codebase.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 13 -
1 file changed, 13 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cata
Continue migration to the MDSS-revision based checks and replace
DPU_WB_INPUT_CTRL feature bit with the core_major_ver >= 5 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 2 +-
Continue migration to the MDSS-revision based checks and replace
DPU_PINGPONG_DSC feature bit with the core_major_ver < 7 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h | 2 --
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h | 1 -
Continue migration to the MDSS-revision based checks and replace
DPU_PINGPONG_DITHER feature bit with the core_major_ver >= 3 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 10 --
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998
Continue migration to the MDSS-revision based checks and replace
DPU_MDP_VSYNC_SEL feature bit with the core_major_ver < 5 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h | 1 -
dr
Inline the _setup_ctl_ops() function, it makes it easier to handle
different conditions involving CTL configuration.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 96 ++
1 file changed, 46 insertions(+), 50 deletions(-)
diff --git a
Continue migration to the MDSS-revision based checks and replace
DPU_MDP_PERIPH_0_REMOVED feature bit with the core_major_ver >= 8 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h |
Continue migration to the MDSS-revision based checks and drop the
DPU_DIM_LAYER feature bit. It is currently unused, but can be replaed
with the core_major_ver >= 4 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 2 --
drivers/gpu/drm/msm/disp
From: Jie Zhang
Add support for Adreno 612 GPU found in SM6150/QCS615 chipsets.
A612 falls under ADRENO_6XX_GEN1 family and is a cut down version
of A615 GPU.
A612 has a new IP called Reduced Graphics Management Unit or RGMU
which is a small state machine which helps to toggle GX GDSC
(connected
On 2024/12/10 19:02, Dmitry Baryshkov wrote:
On Tue, Dec 10, 2024 at 02:54:00PM +0800, Fange Zhang wrote:
From: Li Liu
Add display MDSS and DSI configuration for QCS615 RIDE board.
QCS615 has a DP port, and DP support will be added in a later patch.
Signed-off-by: Li Liu
Signed-off-by: Fa
On Fri, 13 Dec 2024 at 11:21, fange zhang wrote:
>
>
>
> On 2024/12/10 19:02, Dmitry Baryshkov wrote:
> > On Tue, Dec 10, 2024 at 02:54:00PM +0800, Fange Zhang wrote:
> >> From: Li Liu
> >>
> >> Add display MDSS and DSI configuration for QCS615 RIDE board.
> >> QCS615 has a DP port, and DP suppor
On 13.12.2024 11:35 AM, Akhil P Oommen wrote:
> RGMU a.k.a Reduced Graphics Management Unit is a small state machine
> with the sole purpose of providing IFPC support. Compared to GMU, it
> doesn't manage GPU clock, voltage scaling, bw voting or any other
> functionalities. All it does is detect an
On 13.12.2024 11:35 AM, Akhil P Oommen wrote:
> From: Jie Zhang
>
> Add gpu and gmu nodes for qcs615 chipset.
>
> Signed-off-by: Jie Zhang
> Signed-off-by: Akhil P Oommen
> Reviewed-by: Dmitry Baryshkov
> ---
> arch/arm64/boot/dts/qcom/qcs615.dtsi | 88
>
On 13.12.2024 11:35 AM, Akhil P Oommen wrote:
> From: Jie Zhang
>
> Enable GPU for qcs615-ride platform and provide path for zap
> shader.
>
> Signed-off-by: Jie Zhang
> Signed-off-by: Akhil P Oommen
> ---
Reviewed-by: Konrad Dybcio
Konrad
On 12/13/2024 4:05 PM, Akhil P Oommen wrote:
> This series adds support for Adreno 612 to QCS615 chipset's devicetree.
> DRM driver's support was posted earlier and can be found here:
> https://patchwork.freedesktop.org/patch/626066/
>
> Patch#1 & #2 are for Rob Clark and the other 2 for Bjo
From: Lijuan Gao
Add a compatible for the Power Domain Controller on QCS615 platform.
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Lijuan Gao
---
Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git
a/Documentation/devicetr
This series adds support for Adreno 612 to QCS615 chipset's devicetree.
DRM driver's support was posted earlier and can be found here:
https://patchwork.freedesktop.org/patch/626066/
Patch#1 & #2 are for Rob Clark and the other 2 for Bjorn
Signed-off-by: Akhil P Oommen
---
Changes in v2:
RGMU a.k.a Reduced Graphics Management Unit is a small state machine
with the sole purpose of providing IFPC support. Compared to GMU, it
doesn't manage GPU clock, voltage scaling, bw voting or any other
functionalities. All it does is detect an idle GPU and toggle the
GDSC switch. So it doesn't re
A612 GPU requires an additional smmu_vote clock. Update the bindings to
reflect this.
Signed-off-by: Akhil P Oommen
---
.../devicetree/bindings/display/msm/gpu.yaml | 36 ++
1 file changed, 36 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/gpu
From: Jie Zhang
Add gpu and gmu nodes for qcs615 chipset.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
Reviewed-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/qcs615.dtsi | 88
1 file changed, 88 insertions(+)
diff --git a/arch/arm64/boot/dt
From: Jie Zhang
Enable GPU for qcs615-ride platform and provide path for zap
shader.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/qcs615-ride.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts
b/arch
This series adds support for Adreno 612 to QCS615 chipset's devicetree.
DRM driver's support was posted earlier and can be found here:
https://patchwork.freedesktop.org/patch/626066/
Patch#1 & #2 are for Rob Clark and the other 2 for Bjorn
Signed-off-by: Akhil P Oommen
---
Changes in v2:
On 12/13/2024 4:54 PM, Akhil P Oommen wrote:
> From: Lijuan Gao
>
> Add a compatible for the Power Domain Controller on QCS615 platform.
>
> Reviewed-by: Krzysztof Kozlowski
> Signed-off-by: Lijuan Gao
> ---
> Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml | 1 +
> 1 fil
On 12/13/2024 4:54 PM, Akhil P Oommen wrote:
> This series adds support for Adreno 612 to QCS615 chipset's devicetree.
> DRM driver's support was posted earlier and can be found here:
> https://patchwork.freedesktop.org/patch/626066/
>
> Patch#1 & #2 are for Rob Clark and the other 2 for Bjo
This series adds support for Adreno 612 to QCS615 chipset's devicetree.
DRM driver's support was posted earlier and can be found here:
https://patchwork.freedesktop.org/patch/626066/
Patch#1 & #2 are for Rob Clark and the other 2 for Bjorn
Signed-off-by: Akhil P Oommen
---
Changes in v2:
A612 GPU requires an additional smmu_vote clock. Update the bindings to
reflect this.
Signed-off-by: Akhil P Oommen
---
.../devicetree/bindings/display/msm/gpu.yaml | 36 ++
1 file changed, 36 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/gpu
RGMU a.k.a Reduced Graphics Management Unit is a small state machine
with the sole purpose of providing IFPC support. Compared to GMU, it
doesn't manage GPU clock, voltage scaling, bw voting or any other
functionalities. All it does is detect an idle GPU and toggle the
GDSC switch. So it doesn't re
From: Jie Zhang
Add gpu and gmu nodes for qcs615 chipset.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
Reviewed-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/qcs615.dtsi | 88
1 file changed, 88 insertions(+)
diff --git a/arch/arm64/boot/dt
From: Jie Zhang
Enable GPU for qcs615-ride platform and provide path for zap
shader.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/qcs615-ride.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts
b/arch
On 12.12.2024 10:36 PM, Neil Armstrong wrote:
> On 12/12/2024 21:32, Konrad Dybcio wrote:
>> On 11.12.2024 9:29 AM, Neil Armstrong wrote:
>>> Now all the DDR bandwidth voting via the GPU Management Unit (GMU)
>>> is in place, declare the Bus Control Modules (BCMs) and the
>>> corresponding paramete
Hi Vignesh
On 12/11/2024 9:10 PM, Vignesh Raman wrote:
Hi Abhinav / Helen,
On 12/12/24 01:48, Abhinav Kumar wrote:
Hi Helen / Vignesh
On 12/4/2024 12:33 PM, Helen Mae Koike Fornazier wrote:
On Wed, 04 Dec 2024 16:21:26 -0300 Abhinav Kumar wrote ---
> Hi Helen
>
> On 12/4/202
On Fri, Dec 13, 2024 at 8:47 AM Akhil P Oommen wrote:
>
> On 12/12/2024 10:42 PM, Rob Clark wrote:
> > On Thu, Dec 12, 2024 at 9:08 AM Rob Clark wrote:
> >>
> >> On Thu, Dec 12, 2024 at 7:59 AM Akhil P Oommen
> >> wrote:
> >>>
> >>> On 12/5/2024 10:24 PM, Rob Clark wrote:
> From: Rob Clark
On 12/12/2024 5:05 PM, Dmitry Baryshkov wrote:
On Thu, Dec 12, 2024 at 11:11:54AM -0800, Jessica Zhang wrote:
Filter out modes that have a clock rate greater than the max core clock
rate when adjusted for the perf clock factor
This is especially important for chipsets such as QCS615 that hav
On Fri, 13 Dec 2024 at 21:15, Abhinav Kumar wrote:
>
>
>
> On 12/12/2024 5:05 PM, Dmitry Baryshkov wrote:
> > On Thu, Dec 12, 2024 at 11:11:54AM -0800, Jessica Zhang wrote:
> >> Filter out modes that have a clock rate greater than the max core clock
> >> rate when adjusted for the perf clock facto
On Fri, 13 Dec 2024 at 13:32, Akhil P Oommen wrote:
>
> From: Jie Zhang
>
> Enable GPU for qcs615-ride platform and provide path for zap
> shader.
>
> Signed-off-by: Jie Zhang
> Signed-off-by: Akhil P Oommen
> ---
> arch/arm64/boot/dts/qcom/qcs615-ride.dts | 8
> 1 file changed, 8 ins
On 12/12/2024 10:42 PM, Rob Clark wrote:
> On Thu, Dec 12, 2024 at 9:08 AM Rob Clark wrote:
>>
>> On Thu, Dec 12, 2024 at 7:59 AM Akhil P Oommen
>> wrote:
>>>
>>> On 12/5/2024 10:24 PM, Rob Clark wrote:
From: Rob Clark
Performance counter usage falls into two categories:
>>>
On 12/12/2024 9:44 PM, Antonino Maniscalco wrote:
> On 12/12/24 4:58 PM, Akhil P Oommen wrote:
>> On 12/5/2024 10:24 PM, Rob Clark wrote:
>>> From: Rob Clark
>>>
>>> Performance counter usage falls into two categories:
>>>
>>> 1. Local usage, where the counter configuration, start, and end read
>>
On 12/13/2024 10:10 PM, neil.armstr...@linaro.org wrote:
> On 13/12/2024 17:31, Konrad Dybcio wrote:
>> On 13.12.2024 5:28 PM, neil.armstr...@linaro.org wrote:
>>> On 13/12/2024 16:37, Konrad Dybcio wrote:
On 13.12.2024 2:12 PM, Akhil P Oommen wrote:
> On 12/13/2024 3:07 AM, Neil Armstrong
On 13.12.2024 2:12 PM, Akhil P Oommen wrote:
> On 12/13/2024 3:07 AM, Neil Armstrong wrote:
>> On 12/12/2024 21:21, Konrad Dybcio wrote:
>>> On 11.12.2024 9:29 AM, Neil Armstrong wrote:
The Adreno GPU Management Unit (GMU) can also scale the DDR Bandwidth
along the Frequency and Power Dom
On 13.12.2024 12:31 PM, Akhil P Oommen wrote:
> From: Jie Zhang
>
> Add gpu and gmu nodes for qcs615 chipset.
>
> Signed-off-by: Jie Zhang
> Signed-off-by: Akhil P Oommen
> Reviewed-by: Dmitry Baryshkov
> ---
Reviewed-by: Konrad Dybcio
Konrad
On 13.12.2024 4:09 PM, Konrad Dybcio wrote:
> On 13.12.2024 12:31 PM, Akhil P Oommen wrote:
>> From: Jie Zhang
>>
>> Add gpu and gmu nodes for qcs615 chipset.
>>
>> Signed-off-by: Jie Zhang
>> Signed-off-by: Akhil P Oommen
>> Reviewed-by: Dmitry Baryshkov
>> ---
>
> Reviewed-by: Konrad Dybcio
On 13.12.2024 4:55 PM, Rob Clark wrote:
> On Fri, Dec 13, 2024 at 5:11 AM Konrad Dybcio
> wrote:
>>
>> On 23.11.2024 3:41 AM, Rob Clark wrote:
>>> On Fri, Nov 22, 2024 at 4:19 PM Konrad Dybcio
>>> wrote:
On 22.11.2024 4:51 PM, Rob Clark wrote:
> On Fri, Nov 22, 2024 at 4:21 AM Konra
On 13/12/2024 16:37, Konrad Dybcio wrote:
On 13.12.2024 2:12 PM, Akhil P Oommen wrote:
On 12/13/2024 3:07 AM, Neil Armstrong wrote:
On 12/12/2024 21:21, Konrad Dybcio wrote:
On 11.12.2024 9:29 AM, Neil Armstrong wrote:
The Adreno GPU Management Unit (GMU) can also scale the DDR Bandwidth
alon
On 12/13/2024 6:09 PM, Konrad Dybcio wrote:
> On 12.12.2024 10:36 PM, Neil Armstrong wrote:
>> On 12/12/2024 21:32, Konrad Dybcio wrote:
>>> On 11.12.2024 9:29 AM, Neil Armstrong wrote:
Now all the DDR bandwidth voting via the GPU Management Unit (GMU)
is in place, declare the Bus Control
On 12/13/2024 4:27 PM, Konrad Dybcio wrote:
> On 13.12.2024 11:35 AM, Akhil P Oommen wrote:
>> From: Jie Zhang
>>
>> Add gpu and gmu nodes for qcs615 chipset.
>>
>> Signed-off-by: Jie Zhang
>> Signed-off-by: Akhil P Oommen
>> Reviewed-by: Dmitry Baryshkov
>> ---
>> arch/arm64/boot/dts/qcom/qcs
On 12/13/2024 4:23 PM, Konrad Dybcio wrote:
> On 13.12.2024 11:35 AM, Akhil P Oommen wrote:
>> RGMU a.k.a Reduced Graphics Management Unit is a small state machine
>> with the sole purpose of providing IFPC support. Compared to GMU, it
>> doesn't manage GPU clock, voltage scaling, bw voting or any
On 13.12.2024 5:28 PM, neil.armstr...@linaro.org wrote:
> On 13/12/2024 16:37, Konrad Dybcio wrote:
>> On 13.12.2024 2:12 PM, Akhil P Oommen wrote:
>>> On 12/13/2024 3:07 AM, Neil Armstrong wrote:
On 12/12/2024 21:21, Konrad Dybcio wrote:
> On 11.12.2024 9:29 AM, Neil Armstrong wrote:
On 13/12/2024 17:31, Konrad Dybcio wrote:
On 13.12.2024 5:28 PM, neil.armstr...@linaro.org wrote:
On 13/12/2024 16:37, Konrad Dybcio wrote:
On 13.12.2024 2:12 PM, Akhil P Oommen wrote:
On 12/13/2024 3:07 AM, Neil Armstrong wrote:
On 12/12/2024 21:21, Konrad Dybcio wrote:
On 11.12.2024 9:29 A
On 12/13/2024 3:07 AM, Neil Armstrong wrote:
> On 12/12/2024 21:21, Konrad Dybcio wrote:
>> On 11.12.2024 9:29 AM, Neil Armstrong wrote:
>>> The Adreno GPU Management Unit (GMU) can also scale the DDR Bandwidth
>>> along the Frequency and Power Domain level, until now we left the OPP
>>> core scale
On Fri, Dec 13, 2024 at 5:11 AM Konrad Dybcio
wrote:
>
> On 23.11.2024 3:41 AM, Rob Clark wrote:
> > On Fri, Nov 22, 2024 at 4:19 PM Konrad Dybcio
> > wrote:
> >>
> >> On 22.11.2024 4:51 PM, Rob Clark wrote:
> >>> On Fri, Nov 22, 2024 at 4:21 AM Konrad Dybcio
> >>> wrote:
>
> On 21.11.
On 23.11.2024 3:41 AM, Rob Clark wrote:
> On Fri, Nov 22, 2024 at 4:19 PM Konrad Dybcio
> wrote:
>>
>> On 22.11.2024 4:51 PM, Rob Clark wrote:
>>> On Fri, Nov 22, 2024 at 4:21 AM Konrad Dybcio
>>> wrote:
On 21.11.2024 5:48 PM, Rob Clark wrote:
> From: Rob Clark
>
> Debuggin
On 12/13/24 5:50 PM, Akhil P Oommen wrote:
On 12/12/2024 9:44 PM, Antonino Maniscalco wrote:
On 12/12/24 4:58 PM, Akhil P Oommen wrote:
On 12/5/2024 10:24 PM, Rob Clark wrote:
From: Rob Clark
Performance counter usage falls into two categories:
1. Local usage, where the counter configuratio
On 13.12.2024 5:55 PM, Akhil P Oommen wrote:
> On 12/13/2024 10:10 PM, neil.armstr...@linaro.org wrote:
>> On 13/12/2024 17:31, Konrad Dybcio wrote:
>>> On 13.12.2024 5:28 PM, neil.armstr...@linaro.org wrote:
On 13/12/2024 16:37, Konrad Dybcio wrote:
> On 13.12.2024 2:12 PM, Akhil P Oommen
As a preparation to further MDSS-revision cleanups stop passing MDSS
revision to the setup_timing_gen() callback. Instead store a pointer to
it inside struct dpu_hw_intf and use it diretly. It's not that the MDSS
revision can chance between dpu_hw_intf_init() and
dpu_encoder_phys_vid_setup_timing_e
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