Continue migration to the MDSS-revision based checks and replace
DPU_DSC_OUTPUT_CTRL feature bit with the core_major_ver >= 5 check.

Signed-off-by: Dmitry Baryshkov <dmitry.barysh...@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h  | 4 ----
 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 6 ------
 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h  | 2 --
 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h  | 4 ----
 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h  | 1 -
 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h  | 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h          | 5 +----
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c              | 6 ++++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h              | 3 ++-
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c                  | 2 +-
 10 files changed, 8 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h 
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
index 
d5e608402082cfc3cde8d156acdc85ee366af685..6ce69b31bdbcadd4819cf198ec9e7fd7fec9d685
 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
@@ -260,19 +260,15 @@ static const struct dpu_dsc_cfg sm8150_dsc[] = {
        {
                .name = "dsc_0", .id = DSC_0,
                .base = 0x80000, .len = 0x140,
-               .features = BIT(DPU_DSC_OUTPUT_CTRL),
        }, {
                .name = "dsc_1", .id = DSC_1,
                .base = 0x80400, .len = 0x140,
-               .features = BIT(DPU_DSC_OUTPUT_CTRL),
        }, {
                .name = "dsc_2", .id = DSC_2,
                .base = 0x80800, .len = 0x140,
-               .features = BIT(DPU_DSC_OUTPUT_CTRL),
        }, {
                .name = "dsc_3", .id = DSC_3,
                .base = 0x80c00, .len = 0x140,
-               .features = BIT(DPU_DSC_OUTPUT_CTRL),
        },
 };
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h 
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
index 
e3ea28c653328cf926a18426d12f07821c413b30..96a943361fb12bc4cf6fda6fbb6bbb6a01fd97f5
 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
@@ -259,27 +259,21 @@ static const struct dpu_dsc_cfg sc8180x_dsc[] = {
        {
                .name = "dsc_0", .id = DSC_0,
                .base = 0x80000, .len = 0x140,
-               .features = BIT(DPU_DSC_OUTPUT_CTRL),
        }, {
                .name = "dsc_1", .id = DSC_1,
                .base = 0x80400, .len = 0x140,
-               .features = BIT(DPU_DSC_OUTPUT_CTRL),
        }, {
                .name = "dsc_2", .id = DSC_2,
                .base = 0x80800, .len = 0x140,
-               .features = BIT(DPU_DSC_OUTPUT_CTRL),
        }, {
                .name = "dsc_3", .id = DSC_3,
                .base = 0x80c00, .len = 0x140,
-               .features = BIT(DPU_DSC_OUTPUT_CTRL),
        }, {
                .name = "dsc_4", .id = DSC_4,
                .base = 0x81000, .len = 0x140,
-               .features = BIT(DPU_DSC_OUTPUT_CTRL),
        }, {
                .name = "dsc_5", .id = DSC_5,
                .base = 0x81400, .len = 0x140,
-               .features = BIT(DPU_DSC_OUTPUT_CTRL),
        },
 };
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h 
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
index 
a30b8906091d3ae72f2f9cdfc558942cab0a713f..533312fbd70c22314fbabba17116cbbeca8df515
 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
@@ -195,11 +195,9 @@ static const struct dpu_dsc_cfg sm7150_dsc[] = {
        {
                .name = "dsc_0", .id = DSC_0,
                .base = 0x80000, .len = 0x140,
-               .features = BIT(DPU_DSC_OUTPUT_CTRL),
        }, {
                .name = "dsc_1", .id = DSC_1,
                .base = 0x80400, .len = 0x140,
-               .features = BIT(DPU_DSC_OUTPUT_CTRL),
        },
 };
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h 
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
index 
1f542c3fba6a8c3ddb5eafa6536a9206cd5a61ce..68210af03c3d5248530884199f9dcda651584026
 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
@@ -259,19 +259,15 @@ static const struct dpu_dsc_cfg sm8250_dsc[] = {
        {
                .name = "dsc_0", .id = DSC_0,
                .base = 0x80000, .len = 0x140,
-               .features = BIT(DPU_DSC_OUTPUT_CTRL),
        }, {
                .name = "dsc_1", .id = DSC_1,
                .base = 0x80400, .len = 0x140,
-               .features = BIT(DPU_DSC_OUTPUT_CTRL),
        }, {
                .name = "dsc_2", .id = DSC_2,
                .base = 0x80800, .len = 0x140,
-               .features = BIT(DPU_DSC_OUTPUT_CTRL),
        }, {
                .name = "dsc_3", .id = DSC_3,
                .base = 0x80c00, .len = 0x140,
-               .features = BIT(DPU_DSC_OUTPUT_CTRL),
        },
 };
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h 
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
index 
0e4d78470d27f3c5aed8171278ffe5d9d4126174..98891b4b929fd11b92b846ea20467746fc43735e
 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
@@ -135,7 +135,6 @@ static const struct dpu_dsc_cfg sm6350_dsc[] = {
        {
                .name = "dsc_0", .id = DSC_0,
                .base = 0x80000, .len = 0x140,
-               .features = BIT(DPU_DSC_OUTPUT_CTRL),
        },
 };
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h 
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
index 
b5a3574e2ce43f7f5d47c42fe1bdd0f084396a9f..c08d8bae3293d00ef7ff28942699ae2a52e2cea9
 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
@@ -87,7 +87,6 @@ static const struct dpu_dsc_cfg sm6375_dsc[] = {
        {
                .name = "dsc_0", .id = DSC_0,
                .base = 0x80000, .len = 0x140,
-               .features = BIT(DPU_DSC_OUTPUT_CTRL),
        },
 };
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 
f794218f14a96eda34d786783fdbde98f9ad1237..d9b500c14594ed86a8ce33b3a9dddb9f7d69129d
 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -176,14 +176,11 @@ enum {
 
 /**
  * DSC sub-blocks/features
- * @DPU_DSC_OUTPUT_CTRL       Configure which PINGPONG block gets
- *                            the pixel output from this DSC.
  * @DPU_DSC_NATIVE_42x_EN     Supports NATIVE_422_EN and NATIVE_420_EN encoding
  * @DPU_DSC_MAX
  */
 enum {
-       DPU_DSC_OUTPUT_CTRL = 0x1,
-       DPU_DSC_NATIVE_42x_EN,
+       DPU_DSC_NATIVE_42x_EN = 0x1,
        DPU_DSC_MAX
 };
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
index 
0db375d2d779e075d20d08de059124bee81652ab..9fb70ff3aa2d047b7e17f6f063f8b32276267a26
 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
@@ -185,11 +185,13 @@ static void dpu_hw_dsc_bind_pingpong_blk(
  * @dev:  Corresponding device for devres management
  * @cfg:  DSC catalog entry for which driver object is required
  * @addr: Mapped register io address of MDP
+ * @mdss_ver: dpu core's major and minor versions
  * Return: Error code or allocated dpu_hw_dsc context
  */
 struct dpu_hw_dsc *dpu_hw_dsc_init(struct drm_device *dev,
                                   const struct dpu_dsc_cfg *cfg,
-                                  void __iomem *addr)
+                                  void __iomem *addr,
+                                  const struct dpu_mdss_version *mdss_ver)
 {
        struct dpu_hw_dsc *c;
 
@@ -206,7 +208,7 @@ struct dpu_hw_dsc *dpu_hw_dsc_init(struct drm_device *dev,
        c->ops.dsc_disable = dpu_hw_dsc_disable;
        c->ops.dsc_config = dpu_hw_dsc_config;
        c->ops.dsc_config_thresh = dpu_hw_dsc_config_thresh;
-       if (c->caps->features & BIT(DPU_DSC_OUTPUT_CTRL))
+       if (mdss_ver->core_major_ver >= 5)
                c->ops.dsc_bind_pingpong_blk = dpu_hw_dsc_bind_pingpong_blk;
 
        return c;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
index 
fc171bdeca488f6287cf2ba7362ed330ad55b28f..b7013c9822d23238eb5411a5e284bb072ecc3395
 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
@@ -64,7 +64,8 @@ struct dpu_hw_dsc {
 
 struct dpu_hw_dsc *dpu_hw_dsc_init(struct drm_device *dev,
                                   const struct dpu_dsc_cfg *cfg,
-                                  void __iomem *addr);
+                                  void __iomem *addr,
+                                  const struct dpu_mdss_version *mdss_ver);
 
 struct dpu_hw_dsc *dpu_hw_dsc_init_1_2(struct drm_device *dev,
                                       const struct dpu_dsc_cfg *cfg,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 
c0adda2b763648cef439c38980b9f393b59c0094..a7c5cea7489df353491a8885e32d2673133d41c3
 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -163,7 +163,7 @@ int dpu_rm_init(struct drm_device *dev,
                if (cat->mdss_ver->core_major_ver >= 7)
                        hw = dpu_hw_dsc_init_1_2(dev, dsc, mmio);
                else
-                       hw = dpu_hw_dsc_init(dev, dsc, mmio);
+                       hw = dpu_hw_dsc_init(dev, dsc, mmio, cat->mdss_ver);
 
                if (IS_ERR(hw)) {
                        rc = PTR_ERR(hw);

-- 
2.39.5

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