Add a helper to check whether a dp_panel is mst capable.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dp/dp_aux.h | 1 +
drivers/gpu/drm/msm/dp/dp_panel.c | 14 ++
drivers/gpu/drm/msm/dp/dp_panel.h | 1 +
3 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/msm
Move the link related operations to dp_display_unprepare() and keep
only stream related operations in dp_display_disable().
Make dp_display_unprepare() available to other clients such as DP MST.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dp/dp_display.c | 31 --
With MST, each DP controller can handle multiple streams.
There shall be one dp_panel for each stream but the dp_display
object shall be shared among them. To represent this abstraction,
create a stream_id for each DP panel which shall be set by the
MST stream. For SST, default this to stream 0.
U
dp_display_disable() handles special case of when monitor is
disconnected from the dongle while the dongle stays connected
thereby needing a separate function dp_ctrl_off_link_stream()
for this. However with a slight rework this can still be handled
by keeping common paths same for regular and spec
Populate the max_streams for DP controllers to indicate MST support.
If the pixel clock handle for the second stream fails, treat it as
SST case rather than a complete failure.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dp/dp_ctrl.c| 9 +
drivers/gpu/drm/msm/dp/dp_ctrl.h
Currently the dp_display bridge helpers, in particular the
dp_display_enable()/dp_display_disable() use the cached panel.
To be able to re-use these helpers for MST use-case abstract the
helpers to use the panel which is passed in to them.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dp/
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dp/dp_drm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_drm.c
index
920392b3c688821bccdc66d50fb7052ac3a9a85a..225858c6240512cf2c5ca3b5eb52cf9b7f4db3e3
100644
dp_display caches the current display mode and then passes it onto
the panel to be used for programming the panel params. Remove this
two level passing and directly populated the panel's dp_display_mode
instead.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dp/dp_display.c | 46 ++
HPD state machine assumes only one active stream. Fix it to account
for both while marking the state of the hpd as disconnected.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dp/dp_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_disp
Add connector abstraction for the DP MST. Each MST encoder
is connected through a DRM bridge to a MST connector and each
MST connector has a DP panel abstraction attached to it.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dp/dp_mst_drm.c | 517
drive
As required by the hardware programming guide, always program
the MST_FIFO_CONSTANT_FILL for MST use-cases.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dp/dp_catalog.c | 24
drivers/gpu/drm/msm/dp/dp_catalog.h | 1 +
drivers/gpu/drm/msm/dp/dp_ctrl.c| 3 +++
Each DP controller capable of MST can support multiple streams
and each of the streams maps to an interface block ID which can
vary based on chipset. Add a stream to interface map for MST capable
DP controllers.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dp/dp_display.c | 46 ++
Add irq hpd callback for the dp mst module which shall be
invoked from the dp_display's irq hpd handler to perform
mst specific operations in case of irq hpd. In MST case, route
the IRQ HPD messages to MST module.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dp/dp_display.c | 17
dp_bridge helpers take drm_bridge as an input and extract the
dp_display object to be used in the dp_display module. Rather than
doing it in a roundabout way, directly pass the dp_display object
to these helpers so that the MST bridge can also re-use the same
helpers.
Signed-off-by: Abhinav Kumar
During certain cases, the dp mst connector's panel edid can be
re-used such as getting multiple get_modes() without irq_hpd and
should be cleared in cases when the connector is destroyed or when
irq hpd is received. Add support to handle these cases for the
mst_connector's panel edid.
Signed-off-b
For each MST capable DP controller, initialize a dp_mst module to
manage its DP MST operations. The DP MST module for each controller
is the central entity to manage its topology related operations as
well as interfacing with the rest of the DP driver.
Signed-off-by: Abhinav Kumar
---
drivers/gp
Populate the pixel clock for stream 1 for DP1 for sa8775p DP controller.
Signed-off-by: Abhinav Kumar
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
b/arch/arm64/boot/dts/qcom/sa8775
Use the dp_panel's stream_id to adjust the offsets for stream 1
which will be used for MST in the dp_catalog. Also add additional
register defines for stream 1.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dp/dp_catalog.c | 99 -
drivers/gpu/drm/msm/dp
For DP MST, the link clock and power domain resources stay on until
both streams have been disabled OR we receive hotplug. Introduce an
active_stream_cnt to track the number of active streams and necessary
state handling. Replace the power_on variable with active_stream_cnt
as power_on boolean work
Use msm_dp_get_mst_intf_id() to get the intf id for the DP MST
controller as the intf_id is unique for each MST stream of each
DP controller.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 25 -
1 file changed, 20 insertions(+), 5 deletions
Add a new file dp_mst_drm to manage the DP MST bridge operations
similar to the dp_drm file which manages the SST bridge operations.
Each MST encoder creates one bridge and each bridge is bound to its
own dp_panel abstraction to manage the operations of its pipeline.
Signed-off-by: Abhinav Kumar
From: Yongxing Mou
Populate the pixel clock for stream 1 for DP0 for sa8775p DP controller.
Signed-off-by: Yongxing Mou
Signed-off-by: Abhinav Kumar
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/q
Hook up the mst framework APIs with atomic_commit_setup() and
atomic_commit_tail() APIs to handle non-blocking commits.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/msm_atomic.c | 2 ++
drivers/gpu/drm/msm/msm_drv.h| 1 +
drivers/gpu/drm/msm/msm_kms.c| 1 +
3 files changed, 4 ins
If the DP controller is capable of supporting multiple streams
then initialize the DP sink in MST mode by programming the DP_MSTM_CTRL
DPCD register to enable MST mode.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dp/dp_display.c | 32
1 file changed, 32
Initiliaze a DPMST encoder for each MST capable DP controller
and the number of encoders it supports depends on the number
of streams it supports. Replace the opencoded instances of max_stream
with the newly introduced API to centralize the usage.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/dr
Enable/Disable of DP pixel clock happens in multiple code paths
leading to code duplication. Move it into individual helpers so that
the helpers can be called wherever necessary.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dp/dp_ctrl.c | 76 ++--
1 fi
To protect against concurrent access of the dp mst bridges
introduce a session mutex.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dp/dp_mst_drm.c | 20
drivers/gpu/drm/msm/dp/dp_mst_drm.h | 1 +
2 files changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/msm/dp
From: Yongxing Mou
Propagate the hpd state changes to dp mst module so that it
can be synchronized with the cable connect/disconnect.
Signed-off-by: Yongxing Mou
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dp/dp_display.c | 20
drivers/gpu/drm/msm/dp/dp_mst_drm.c
Add an API dp_display_get_panel() to initialize and return a DP
panel to be used by DP MST module. Since some of the fields of
DP panel are private, dp_display module needs to initialize these
parts and return the panel back.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dp/dp_display.c |
Whenever virtual channel slot allocation changes, the DP
source must send the action control trigger sequence to notify
the sink about the same. This would be applicable during the
start and stop of the pixel stream. Add the infrastructure
to be able to send ACT packets for the DP controller when
o
Currently, the dp_ctrl stream APIs operate on their own dp_panel
which is cached inside the dp_ctrl's private struct. However with MST,
the cached panel represents the fixed link and not the sinks which
are hotplugged. Allow the stream related APIs to work on the panel
which is passed to them rathe
DP stream is transmitted in transfer units only for SST
case there is no need to calculate and program TU parameters
for MST case. Skip the TU programming for MST cases.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dp/dp_ctrl.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
dif
dp_display_enable() currently re-trains the link if needed
and then enables the pixel clock, programs the controller to
start sending the pixel stream. Break up these two parts into
separate APIs to distinguish these two parts better.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dp/dp_ct
Interface type of MST interfaces is currently INTF_NONE.
Fix this to INTF_DP.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p
For DP MST streams, the 64 MTP slots are time-shared between
the streams. Add the support to calculate the rate governor,
slots and reservation of the slots to the DP controller. Each
DP MST stream shall reserve its streams by calling the
dp_display_set_stream_info() from its bridge calls.
Signed-
Add support to program the MST enabled bit in the mainlink
control when a mst session is active and disabled.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dp/dp_catalog.c | 17 +
drivers/gpu/drm/msm/dp/dp_catalog.h | 1 +
drivers/gpu/drm/msm/dp/dp_ctrl.c| 4
3
For MST cases, EDID is handled through AUX sideband messaging.
Skip the EDID read during hotplug handle for MST cases.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dp/dp_display.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_displa
dp_ctrl_off_link() was created to handle a case where we received
a cable connect and then get a cable disconnect without the corresponding
dp_display_enable(). For such cases the pixel clock will be off but the
link clock will still be on. dp_ctrl_off_link() handles this case by
turning off the li
Convert dp_display_set_mode() to use the dp_panel passed to it
as an argument rather than the cached one in dp_display_private.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dp/dp_display.c | 60 ++---
1 file changed, 30 insertions(+), 30 deletions(-)
diff
p1 register block is needed for the second mst stream.
Add support in the catalog to be able to program this block.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dp/dp_catalog.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/msm/dp/dp_ca
VC payload fill sequence is inserted by the DP controller in the
absence of stream symbols that is before stream is disabled. Add
support to send the VCPF sequence for msm dp controller.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dp/dp_catalog.c | 25 +++
drivers/gp
dp_display_prepare() only prepares the link in case its not
already ready before dp_display_enable(). Hence separate it into
its own API.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dp/dp_display.c | 24 +---
drivers/gpu/drm/msm/dp/dp_display.h | 1 +
drivers/gpu/dr
Split dp_ctrl_off() into stream and link parts so that for MST
cases we can control the link and pixel parts separately.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dp/dp_ctrl.c| 29 +++--
drivers/gpu/drm/msm/dp/dp_ctrl.h| 2 +-
drivers/gpu/drm/msm/dp/dp
In preparation of DP MST where link caps are read for the
immediate downstream device and the edid is read through
sideband messaging, split the msm_dp_panel_read_sink_caps() into
two parts which read the link parameters and the edid parts
respectively.
Signed-off-by: Abhinav Kumar
---
drivers/g
rs/gpu/drm/msm/msm_atomic.c |2 +
drivers/gpu/drm/msm/msm_drv.h | 29 +
drivers/gpu/drm/msm/msm_kms.c |1 +
24 files changed, 2589 insertions(+), 296 deletions(-)
---
base-commit: b166256c1e6ce356fa1404d4c8531830e6f100a8
change-id
Once the link has already been setup there is no need to call
dp_catalog_ctrl_mainlink_ctrl() as this does a reset on the mainlink
thereby tearing down the link briefly.
Fixes: c943b4948b58 ("drm/msm/dp: add displayPort driver support")
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dp/dp_
On 26.11.2024 3:06 PM, Akhil P Oommen wrote:
> From: Jie Zhang
>
> Add gpu and gmu nodes for qcs615 chipset.
>
> Signed-off-by: Jie Zhang
> Signed-off-by: Akhil P Oommen
> ---
> arch/arm64/boot/dts/qcom/qcs615.dtsi | 86
>
> 1 file changed, 86 insertions(
On Thu, Dec 05, 2024 at 09:26:47PM +0800, Xiangxu Yin wrote:
>
>
> On 11/29/2024 10:33 PM, Dmitry Baryshkov wrote:
> > On Fri, 29 Nov 2024 at 09:59, Xiangxu Yin wrote:
> >>
> >> Extended DP support for QCS615 USB or DP phy. Differentiated between
> >> USBC and DP PHY using the match table’s type
From: Rob Clark
Performance counter usage falls into two categories:
1. Local usage, where the counter configuration, start, and end read
happen within (locally to) a single SUBMIT. In this case, there is
no dependency on counter configuration or values between submits, and
in fact cou
On 12/5/2024 3:20 AM, Rob Clark wrote:
> On Wed, Dec 4, 2024 at 1:47 PM Rob Clark wrote:
>>
>> On Wed, Dec 4, 2024 at 11:04 AM Akhil P Oommen
>> wrote:
>>>
>>> On 12/1/2024 10:06 PM, Rob Clark wrote:
On Sat, Nov 30, 2024 at 12:30 PM Akhil P Oommen
wrote:
>
> On 11/30/2024 7:01
Each GPU OPP requires a specific peak DDR bandwidth, let's add
those to each OPP and also the related interconnect path.
Signed-off-by: Neil Armstrong
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi
Each GPU OPP requires a specific peak DDR bandwidth, let's add
those to each OPP and also the related interconnect path.
Signed-off-by: Neil Armstrong
---
arch/arm64/boot/dts/qcom/sm8650.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8650.dts
The Adreno GPU Management Unit (GMU) can also vote for DDR Bandwidth
along the Frequency and Power Domain level, but by default we leave the
OPP core scale the interconnect ddr path.
While scaling the interconnect path was sufficient, newer GPUs
like the A750 requires specific vote parameters and
Even if the code uses ARRAY_SIZE() to fill those tables,
it's still a best practice to not use magic values for
tables in structs.
Suggested-by: Dmitry Baryshkov
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Akhil P Oommen
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.h |
Now all the DDR bandwidth voting via the GPU Management Unit (GMU)
is in place, declare the Bus Control Modules (BCMs) and the
corresponding parameters in the GPU info struct.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 22
The Adreno GPU Management Unit (GMU) can also scale the ddr
bandwidth along the frequency and power domain level, but for
now we statically fill the bw_table with values from the
downstream driver.
Only the first entry is used, which is a disable vote, so we
currently rely on scaling via the linux
The Adreno GPU Management Unit (GMU) can also scale the DDR Bandwidth
along the Frequency and Power Domain level, until now we left the OPP
core scale the OPP bandwidth via the interconnect path.
In order to enable bandwidth voting via the GPU Management
Unit (GMU), when an opp is set by devfreq w
The Adreno GPU Management Unit (GMU) can also scale DDR Bandwidth along
the Frequency and Power Domain level, but by default we leave the
OPP core scale the interconnect ddr path.
While scaling via the interconnect path was sufficient, newer GPUs
like the A750 requires specific vote paremeters and
On 11/29/2024 10:33 PM, Dmitry Baryshkov wrote:
> On Fri, 29 Nov 2024 at 09:59, Xiangxu Yin wrote:
>>
>> Extended DP support for QCS615 USB or DP phy. Differentiated between
>> USBC and DP PHY using the match table’s type, dynamically generating
>> different types of cfg and layout attributes d
sry，Please ignore this email forwarding， thks.
Dmitry Baryshkov 于2024年12月4日周三 16:28写道：
>
> On Wed, Nov 20, 2024 at 01:37:48PM +0100, Neil Armstrong wrote:
> > On 20/11/2024 12:19, Dmitry Baryshkov wrote:
> > > On Tue, Nov 19, 2024 at 06:56:39PM +0100, Neil Armstrong wrote:
> > > > The Adreno GMU
On Wed, Nov 20, 2024 at 01:37:48PM +0100, Neil Armstrong wrote:
> On 20/11/2024 12:19, Dmitry Baryshkov wrote:
> > On Tue, Nov 19, 2024 at 06:56:39PM +0100, Neil Armstrong wrote:
> > > The Adreno GMU Management Unit (GNU) can also scale the DDR Bandwidth
> > > along the Frequency and Power Domain l
On Thu, 5 Dec 2024 at 13:28, Xiangxu Yin wrote:
>
>
>
> On 12/2/2024 6:46 PM, Dmitry Baryshkov wrote:
> > On Mon, Dec 02, 2024 at 04:40:05PM +0800, Xiangxu Yin wrote:
> >>
> >>
> >> On 11/29/2024 9:50 PM, Dmitry Baryshkov wrote:
> >>> On Fri, 29 Nov 2024 at 09:59, Xiangxu Yin
> >>> wrote:
>
On 12/2/2024 6:46 PM, Dmitry Baryshkov wrote:
> On Mon, Dec 02, 2024 at 04:40:05PM +0800, Xiangxu Yin wrote:
>>
>>
>> On 11/29/2024 9:50 PM, Dmitry Baryshkov wrote:
>>> On Fri, 29 Nov 2024 at 09:59, Xiangxu Yin wrote:
Add the ability to configure lane mapping for the DP controller. Th
On Thu, 5 Dec 2024 at 09:33, Krzysztof Kozlowski wrote:
>
> On 04/12/2024 11:09, Dmitry Baryshkov wrote:
> > On Wed, Dec 04, 2024 at 09:02:18AM +0100, Krzysztof Kozlowski wrote:
> >> On Tue, Dec 03, 2024 at 03:41:48PM +0200, Dmitry Baryshkov wrote:
> >>> On Tue, Dec 03, 2024 at 09:01:31AM +0100, K
On 2024/11/29 21:37, Dmitry Baryshkov wrote:
On Fri, 29 Nov 2024 at 11:56, Yongxing Mou wrote:
On 2024/11/27 21:46, Dmitry Baryshkov wrote:
On Wed, Nov 27, 2024 at 03:05:03PM +0800, Yongxing Mou wrote:
Add Mobile Display Subsystem (MDSS) support for the QCS8300 platform.
Please mentio
On 2024/11/29 21:32, Dmitry Baryshkov wrote:
On Fri, 29 Nov 2024 at 12:01, Yongxing Mou wrote:
On 2024/11/27 21:49, Dmitry Baryshkov wrote:
On Wed, Nov 27, 2024 at 03:05:04PM +0800, Yongxing Mou wrote:
Add definitions for the display hardware used on the
Qualcomm QCS8300 platform.
Sign
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