[PATCH 44/45] arm64: dts: qcom: add mst support for pixel stream clk for DP0

[Abhinav Kumar]

From: Yongxing Mou <quic_yong...@quicinc.com>

Populate the pixel clock for stream 1 for DP0 for sa8775p DP controller.

Signed-off-by: Yongxing Mou <quic_yong...@quicinc.com>
Signed-off-by: Abhinav Kumar <quic_abhin...@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sa8775p.dtsi | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi 
b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 
0dbaa17e5e3f06c61b2aa777e45b73a48e50e66b..0150ce27b98e9894fa9ee6cccd020528d716f543
 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -3944,16 +3944,20 @@ mdss0_dp0: displayport-controller@af54000 {
                                         <&dispcc0 
MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
                                         <&dispcc0 
MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>,
                                         <&dispcc0 
MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
-                                        <&dispcc0 
MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+                                        <&dispcc0 
MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
+                                        <&dispcc0 
MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
                                clock-names = "core_iface",
                                              "core_aux",
                                              "ctrl_link",
                                              "ctrl_link_iface",
-                                             "stream_pixel";
+                                             "stream_pixel",
+                                             "stream_1_pixel";
                                assigned-clocks = <&dispcc0 
MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
-                                                 <&dispcc0 
MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
-                               assigned-clock-parents = <&mdss0_dp0_phy 0>, 
<&mdss0_dp0_phy 1>;
+                                                 <&dispcc0 
MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
+                                                 <&dispcc0 
MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
+                               assigned-clock-parents = <&mdss0_dp0_phy 0>, 
<&mdss0_dp0_phy 1>, <&mdss0_dp0_phy 1>;
                                phys = <&mdss0_dp0_phy>;
+
                                phy-names = "dp";
 
                                operating-points-v2 = <&dp_opp_table>;

-- 
2.34.1