[PATCH 45/45] arm64: dts: qcom: add mst support for pixel 1 stream clk for DP1

[Abhinav Kumar]

Populate the pixel clock for stream 1 for DP1 for sa8775p DP controller.

Signed-off-by: Abhinav Kumar <quic_abhin...@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sa8775p.dtsi | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi 
b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 
0150ce27b98e9894fa9ee6cccd020528d716f543..91149f8b3adb93ece159f30bfea39f9725b6c9e8
 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -4027,15 +4027,18 @@ mdss0_dp1: displayport-controller@af5c000 {
                                         <&dispcc0 
MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
                                         <&dispcc0 
MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>,
                                         <&dispcc0 
MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
-                                        <&dispcc0 
MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
+                                        <&dispcc0 
MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>,
+                                        <&dispcc0 
MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK>;
                                clock-names = "core_iface",
                                              "core_aux",
                                              "ctrl_link",
                                              "ctrl_link_iface",
-                                             "stream_pixel";
+                                             "stream_pixel",
+                                             "stream_1_pixel";
                                assigned-clocks = <&dispcc0 
MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
-                                                 <&dispcc0 
MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
-                               assigned-clock-parents = <&mdss0_dp1_phy 0>, 
<&mdss0_dp1_phy 1>;
+                                                 <&dispcc0 
MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>,
+                                                 <&dispcc0 
MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>;
+                               assigned-clock-parents = <&mdss0_dp1_phy 0>, 
<&mdss0_dp1_phy 1>, <&mdss0_dp1_phy 1>;
                                phys = <&mdss0_dp1_phy>;
                                phy-names = "dp";
 

-- 
2.34.1