On 27/11/2024 17:00, Akhil P Oommen wrote:
On 11/25/2024 1:46 PM, Neil Armstrong wrote:
On 23/11/2024 20:43, Akhil P Oommen wrote:
On Tue, Nov 19, 2024 at 06:56:39PM +0100, Neil Armstrong wrote:
The Adreno GMU Management Unit (GNU) can also scale the DDR Bandwidth
along the Frequency and Power
On 27/11/2024 09:15, Yongxing Mou wrote:
> Add compatible string for the supported eDP PHY on qcs8300 platform.
What is supported eDP PHY? Can it be unsupported? Anyway, this repeats
the diff. Say something useful instead, like why this is not compatible
with sa8775p.
Best regards,
Krzysztof
On 11/27/2024 6:04 AM, Dmitry Baryshkov wrote:
Follow other msm_mdss_setup_ubwc_dec_nn functions and use individual
bits instead of just specifying the value to be programmed to the
UBWC_STATIC register.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_mdss.c | 17 +-
On 11/27/2024 6:04 AM, Dmitry Baryshkov wrote:
Rather than hand-coding UBWC_STATIC value calculation, define
corresponding bitfields and use them to setup the register value.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_mdss.c | 38 +++---
On 11/25/2024 1:46 PM, Neil Armstrong wrote:
> On 23/11/2024 20:43, Akhil P Oommen wrote:
>> On Tue, Nov 19, 2024 at 06:56:39PM +0100, Neil Armstrong wrote:
>>> The Adreno GMU Management Unit (GNU) can also scale the DDR Bandwidth
>>> along the Frequency and Power Domain level, but by default we le
On 27/11/2024 16:46, Akhil P Oommen wrote:
On 11/25/2024 1:44 PM, Neil Armstrong wrote:
On 23/11/2024 23:59, Akhil P Oommen wrote:
On Tue, Nov 19, 2024 at 06:56:43PM +0100, Neil Armstrong wrote:
When requesting a DDR bandwidth level along a GPU frequency
level via the GMU, we can also specify
On 27/11/2024 16:29, Akhil P Oommen wrote:
On 11/25/2024 1:42 PM, Neil Armstrong wrote:
On 23/11/2024 23:46, Akhil P Oommen wrote:
On Sun, Nov 24, 2024 at 02:52:46AM +0530, Akhil P Oommen wrote:
On Tue, Nov 19, 2024 at 06:56:40PM +0100, Neil Armstrong wrote:
The Adreno GMU Management Unit (GM
On 11/25/2024 1:44 PM, Neil Armstrong wrote:
> On 23/11/2024 23:59, Akhil P Oommen wrote:
>> On Tue, Nov 19, 2024 at 06:56:43PM +0100, Neil Armstrong wrote:
>>> When requesting a DDR bandwidth level along a GPU frequency
>>> level via the GMU, we can also specify the bus bandwidth usage in a
>>> 16
On 11/25/2024 1:42 PM, Neil Armstrong wrote:
> On 23/11/2024 23:46, Akhil P Oommen wrote:
>> On Sun, Nov 24, 2024 at 02:52:46AM +0530, Akhil P Oommen wrote:
>>> On Tue, Nov 19, 2024 at 06:56:40PM +0100, Neil Armstrong wrote:
The Adreno GMU Management Unit (GMU) can also scale DDR Bandwidth alo
Follow other msm_mdss_setup_ubwc_dec_nn functions and use individual
bits instead of just specifying the value to be programmed to the
UBWC_STATIC register.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_mdss.c | 17 +
drivers/gpu/drm/msm/msm_mdss.h | 1 -
2 files c
The macrotile_mode is a flag, not a bit value. Use true/false values to
set it rather than 1/0.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_mdss.c | 16
drivers/gpu/drm/msm/msm_mdss.h | 2 +-
2 files changed, 9 insertions(+), 9 deleti
Rather than hand-coding UBWC_STATIC value calculation, define
corresponding bitfields and use them to setup the register value.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_mdss.c | 38 +++---
drivers/gpu/drm/msm/msm_mdss.h | 1
Current way of programming of the UBWC-related registers has been
inherited from vendor's drivers. The ubwc_static was supposed to contain
raw data to be programmed to the hardware, but was later repurposed to
define of the bits. As it can be seen by the commit 3e30296b374a
("drm/msm: fix the highe
On Wed, Nov 27, 2024 at 06:54:10PM +0800, Yongxing Mou wrote:
>
>
> On 2024/11/27 15:13, Krzysztof Kozlowski wrote:
> > On 27/11/2024 08:05, Yongxing Mou wrote:
> > > This series introduces support to enable the Mobile Display Subsystem
> > > (MDSS)
> > > and Display Processing Unit (DPU) for th
On Wed, Nov 27, 2024 at 03:05:02PM +0800, Yongxing Mou wrote:
> Document the DPU for Qualcomm QCS8300 platform.
>
> Signed-off-by: Yongxing Mou
> ---
> Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git
> a/Documentation/de
On Wed, Nov 27, 2024 at 03:05:04PM +0800, Yongxing Mou wrote:
> Add definitions for the display hardware used on the
> Qualcomm QCS8300 platform.
>
> Signed-off-by: Yongxing Mou
> ---
> .../drm/msm/disp/dpu1/catalog/dpu_8_4_qcs8300.h| 485
> +
> drivers/gpu/drm/msm/disp/
On Wed, Nov 27, 2024 at 03:05:03PM +0800, Yongxing Mou wrote:
> Add Mobile Display Subsystem (MDSS) support for the QCS8300 platform.
Please mention, why do you need it at all. I see that the UBWC swizzle
and HBB settings are different. Is this really the case? Is it because
of the different memor
On Wed, Nov 27, 2024 at 04:15:51PM +0800, Yongxing Mou wrote:
> The Qualcomm QCS8300 platform comes with a DisplayPort controller
> with same base offset with SA8775P, add support for this in the
> DisplayPort driver.
Can we reuse SA8775P config then? And SA8775p compatible as a fallback,
not requ
On Wed, Nov 27, 2024 at 04:15:49PM +0800, Yongxing Mou wrote:
> Add support for eDP PHY v5 found on the Qualcomm QCS8300 platform.
>
> Signed-off-by: Yongxing Mou
> ---
> drivers/phy/qualcomm/phy-qcom-edp.c | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/phy/qualcomm/ph
On 27/11/2024 11:54, Yongxing Mou wrote:
>
>
> On 2024/11/27 15:13, Krzysztof Kozlowski wrote:
>> On 27/11/2024 08:05, Yongxing Mou wrote:
>>> This series introduces support to enable the Mobile Display Subsystem (MDSS)
>>> and Display Processing Unit (DPU) for the Qualcomm QCS8300 target. It
>>>
On 27/11/2024 12:02, Yongxing Mou wrote:
>>
>> doc reference errors (make refcheckdocs):
>>
>> See
>> https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20241127-mdss_qcs8300-v1-1-29b2c3ee9...@quicinc.com
>>
>> The base for the serie
On 2024/11/27 19:06, Tingwei Zhang wrote:
On 11/27/2024 6:54 PM, Yongxing Mou wrote:
On 2024/11/27 15:13, Krzysztof Kozlowski wrote:
On 27/11/2024 08:05, Yongxing Mou wrote:
This series introduces support to enable the Mobile Display
Subsystem (MDSS)
and Display Processing Unit (DPU) for
On 11/27/2024 6:54 PM, Yongxing Mou wrote:
On 2024/11/27 15:13, Krzysztof Kozlowski wrote:
On 27/11/2024 08:05, Yongxing Mou wrote:
This series introduces support to enable the Mobile Display Subsystem
(MDSS)
and Display Processing Unit (DPU) for the Qualcomm QCS8300 target. It
includes the
unfinished jobs
make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1442:
dt_binding_check] Error 2
make: *** [Makefile:224: __sub-make] Error 2
doc reference errors (make refcheckdocs):
See
https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20241127-mdss_qcs8300-v1-1
On 2024/11/27 15:13, Krzysztof Kozlowski wrote:
On 27/11/2024 08:05, Yongxing Mou wrote:
This series introduces support to enable the Mobile Display Subsystem (MDSS)
and Display Processing Unit (DPU) for the Qualcomm QCS8300 target. It
includes the addition of the hardware catalog, compatible
.
make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1442:
dt_binding_check] Error 2
make: *** [Makefile:224: __sub-make] Error 2
doc reference errors (make refcheckdocs):
See
https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20241127-mdss_qcs8300-v1-1-29b2c3ee9...@quici
The Qualcomm QCS8300 platform comes with a DisplayPort controller
with same base offset with SA8775P, add support for this in the
DisplayPort driver.
Signed-off-by: Yongxing Mou
---
drivers/gpu/drm/msm/dp/dp_display.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/msm/
Add compatible string for the DisplayPort controller found on the
Qualcomm QCS8300 platform.
Signed-off-by: Yongxing Mou
---
Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/msm/dp-contr
| 6 ++
drivers/phy/qualcomm/phy-qcom-edp.c | 8
4 files changed, 16 insertions(+)
---
base-commit: 414c97c966b69e4a6ea7b32970fa166b2f9b9ef0
change-id: 20241127-qcs8300_dp-272c591c3aea
Best regards,
--
Yongxing Mou
Add support for eDP PHY v5 found on the Qualcomm QCS8300 platform.
Signed-off-by: Yongxing Mou
---
drivers/phy/qualcomm/phy-qcom-edp.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c
b/drivers/phy/qualcomm/phy-qcom-edp.c
index
f1b51018683d51df064
Add compatible string for the supported eDP PHY on qcs8300 platform.
Signed-off-by: Yongxing Mou
---
Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
b/Documentation/devicetree/bin
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