On 21.07.2021 18:11, Vinay Belgaumkar wrote:
> Add macros to check for SLPC support. This feature is currently supported
> for Gen12+ and enabled whenever GuC submission is enabled/selected.
>
> Include templates for SLPC init/fini and enable.
>
> v2: Move SLPC helper functions to intel_guc_sl
On 21.07.2021 18:11, Vinay Belgaumkar wrote:
> Add constants and params that are needed to configure SLPC.
>
> v2: Add a new abi header for SLPC. Replace bitfields with
> genmasks. Address other comments from Michal W.
>
> Signed-off-by: Vinay Belgaumkar
> Signed-off-by: Sundaresan Sujaritha
On 21.07.2021 18:11, Vinay Belgaumkar wrote:
> Allocate data structures for SLPC and functions for
> initializing on host side.
>
> v2: Address review comments (Michal W)
>
> Signed-off-by: Vinay Belgaumkar
> Signed-off-by: Sundaresan Sujaritha
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc.c
On 15.07.2021 03:58, Belgaumkar, Vinay wrote:
>
>
> On 7/10/2021 10:37 AM, Michal Wajdeczko wrote:
>>
>>
>> On 10.07.2021 03:20, Vinay Belgaumkar wrote:
...
>>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>>> b/drivers/gpu/dr
On 21.07.2021 18:11, Vinay Belgaumkar wrote:
> Add methods for interacting with GuC for enabling SLPC. Enable
> SLPC after GuC submission has been established. GuC load will
> fail if SLPC cannot be successfully initialized. Add various
> helper methods to set/unset the parameters for SLPC. They
On 21.07.2021 18:11, Vinay Belgaumkar wrote:
> Add param set h2g helpers to set the min and max frequencies
> for use by SLPC.
>
> v2: Address review comments (Michal W)
>
> Signed-off-by: Sundaresan Sujaritha
> Signed-off-by: Vinay Belgaumkar
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_sl
On 21.07.2021 18:11, Vinay Belgaumkar wrote:
> Add helpers to read the min/max frequency being used
> by SLPC. This is done by send a H2G command which forces
> SLPC to update the shared data struct which can then be
> read.
add note that functions will be used later
>
> v2: Address review co
On 21.07.2021 18:11, Vinay Belgaumkar wrote:
> This prints out relevant SLPC info from the SLPC shared structure.
>
> We will send a h2g message which forces SLPC to update the
> shared data structure with latest information before reading it.
>
> v2: Address review comments (Michal W)
>
> Si
On 21.07.2021 18:11, Vinay Belgaumkar wrote:
> Cache rp0, rp1 and rpn platform limits into SLPC structure
> for range checking while setting min/max frequencies.
>
> Also add "soft" limits which keep track of frequency changes
> made from userland. These are initially set to platform min
> and
tlimit));
> + return sysfs_emit(buf, "%d\n", intel_rps_get_min_frequency(rps));
> }
>
> static ssize_t gt_min_freq_mhz_store(struct device *kdev,
> @@ -398,31 +373,7 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
> if (ret)
> return ret;
>
> - mutex_lock(&rps->lock);
> -
> - val = intel_freq_opcode(rps, val);
> - if (val < rps->min_freq ||
> - val > rps->max_freq ||
> - val > rps->max_freq_softlimit) {
> - ret = -EINVAL;
> - goto unlock;
> - }
> -
> - rps->min_freq_softlimit = val;
> -
> - val = clamp_t(int, rps->cur_freq,
> - rps->min_freq_softlimit,
> - rps->max_freq_softlimit);
> -
> - /*
> - * We still need *_set_rps to process the new min_delay and
> - * update the interrupt limits and PMINTRMSK even though
> - * frequency request may be unchanged.
> - */
> - intel_rps_set(rps, val);
> -
> -unlock:
> - mutex_unlock(&rps->lock);
> + ret = intel_rps_set_min_frequency(rps, val);
>
> return ret ?: count;
> }
> @@ -448,11 +399,11 @@ static ssize_t gt_rp_mhz_show(struct device *kdev,
> struct device_attribute *attr
> u32 val;
>
> if (attr == &dev_attr_gt_RP0_freq_mhz)
> - val = intel_gpu_freq(rps, rps->rp0_freq);
> + val = intel_rps_get_rp0_frequency(rps);
> else if (attr == &dev_attr_gt_RP1_freq_mhz)
> - val = intel_gpu_freq(rps, rps->rp1_freq);
> + val = intel_rps_get_rp1_frequency(rps);
> else if (attr == &dev_attr_gt_RPn_freq_mhz)
> - val = intel_gpu_freq(rps, rps->min_freq);
> + val = intel_rps_get_rpn_frequency(rps);
> else
> BUG();
>
>
LGTM, but likely you will want someone who is more familiar with RPS to
give r-b, from my side, with typo fixed, this is:
Acked-by: Michal Wajdeczko
t > 0 ? -EPROTO : ret;
> +
> + return ret;
> +}
> +
> +static int __guc_rc_control(struct intel_guc *guc, bool enable)
> +{
> + struct intel_gt *gt = guc_to_gt(guc);
> + struct drm_device *drm = &guc_to_gt(guc)->i915->drm;
> + int ret;
> +
&
On 22.07.2021 01:51, Daniele Ceraolo Spurio wrote:
>
>
> On 7/19/2021 9:04 PM, Matthew Brost wrote:
>> On Mon, Jul 19, 2021 at 05:51:46PM -0700, Daniele Ceraolo Spurio wrote:
>>>
>>> On 7/16/2021 1:16 PM, Matthew Brost wrote:
Implement GuC context operations which includes GuC specific op
gt; /* Global engine used to submit requests to GuC */
> struct i915_sched_engine *sched_engine;
> @@ -57,6 +59,8 @@ struct intel_guc {
>
> bool submission_supported;
> bool submission_selected;
> + bool slpc_supported;
> + bool slpc_selected;
(
On 26.07.2021 21:07, Vinay Belgaumkar wrote:
> Add constants and params that are needed to configure SLPC.
>
> v2: Add a new abi header for SLPC. Replace bitfields with
> genmasks. Address other comments from Michal W.
>
> v3: Add slpc H2G format in abi, other review commments (Michal W)
>
>
)
> {
> + if (!slpc->vma)
> + return;
> +
> + i915_vma_unpin_and_release(&slpc->vma, I915_VMA_RELEASE_MAP);
> }
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
> index bfe4a7f9ce15..edcf4c05bd9f 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
> @@ -7,6 +7,8 @@
> #define _INTEL_GUC_SLPC_TYPES_H_
>
> struct intel_guc_slpc {
> + struct i915_vma *vma;
> + struct slpc_shared_data *vaddr;
> };
>
> #endif
>
Reviewed-by: Michal Wajdeczko
On 26.07.2021 21:07, Vinay Belgaumkar wrote:
> Add methods for interacting with GuC for enabling SLPC. Enable
> SLPC after GuC submission has been established. GuC load will
> fail if SLPC cannot be successfully initialized. Add various
> helper methods to set/unset the parameters for SLPC. They
On 26.07.2021 21:07, Vinay Belgaumkar wrote:
> Add param set h2g helpers to set the min and max frequencies
s/h2g/H2G
> for use by SLPC.
>
> v2: Address review comments (Michal W)
> v3: Check for positive error code (Michal W)
>
> Signed-off-by: Sundaresan Sujaritha
> Signed-off-by: Vinay B
+int intel_guc_slpc_get_min_freq(struct intel_guc_slpc *slpc, u32 *val)
> +{
> + intel_wakeref_t wakeref;
> + struct drm_i915_private *i915 = guc_to_gt(slpc_to_guc(slpc))->i915;
use slpc_to_i915() and in this order:
struct drm_i915_private *i915 = slpc_to_i915(slpc);
gt;vma)
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
> index 92d7afd44f07..d133c8020c16 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
> @@ -9,6 +9,8
On 26.07.2021 21:07, Vinay Belgaumkar wrote:
> Cache rp0, rp1 and rpn platform limits into SLPC structure
> for range checking while setting min/max frequencies.
>
> Also add "soft" limits which keep track of frequency changes
> made from userland. These are initially set to platform min
> and
: Add wrappers for getting rp0/1/n frequencies, update
> softlimits in set min/max SLPC functions. Also check for
> boundary conditions before setting them.
>
> v3: Address review comments (Michal W)
>
> Acked-by: Michal Wajdeczko
> Signed-off-by: Vinay Belgaumkar
> Sign
On 27.07.2021 22:00, Belgaumkar, Vinay wrote:
>
>
> On 7/27/2021 8:12 AM, Michal Wajdeczko wrote:
>>
>>
>> On 26.07.2021 21:07, Vinay Belgaumkar wrote:
>>> Add methods for interacting with GuC for enabling SLPC. Enable
>>> SLPC after GuC submission
elper functions to intel_guc_slpc.c/.h. Define basic
> template for SLPC structure in intel_guc_slpc_types.h. Fix copyright (Michal
> W)
>
> v3: Review comments (Michal W)
>
> v4: Include supported/selected inside slpc struct (Michal W)
>
> Reviewed-by: Michal Wajdeczko
> Sig
100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> @@ -12,6 +12,7 @@
> #include "gt/intel_engine_types.h"
>
> #include "abi/guc_actions_abi.h"
> +#include "abi/guc_actions_slpc_abi.h"
> #include "abi/guc_errors_abi.h"
> #include "abi/guc_communication_mmio_abi.h"
> #include "abi/guc_communication_ctb_abi.h"
> @@ -95,6 +96,7 @@
> #define GUC_CTL_WA 1
> #define GUC_CTL_FEATURE 2
> #define GUC_CTL_DISABLE_SCHEDULER (1 << 14)
> +#define GUC_CTL_ENABLE_SLPCBIT(2)
>
> #define GUC_CTL_DEBUG3
> #define GUC_LOG_VERBOSITY_SHIFT0
> @@ -141,6 +143,11 @@
> #define GUC_ID_TO_ENGINE_INSTANCE(guc_id) \
> (((guc_id) & GUC_ENGINE_INSTANCE_MASK) >> GUC_ENGINE_INSTANCE_SHIFT)
>
> +#define SLPC_EVENT(id,c) (\
> +FIELD_PREP(HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ID, id) | \
> +FIELD_PREP(HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ARGC, c ) \
> +)
not sure if this is right style for multi-line macro (no leading \t)
but other LGTM,
Reviewed-by: Michal Wajdeczko
> +
> static inline u8 engine_class_to_guc_class(u8 class)
> {
> BUILD_BUG_ON(GUC_RENDER_CLASS != RENDER_CLASS);
>
c.c
> @@ -500,12 +500,21 @@ static int __uc_init_hw(struct intel_uc *uc)
> if (intel_uc_uses_guc_submission(uc))
> intel_guc_submission_enable(guc);
>
> + if (intel_uc_uses_guc_slpc(uc)) {
> + ret = intel_guc_slpc_enable(&guc->slpc);
> + if (ret)
> + goto err_submission;
> + }
> +
> drm_info(&i915->drm, "%s firmware %s version %u.%u %s:%s\n",
>intel_uc_fw_type_repr(INTEL_UC_FW_TYPE_GUC), guc->fw.path,
>guc->fw.major_ver_found, guc->fw.minor_ver_found,
>"submission",
>enableddisabled(intel_uc_uses_guc_submission(uc)));
>
> + drm_info(&i915->drm, "GuC SLPC: %s\n",
> + enableddisabled(intel_uc_uses_guc_slpc(uc)));
> +
> if (intel_uc_uses_huc(uc)) {
> drm_info(&i915->drm, "%s firmware %s version %u.%u %s:%s\n",
>intel_uc_fw_type_repr(INTEL_UC_FW_TYPE_HUC),
> @@ -520,6 +529,8 @@ static int __uc_init_hw(struct intel_uc *uc)
> /*
>* We've failed to load the firmware :(
>*/
> +err_submission:
> + intel_guc_submission_disable(guc);
> err_log_capture:
> __uc_capture_load_err_log(uc);
> err_out:
>
make sure checkpatch.pl is happy with indents, with that
Reviewed-by: Michal Wajdeczko
On 28.07.2021 23:11, Vinay Belgaumkar wrote:
> Cache rp0, rp1 and rpn platform limits into SLPC structure
> for range checking while setting min/max frequencies.
>
> Also add "soft" limits which keep track of frequency changes
> made from userland. These are initially set to platform min
> and
; index bc139682ad0f..788d87ff7b58 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
> @@ -29,5 +29,7 @@ void intel_guc_slpc_init_early(struct intel_guc_slpc *slpc);
> int intel_guc_slpc_init(struct intel_guc_slpc *slpc);
> int intel_guc_slpc_enable(struct intel_guc_slpc *slpc);
> void intel_guc_slpc_fini(struct intel_guc_slpc *slpc);
> +int intel_guc_slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 val);
> +int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val);
>
> #endif
>
Reviewed-by: Michal Wajdeczko
: Add wrappers for getting rp0/1/n frequencies, update
> softlimits in set min/max SLPC functions. Also check for
> boundary conditions before setting them.
>
> v3: Address review comments (Michal W)
>
> v4: Add helper for host part of intel_rps_set_freq helpers (Michal W)
>
ER;
> + slpc->rp1_freq = REG_FIELD_GET(RP1_CAP_MASK, rp_state_cap) *
> + GT_FREQUENCY_MULTIPLIER;
> + slpc->min_freq = REG_FIELD_GET(RPN_CAP_MASK, rp_state_cap) *
> + GT_FREQUENCY_MUL
On 17.08.2021 19:20, Daniel Vetter wrote:
> On Tue, Aug 17, 2021 at 09:36:49AM -0700, Matthew Brost wrote:
>> On Tue, Aug 17, 2021 at 01:11:41PM +0200, Daniel Vetter wrote:
>>> On Mon, Aug 16, 2021 at 06:51:39AM -0700, Matthew Brost wrote:
Add GuC kernel doc for all structures added thus fa
On 17.08.2021 19:34, Daniel Vetter wrote:
> On Tue, Aug 17, 2021 at 07:27:18PM +0200, Michal Wajdeczko wrote:
>>
>>
>> On 17.08.2021 19:20, Daniel Vetter wrote:
>>> On Tue, Aug 17, 2021 at 09:36:49AM -0700, Matthew Brost wrote:
>>>> On Tue, Aug 17, 202
On 18.08.2021 16:20, Daniel Vetter wrote:
> On Thu, Jul 01, 2021 at 05:55:11PM +0200, Michal Wajdeczko wrote:
>> Instead of plain error value (%d) print more user friendly error
>> name (%pe).
>>
>> Signed-off-by: Michal Wajdeczko
>> ---
>> driver
On 18.08.2021 18:35, Daniel Vetter wrote:
> On Wed, Aug 18, 2021 at 5:11 PM Michal Wajdeczko
> wrote:
>>
>>
>>
>> On 18.08.2021 16:20, Daniel Vetter wrote:
>>> On Thu, Jul 01, 2021 at 05:55:11PM +0200, Michal Wajdeczko wrote:
>>>> Instead
On 11.05.2021 17:16, Daniel Vetter wrote:
> On Thu, May 06, 2021 at 12:13:34PM -0700, Matthew Brost wrote:
>> From: Michal Wajdeczko
>>
>> New GuC firmware will unify format of MMIO and CTB H2G messages.
>> Introduce their definitions now to allow gradual transition
On 28.06.2021 01:14, Matthew Brost wrote:
> Add non blocking CTB send function, intel_guc_send_nb. GuC submission
> will send CTBs in the critical path and does not need to wait for these
> CTBs to complete before moving on, hence the need for this new function.
>
> The non-blocking CTB now mus
On 28.06.2021 01:14, Matthew Brost wrote:
> Implement a stall timer which fails H2G CTBs once a period of time
> with no forward progress is reached to prevent deadlock.
>
> v2:
> (Michal)
> - Improve error message in ct_deadlock()
> - Set broken when ct_deadlock() returns true
> - Retur
IO, in the meantime this
value will be passed to ERR_PTR that could be misleading.
v2: rebased
Reported-by: Dan Carpenter
Signed-off-by: Michal Wajdeczko
Cc: Dan Carpenter
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/d
Instead of plain error value (%d) print more user friendly error
name (%pe).
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
b/drivers/gpu/drm
Instead of plain error value (%d) print more user friendly error
name (%pe).
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
b/drivers/gpu/drm/i915/gt
If we timeout waiting for a CT reply we print very simple error
message. Improve that and by moving error reporting to the caller
we can use CT_ERROR instead of DRM_ERROR and report just fence
as error code will be reported later anyway.
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915
There was a gap in handling MMIO result from CTB (de)registration
and while fixing it improve some other error reports.
Signed-off-by: Michal Wajdeczko
Michal Wajdeczko (4):
drm/i915/guc: Verify result from CTB (de)register action
drm/i915/guc: Print error name on CTB (de)registration
Make CTB Header explicit and separate from CTB Message.
Signed-off-by: Michal Wajdeczko
Cc: Matthew Brost
---
.../gt/uc/abi/guc_communication_ctb_abi.h | 51 +++
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 24 -
2 files changed, 43 insertions(+), 32 deletions
On 02.07.2021 10:13, Martin Peres wrote:
> On 01/07/2021 21:24, Martin Peres wrote:
> [...]
>>>
> + i915->params.enable_guc = ENABLE_GUC_LOAD_HUC;
> + return;
> + }
> +
> + /* Default: enable HuC authentication and GuC submission */
> + i915->p
On 02.07.2021 15:12, Martin Peres wrote:
> On 02/07/2021 16:06, Michal Wajdeczko wrote:
>>
>>
>> On 02.07.2021 10:13, Martin Peres wrote:
>>> On 01/07/2021 21:24, Martin Peres wrote:
>>> [...]
>>>>>
>>>>>>
>>>>
21 11:14, Pekka Paalanen wrote:
>>>>> On Wed, 30 Jun 2021 11:58:25 -0700
>>>>> John Harrison wrote:
>>>>>
>>>>>> On 6/30/2021 01:22, Martin Peres wrote:
>>>>>>> On 24/06/2021 10:05, Matthew Brost wrote:
>
On 06.07.2021 21:00, John Harrison wrote:
> On 7/1/2021 10:15, Matthew Brost wrote:
>> CTB writes are now in the path of command submission and should be
>> optimized for performance. Rather than reading CTB descriptor values
>> (e.g. head, tail) which could result in accesses across the PCIe bu
On 06.07.2021 21:19, John Harrison wrote:
> On 7/6/2021 12:12, Michal Wajdeczko wrote:
>> On 06.07.2021 21:00, John Harrison wrote:
>>> On 7/1/2021 10:15, Matthew Brost wrote:
>>>> CTB writes are now in the path of command submission and should be
>>>&
Hi John,
On 26.06.2021 02:45, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> There is a new HuC version available for TGL and compatible platforms,
> so switch to using it. Also, there is now a GuC and HuC for ADL-P, so
> use those too.
I recall discussion about splitting UC_FW meta
On 07.07.2021 02:57, John Harrison wrote:
> On 7/3/2021 01:21, Martin Peres wrote:
>> On 02/07/2021 18:07, Michal Wajdeczko wrote:
>>> On 02.07.2021 10:09, Martin Peres wrote:
>>>> On 02/07/2021 10:29, Pekka Paalanen wrote:
>>>>> On Thu, 1 Jul 2
Hi,
On 07.07.2021 21:09, Matthew Brost wrote:
> CTB writes are now in the path of command submission and should be
> optimized for performance. Rather than reading CTB descriptor values
> (e.g. head, tail) which could result in accesses across the PCIe bus,
> store shadow local copies and only rea
re there is a space including extra dw for the header */
> - if (unlikely(used + len + GUC_CTB_HDR_LEN >= size))
> - return -ENOSPC;
> +#endif
>
> /*
>* dw0: CT header (including fence)
> @@ -452,6 +451,10 @@ static int ct_write(struct intel_guc_c
Hi Vinay,
On 10.07.2021 03:20, Vinay Belgaumkar wrote:
> Add macros to check for slpc support. This feature is currently supported
> for gen12+ and enabled whenever guc submission is enabled/selected.
please try to use consistent names across all patches:
s/slpc/SLPC
s/gen12/Gen12
s/guc/GuC
>
On 10.07.2021 03:20, Vinay Belgaumkar wrote:
> Declare header and source files for SLPC, along with init and
> enable/disable function templates.
later you claim that "disable" is not needed
>
> Signed-off-by: Vinay Belgaumkar
> Signed-off-by: Sundaresan Sujaritha
> ---
> drivers/gpu/drm/i
On 10.07.2021 03:20, Vinay Belgaumkar wrote:
> Replicate the SLPC header file in GuC for the most part. There are
what you mean by "replicate" here?
> some SLPC mode based parameters which haven't been included since
> we are not using them.
>
> Signed-off-by: Vinay Belgaumkar
> Signed-off-b
On 10.07.2021 03:20, Vinay Belgaumkar wrote:
> Allocate data structures for SLPC and functions for
> initializing on host side.
>
> Signed-off-by: Vinay Belgaumkar
> Signed-off-by: Sundaresan Sujaritha
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 11 +++
> drivers/gpu/drm/i915/g
On 10.07.2021 03:20, Vinay Belgaumkar wrote:
> Add methods for interacting with guc for enabling SLPC. Enable
> SLPC after guc submission has been established. GuC load will
s/guc/GuC
> fail if SLPC cannot be successfully initialized. Add various
> helper methods to set/unset the parameters fo
On 10.07.2021 03:20, Vinay Belgaumkar wrote:
> Add param set h2g helpers to set the min and max frequencies
> for use by SLPC.
>
> Signed-off-by: Sundaresan Sujaritha
> Signed-off-by: Vinay Belgaumkar
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 94 +
> drivers/g
On 10.07.2021 03:20, Vinay Belgaumkar wrote:
> Add helpers to read the min/max frequency being used
> by SLPC. This is done by send a h2g command which forces
s/h2g/H2G
> SLPC to update the shared data struct which can then be
> read.
>
> Signed-off-by: Vinay Belgaumkar
> Signed-off-by: Sund
On 10.07.2021 03:20, Vinay Belgaumkar wrote:
> This prints out relevant SLPC info from the SLPC shared structure.
>
> We will send a h2g message which forces SLPC to update the
> shared data structure with latest information before reading it.
>
> Signed-off-by: Vinay Belgaumkar
> Signed-off-
On 10.07.2021 03:20, Vinay Belgaumkar wrote:
> Cache rp0, rp1 and rpn platform limits into slpc structure
> for range checking while setting min/max frequencies.
>
> Also add "soft" limits which keep track of frequency changes
> made from userland. These are initially set to platform min
> and
On 10.07.2021 03:20, Vinay Belgaumkar wrote:
> Update the get/set min/max freq hooks to work for
> slpc case as well. Consolidate helpers for requested/min/max
> frequency get/set to intel_rps where the proper action can
> be taken depending on whether slpc is enabled.
2x s/slpc/SLPC
>
> Sign
On 10.07.2021 03:20, Vinay Belgaumkar wrote:
> Tests that exercise the slpc get/set frequency interfaces.
>
> Clamp_max will set max frequency to multiple levels and check
> that slpc requests frequency lower than or equal to it.
>
> Clamp_min will set min frequency to different levels and che
On 10.07.2021 03:20, Vinay Belgaumkar wrote:
> This feature hands over the control of HW RC6 to the GUC.
> GUC decides when to put HW into RC6 based on it's internal
> busyness algorithms.
>
> GUCRC needs GUC submission to be enabled, and only
> supported on Gen12+ for now.
>
> When GUCRC is e
On 24.06.2021 09:04, Matthew Brost wrote:
> Update GuC debugfs to support the new GuC structures.
>
> Signed-off-by: John Harrison
> Signed-off-by: Matthew Brost
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 22
> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 3 ++
> ..
On 19.03.2022 00:39, Andi Shyti wrote:
> From: Tvrtko Ursulin
>
> On a multi-tile platform, each tile has its own registers + GGTT
> space, and BAR 0 is extended to cover all of them.
>
> Up to four GTs are supported in i915->gt[], with slot zero
> shadowing the existing i915->gt0 to enable s
On 21.03.2022 22:14, Lucas De Marchi wrote:
> On Thu, Mar 03, 2022 at 11:30:10PM +0530, Balasubramani Vivekanandan wrote:
>> memcpy_from_wc functions in i915_memcpy.c will be removed and replaced
>> by the implementation in drm_cache.c.
>> Updated to use the functions provided by drm_cache.c.
>>
get size
>- Add has_guc_hwconfig to devinfo and drop has_table()
>- Change drm_err to notice in __uc_init_hw() and use %pe
>
> Cc: Michal Wajdeczko
> Signed-off-by: Rodrigo Vivi
> Signed-off-by: John Harrison
> Reviewed-by: Matthew Brost
> Acked-by: Jon Bloomfield
&g
- Replace hwconfig param with guc in __guc_action_get_hwconfig()
>>> - Move zero size check into guc_hwconfig_discover_size()
>>> - Change comment to say zero size offset/size is needed to get size
>>> - Add has_guc_hwconfig to devinfo and drop has_table
On 25.02.2022 18:18, Tvrtko Ursulin wrote:
>
> On 25/02/2022 16:46, John Harrison wrote:
>
driver we don't care that much that we failed to load HWconfig and
'notice' is enough.
but I'm fine with all messages being drm_err (as we will not have to
change that once again
On 17.02.2022 15:41, Andi Shyti wrote:
> With the upcoming multitile support each tile will have its own
> local memory. Mark the current LMEM with the suffix '0' to
> emphasise that it belongs to the root tile.
>
> Suggested-by: Michal Wajdeczko
> Signed-off-by:
On 17.02.2022 15:41, Andi Shyti wrote:
> The "gt_is_root(struct intel_gt *gt)" helper return true if the
> gt is the root gt, which means that its id is 0. Return false
> otherwise.
>
> Suggested-by: Michal Wajdeczko
> Signed-off-by: Andi Shyti
> ---
> driv
On 17.02.2022 15:41, Andi Shyti wrote:
> From: Sujaritha Sundaresan
>
> This patch adds the following new sysfs frequency attributes;
> - punit_req_freq_mhz
> - throttle_reason_status
> - throttle_reason_pl1
> - throttle_reason_pl2
> - throttle_reason_pl4
>
.
but the point of this exercise is not to handle such error but to
gracefully abort probe without panic or leaks. note that we are already
using -ENXIO in many other injected failure points (mostly in uc code)
thus for me above change is also fine and the whole series is:
Reviewed-by: Michal Wa
On 12.10.2021 18:16, Jani Nikula wrote:
> On Mon, 11 Oct 2021, Matthew Brost wrote:
>> On Mon, Oct 11, 2021 at 08:51:03PM +0530, Thanneeru Srinivasulu wrote:
>>> Replace DRM_ERROR with CT_PROBE_ERROR to report early CTB failures.
>>>
>>> Signed-off-by: Thanneeru Srinivasulu
>>
>> Reviewed-by:
We assumed that for all modern GENs the PTEs and register space are
split in the GTTMMADR BAR, but while it is true, we should rather use
fixed offset as it is defined in the specification.
Bspec: 4409, 4457, 4604, 11181, 9027, 13246, 13321, 44980
Signed-off-by: Michal Wajdeczko
Cc: CQ Tang
Cc
Hi Andi,
please find few late nits below
On 17.01.2022 20:32, Andi Shyti wrote:
> From: Tvrtko Ursulin
>
> On a multi-tile platform, each tile has its own registers + GGTT
> space, and BAR 0 is extended to cover all of them.
>
> Up to four gts are supported in i915->gt[], with slot zero
s/gts
Hi Andi,
few more late nits below
On 17.01.2022 20:32, Andi Shyti wrote:
> The GT has its own properties and in sysfs they should be grouped
> in the 'gt/' directory.
>
> Create a 'gt/' directory in sysfs which will contain gt0...gtN
> directories related to each tile configured in the GPU. Move
On 01.12.2021 01:38, Lucas De Marchi wrote:
> On Wed, Dec 01, 2021 at 12:41:08AM +0200, Andi Shyti wrote:
>> Hi Lucas,
>>
>> fist of all thanks for taking a look at this, I was eagerly
>> waiting for reviewers.
>>
>> On Tue, Nov 30, 2021 at 01:07:30PM -0800, Lucas De Marchi wrote:
>>> On Sun, No
or the exception case, the GuC is
> basically dead. The KMD will detect this via the heartbeat and trigger
> both an error log (which will include the crash dump as part of the
> GuC log) and a GT reset. So no other processing is really required.
>
> Signed-off-by: John Harrison
> S
On 11.01.2022 17:30, Matthew Brost wrote:
> Move the multi-lrc guc_id from the lower allocation partition (0 to
> number of multi-lrc guc_ids) to upper allocation partition (number of
> single-lrc to max guc_ids).
>
> Signed-off-by: Matthew Brost
> ---
> .../gpu/drm/i915/gt/uc/intel_guc_submi
On 13.01.2022 00:26, Matthew Brost wrote:
> On Thu, Jan 13, 2022 at 12:21:17AM +0100, Michal Wajdeczko wrote:
>> On 11.01.2022 17:30, Matthew Brost wrote:
...
>>> @@ -1863,6 +1861,33 @@ static void guc_submit_request(struct i915_request
>>> *rq)
>>>
On 02.06.2022 19:21, Zhanjun Dong wrote:
> We are seeing error message of "No response for request". Some cases happened
> while waiting for response and reset/suspend action was triggered. In this
> case, no response is not an error, active requests will be cancelled.
>
> This patch will handl
On 13.01.2022 17:27, Matthew Brost wrote:
> Move the multi-lrc guc_id from the lower allocation partition (0 to
> number of multi-lrc guc_ids) to upper allocation partition (number of
> single-lrc to max guc_ids).
>
> This will help when a native driver transitions to a PF after driver
> load t
;
> Note that the table is only available on ADL-P and later platforms.
>
> Cc: Michal Wajdeczko
> Signed-off-by: Rodrigo Vivi
> Signed-off-by: John Harrison
> Reviewed-by: Matthew Brost
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> .../gp
On 08.02.2022 22:05, Jordan Justen wrote:
> i915_drm.h now defines the format of the returned
> DRM_I915_QUERY_HWCONFIG_BLOB query item. Since i915 receives this from
> the black box GuC software, it should verify that the data matches
> that format before sending it to user-space.
>
> The veri
On 01.09.2022 09:45, Jani Nikula wrote:
> On Wed, 31 Aug 2022, Radhakrishna Sripada
> wrote:
...
>> struct ip_version graphics;
>> +struct ip_version media;
>> +struct ip_version display;
>
> The runtime display info is now in an unnamed struct under struct
> intel_runtime_info
On 14.07.2022 14:06, Mauro Carvalho Chehab wrote:
> From: Prathap Kumar Valsan
>
> Add routines to interface with GuC firmware for TLB invalidation.
>
> Signed-off-by: Prathap Kumar Valsan
> Cc: Bruce Chang
> Cc: Michal Wajdeczko
> Cc: Matthew Brost
> Cc: Ch
On 14.07.2022 14:06, Mauro Carvalho Chehab wrote:
> From: Prathap Kumar Valsan
>
> Add routines to interface with GuC firmware for selective TLB invalidation
> supported on XeHP.
>
> Signed-off-by: Prathap Kumar Valsan
> Cc: Matthew Brost
> Signed-off-by: Mauro Carvalho Chehab
> ---
>
> T
On 28.07.2022 04:42, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> When the KMD sends a CLIENT_RESET request to GuC (as part of the
> suspend sequence), GuC will mark the CTB buffer as 'UNUSED'. If the
hmm, GuC shouldn't do that on CLIENT_RESET, GuC shall only mark CTB as
UNUSED
t; {
> switch (type) {
> @@ -264,7 +266,7 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
> err_deregister:
> ct_deregister_buffer(ct, INTEL_GUC_CT_BUFFER_TYPE_RECV);
> err_out:
> - CT_ERROR(ct, "Failed to open open CT channel (err=%d)\n", err);
> + CT_PROBE_ERROR(ct, "Failed to open channel (err=%d)\n", err);
nit: while here we can start using %pe to print error
Reviewed-by: Michal Wajdeczko
> return err;
> }
>
>
nay Belgaumkar
> Signed-off-by: Rodrigo Vivi
> Signed-off-by: Matthew Brost
Acked-by: Michal Wajdeczko
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 16
> drivers/gpu/drm/i915/gt/uc/intel_guc.h | 1 -
> drivers/gpu/drm/i915/gt/uc/intel_guc_fwif
aolo Spurio
> Signed-off-by: Matthew Brost
> Cc: Michal Wajdeczko
> Cc: John Harrison
> ---
> drivers/gpu/drm/i915/i915_params.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_params.h
> b/drivers/gpu/drm/i915/i915_pa
On 06.05.2021 21:13, Matthew Brost wrote:
> Improve the error message when a unsolicited CT response is received by
> printing fence that couldn't be found, the last fence, and all requests
> with a response outstanding.
>
> Signed-off-by: Matthew Brost
> ---
> drivers/gpu/drm/i915/gt/uc/inte
On 06.05.2021 21:13, Matthew Brost wrote:
> Add non blocking CTB send function, intel_guc_send_nb. In order to
> support a non blocking CTB send function a spin lock is needed to
spin lock was added in 16/97
> protect the CTB descriptors fields. Also the non blocking call must not
> update the
On 06.05.2021 21:13, Matthew Brost wrote:
> Implement a stall timer which fails H2G CTBs once a period of time
> with no forward progress is reached to prevent deadlock.
>
> Also update to ct_write to return -EDEADLK rather than -EPIPE on a
> corrupted descriptor.
broken descriptor is really s
On 06.05.2021 21:13, Matthew Brost wrote:
> CTB writes are now in the path of command submission and should be
> optimized for performance. Rather than reading CTB descriptor values
> (e.g. head, tail, size) which could result in accesses across the PCIe
size was removed from the descriptor in
On 06.05.2021 21:13, Matthew Brost wrote:
> With the introduction of non-blocking CTBs more than one CTB can be in
> flight at a time. Increasing the size of the CTBs should reduce how
> often software hits the case where no space is available in the CTB
> buffer.
>
> Cc: John Harrison
> Signe
nt err;
>
> + err = i915_inject_probe_error(guc_to_gt(guc)->i915, -ENXIO);
> + if (err)
> + return err;
> +
> GEM_BUG_ON(ct->vma);
>
> blob_size = 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE +
> CTB_G2H_BUFFER_SIZE;
>
likely could be introduced earlier, maybe right after patch 5/97
Reviewed-by: Michal Wajdeczko
On 25.05.2021 04:47, Matthew Brost wrote:
> On Thu, May 06, 2021 at 12:13:25PM -0700, Matthew Brost wrote:
>> From: Michal Wajdeczko
>>
>> In upcoming GuC firmware, CTB size will be removed from the CTB
>> descriptor so we must keep it locally for any calculations.
On 25.05.2021 04:53, Matthew Brost wrote:
> On Thu, May 06, 2021 at 12:13:26PM -0700, Matthew Brost wrote:
>> From: Michal Wajdeczko
>>
>> We can retrieve offsets to cmds buffers and descriptor from
>> actual pointers that we already keep locally.
>>
&
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