On 3/12/2025 1:34 AM, Chen Ni wrote:
'destroy_workqueue()' already drains the queue before destroying it, so
there is no need to flush it explicitly.
Remove the redundant 'flush_workqueue()' calls.
This was generated with coccinelle:
@@
expression E;
@@
- flush_workqueue(E);
destroy_workque
- flush_workqueue(E);
destroy_workqueue(E);
Signed-off-by: Chen Ni
Reviewed-by: Jeff Hugo
On 3/6/2025 11:03 AM, Lizhi Hou wrote:
+struct drm_gem_object *
+amdxdna_gem_prime_import(struct drm_device *dev, struct dma_buf *dma_buf)
+{
+ struct dma_buf_attachment *attach;
+ struct drm_gem_object *gobj;
+ struct sg_table *sgt;
+ int ret;
+
+ attach = dma_buf_a
On 2/25/2025 12:55 AM, Tomeu Vizoso wrote:
diff --git a/Documentation/accel/rocket/index.rst b/Documentation/accel/rocket/index.rst
new file mode 100644
index
..ad33194dec0325d0dab362768fd349e8dc286970
--- /dev/null
+++ b/Documentation/accel/rocket/inde
On 2/25/2025 12:55 AM, Tomeu Vizoso wrote:
+/**
+ * struct drm_rocket_task - A task to be run on the NPU
+ *
+ * A task is the smallest unit of work that can be run on the NPU.
+ */
+struct drm_rocket_task {
+ /** DMA address to NPU mapping of register command buffer */
+ __u64 regcmd
On 3/7/2025 1:41 AM, Dan Carpenter wrote:
These are u64 variables that come from the user via
qaic_attach_slice_bo_ioctl(). Use check_add_overflow() to ensure that
the math doesn't have an integer wrapping bug.
Cc: sta...@vger.kernel.org
Fixes: ff13be830333 ("accel/qaic: Add datapath")
Signed-o
h")
Signed-off-by: Dan Carpenter
Thanks!
Reviewed-by: Jeff Hugo
if it is exported and imported
by an application. Use a link list to track VMAs the BO been mapped.
Signed-off-by: Lizhi Hou
Reviewed-by: Jeff Hugo
I think this was just a one time glitch, but please remember to include
a changelog for v2+.
On 3/6/2025 10:19 AM, Jeff Hugo wrote:
From: Jeffrey Hugo
When slicing a BO, we need to iterate through the BO's sgt to find the
right pieces to construct the slice. Some of the data types chosen for
this process are incorrectly too small, and can overflow. This can
result in the inco
onfig | 1 -
For qaic:
Acked-by: Jeff Hugo
: Thomas Zimmermann
Reviewed-by: Jeff Hugo
On 4/8/2025 5:52 AM, Thomas Zimmermann wrote:
Instead of testing import_attach for imported GEM buffers, invoke
drm_gem_is_imported() to do the test. The helper tests the dma_buf
itself while import_attach is just an artifact of the import. Prepares
to make import_attach optional.
Signed-off-by:
t;)
Signed-off-by: Lizhi Hou
Reviewed-by: Jeff Hugo
On 4/8/2025 8:55 AM, Falkowski, Maciej wrote:
On 4/4/2025 5:13 PM, Jeff Hugo wrote:
On 4/1/2025 9:59 AM, Maciej Falkowski wrote:
From: Andrzej Kacprowski
Add sysfs files that show maximum and current
frequency of the NPU's data processing unit.
New sysfs entries:
- npu_max_frequenc
On 4/9/2025 11:30 AM, Nipun Gupta wrote:
No cover letter?
Add binding documentation for AMD PKI accelerator supported for AMD
versal-net SoC.
AMD PKI accelerator is a device on AMD versa-net SoC to execute public key
asymmetric crypto operations like ECDSA, ECDH, RSA etc. with high performance
On 4/9/2025 11:30 AM, Nipun Gupta wrote:
The AMD PKI accelerator driver provides a accel interface to interact
"an accel"
with the device for offloading and accelerating asymmetric crypto
operations.
Signed-off-by: Nipun Gupta
---
Changes RFC->v2:
- moved from misc to accel
- added archite
accordingly to HW architecture specification.
Fixes: a19bffb10c46 ("accel/ivpu: Implement DCT handling")
Signed-off-by: Karol Wachowski
Signed-off-by: Maciej Falkowski
Reviewed-by: Jeff Hugo
by: Maciej Falkowski
Reviewed-by: Jeff Hugo
s all
known workloads. Also, I think a comment on PM_TDR_HEARTBEAT_LIMIT that
tells how long the limit is (60 seconds) would be helpful to future
readers, instead of needing to parse through multiple functions and how
they all interact.
With the commit text update -
Reviewed-by: Jeff Hugo
pu: Add FW state dump on TDR")
Cc: # v6.13+
Signed-off-by: Jacek Lawrynowicz
Reviewed-by: Jeff Hugo
As a side note, my email address changed a little bit ago, but I suspect
you are not aware as I'm still getting patches addressed to my old
address. While I still have access to the
6f0
[ 3443.180289] do_syscall_64+0x62/0x180
[ 3443.180291] entry_SYSCALL_64_after_hwframe+0x71/0x79
Fixes: 465a3914b254 ("accel/ivpu: Add API for command queue
create/destroy/submit")
Signed-off-by: Jacek Lawrynowicz
Reviewed-by: Jeff Hugo
On 4/25/2025 3:36 AM, Jacek Lawrynowicz wrote:
From: Karol Wachowski
The mutex unlock for vdev->submitted_jobs_lock was incorrectly placed
after unlocking file_priv->lock. Change order of unlocks to avoid potential
This should read "before unlocking", right?
race conditions.
Fixes: 5bbccad
On 4/28/2025 12:47 AM, Jacek Lawrynowicz wrote:
Hi,
On 4/25/2025 7:22 PM, Jeff Hugo wrote:
On 4/25/2025 3:36 AM, Jacek Lawrynowicz wrote:
From: Karol Wachowski
The mutex unlock for vdev->submitted_jobs_lock was incorrectly placed
after unlocking file_priv->lock. Change order of unlo
On 4/29/2025 2:41 AM, Jacek Lawrynowicz wrote:
Hi,
On 4/28/2025 4:21 PM, Jeff Hugo wrote:
On 4/28/2025 12:47 AM, Jacek Lawrynowicz wrote:
Hi,
On 4/25/2025 7:22 PM, Jeff Hugo wrote:
On 4/25/2025 3:36 AM, Jacek Lawrynowicz wrote:
From: Karol Wachowski
The mutex unlock for vdev
sible on the system. That is the
definition of size_t, so use it.
Fixes: ff13be830333 ("accel/qaic: Add datapath")
Signed-off-by: Jeffrey Hugo
Signed-off-by: Jeff Hugo
---
drivers/accel/qaic/qaic_data.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/dri
On 3/5/2025 8:53 AM, Dan Carpenter wrote:
These are u64 variables that come from the user via
qaic_attach_slice_bo_ioctl(). Ensure that the math doesn't have an
integer wrapping bug.
Cc: sta...@vger.kernel.org
Fixes: ff13be830333 ("accel/qaic: Add datapath")
Signed-off-by: Dan Carpenter
---
Qualcomm is migrating away from quicinc.com email addresses towards ones
with *.qualcomm.com.
Signed-off-by: Jeff Hugo
---
.mailmap| 3 ++-
MAINTAINERS | 2 +-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/.mailmap b/.mailmap
index ae0adc499f4a..f4b927e48ad1 100644
--- a
On 2/14/2025 9:21 AM, Jeffrey Hugo wrote:
If mhi_fw_load_handler() bails out early because the EE is not capable
of loading firmware, we may reference fw_load_type in cleanup which is
uninitialized at this point. The cleanup code checks fw_load_type as a
proxy for knowing if fbc_image was allocat
On 2/19/2025 2:41 PM, Jeff Hugo wrote:
Qualcomm is migrating away from quicinc.com email addresses towards ones
with *.qualcomm.com.
Signed-off-by: Jeff Hugo
Pushed to drm-misc-next
-Jeff
ned-off-by: Maciej Falkowski
Reviewed-by: Jeff Hugo
On 4/1/2025 9:59 AM, Maciej Falkowski wrote:
From: Karol Wachowski
Add tracking of command queue ID in JOB debug message to improve
debugging capabilities.
Signed-off-by: Karol Wachowski
Signed-off-by: Maciej Falkowski
Reviewed-by: Jeff Hugo
When reviewing this patch, I noticed the
buffers allocations,
if those new fields are zeroed use old values instead.
Signed-off-by: Karol Wachowski
Signed-off-by: Maciej Falkowski
Reviewed-by: Jeff Hugo
On 4/1/2025 9:59 AM, Maciej Falkowski wrote:
From: Andrzej Kacprowski
Add sysfs files that show maximum and current
frequency of the NPU's data processing unit.
New sysfs entries:
- npu_max_frequency_mhz
Don't you have an ioctl to get this, which is fixed in patch 1 of the
series? Why dupli
s unanswered.
With that
Reviewed-by: Jeff Hugo
all be reported via other mechanisms like AER, maintain counts of
the number of errors observed for each type.
Signed-off-by: Jeff Hugo
---
Documentation/ABI/testing/sysfs-driver-qaic | 18 +
MAINTAINERS | 1 +
drivers/accel/qaic/Makefile | 1
we can catch more memory
corruption issues
Fixes: 37dee2a2f433 ("accel/ivpu: Improve buffer object debug logs")
Cc: # v6.8+
Signed-off-by: Jacek Lawrynowicz
Reviewed-by: Jeff Hugo
it is safe to remove. Maybe it make sense to mention this
in commit message :)
Sounds great.
Reviewed-by: Lizhi Hou
Reviewed-by: Jeff Hugo
On 5/13/2025 3:53 AM, Jacek Lawrynowicz wrote:
Hi,
On 5/12/2025 9:49 PM, Jeff Hugo wrote:
diff --git a/drivers/accel/qaic/qaic_ras.c b/drivers/accel/qaic/qaic_ras.c
new file mode 100644
index ..2f8c1f08dbc0
--- /dev/null
+++ b/drivers/accel/qaic/qaic_ras.c
@@ -0,0 +1,629
On 5/13/2025 10:13 AM, Jacek Lawrynowicz wrote:
Hi,
On 5/13/2025 5:05 PM, Jeff Hugo wrote:
On 5/13/2025 3:53 AM, Jacek Lawrynowicz wrote:
Hi,
On 5/12/2025 9:49 PM, Jeff Hugo wrote:
diff --git a/drivers/accel/qaic/qaic_ras.c b/drivers/accel/qaic/qaic_ras.c
new file mode 100644
index
all be reported via other mechanisms like AER, maintain counts of
the number of errors observed for each type.
Signed-off-by: Jeff Hugo
---
v2:
-Fix SPDX comment in header
-New line before #endif in header
-Add a comment about printk() use
-Print err_threshold
Documentation/ABI/testing/sysfs
preventing unnecessary NOP operation.
Fixes: 465a3914b254 ("accel/ivpu: Add API for command queue
create/destroy/submit")
Signed-off-by: Karol Wachowski
Signed-off-by: Jacek Lawrynowicz
Reviewed-by: Jeff Hugo
between
inference timeout and tdr timeout.
Signed-off-by: Karol Wachowski
Signed-off-by: Jacek Lawrynowicz
Reviewed-by: Jeff Hugo
On 6/2/2025 8:43 AM, Simona Vetter wrote:
On Wed, May 28, 2025 at 09:15:22AM -0600, Jeff Hugo wrote:
On 5/28/2025 3:13 AM, Simona Vetter wrote:
Handles are per-file, not global, so this makes no sense. Plus it's
set only after calling drm_gem_handle_create(), and drivers are not
allow
On 6/4/2025 9:44 AM, Maciej Falkowski wrote:
From: Karol Wachowski
Refactor ivpu_cmdq_unregister() to ensure the doorbell is unregistered
before destroying the command queue. The NPU firmware requires doorbells
to be unregistered prior to command queue destruction.
If doorbell remains register
On 5/16/2025 10:06 AM, Jeff Hugo wrote:
AIC100 devices generates Reliability, Availability, Serviceability events
via MHI QAIC_STATUS channel. Support such events and print a structured
log with details of the events, and if the event describes an uncorrected
error, reset the device to put it
essed from the CPU.
Initially based on the same IOCTLs from the Etnaviv driver.
v2:
- Don't break UABI by reordering the IOCTL IDs (Jeff Hugo)
v3:
- Check that padding fields in IOCTLs are zero (Jeff Hugo)
Signed-off-by: Tomeu Vizoso
Assuming what Lucas pointed out is addressed,
Reviewe
On 5/20/2025 4:27 AM, Tomeu Vizoso wrote:
- version = rocket_pc_read(core, VERSION);
- version += rocket_pc_read(core, VERSION_NUM) & 0x;
+ version = rocket_pc_readl(core, VERSION);
+ version += rocket_pc_readl(core, VERSION_NUM) & 0x;
This seems weird. Feels li
On 5/20/2025 4:26 AM, Tomeu Vizoso wrote:
diff --git a/drivers/accel/rocket/rocket_device.h
b/drivers/accel/rocket/rocket_device.h
new file mode 100644
index
..55f4da252cfbd1f102c56e5009472deff59aaaec
--- /dev/null
+++ b/drivers/accel/rocket/rocket_device
much for the audit.
Since we're still holding a reference to the bo nothing bad can
happen, hence not cc: stable material.
Cc: Jeff Hugo
Cc: Carl Vanderlip
Cc: linux-arm-...@vger.kernel.org
Signed-off-by: Simona Vetter
Signed-off-by: Simona Vetter
SOB chain seems weird to me. I got th
d-off-by: Jacek Lawrynowicz
Reviewed-by: Jeff Hugo
On 6/5/2025 10:19 AM, Maciej Falkowski wrote:
Add support for Wildcat Lake (WCL) CPUs.
Wildcat Lake contains NPU5 just like Panther Lake
hence the initial support is very simple and adds
only PCI IDs.
Signed-off-by: Maciej Falkowski
Reviewed-by: Jeff Hugo
which helps enormously with removing it
:-)
Since we're still holding a reference to the bo nothing bad can
happen, hence not cc: stable material.
Cc: Jeff Hugo
Cc: Carl Vanderlip
Cc: linux-arm-...@vger.kernel.org
Signed-off-by: Simona Vetter
Signed-off-by: Simona Vetter
Pushed to drm
On 6/5/2025 10:20 AM, Maciej Falkowski wrote:
From: Andrzej Kacprowski
Introduces a new parameter to the DRM_IVPU_CMDQ_CREATE ioctl,
Introduce
enabling turbo mode for jobs submitted via the command queue.
Turbo mode allows jobs to run at higher frequencies,
potentially improving performance
On 6/12/2025 7:31 AM, Falkowski, Maciej wrote:
On 6/6/2025 6:30 PM, Jeff Hugo wrote:
On 6/5/2025 10:20 AM, Maciej Falkowski wrote:
From: Andrzej Kacprowski
Introduces a new parameter to the DRM_IVPU_CMDQ_CREATE ioctl,
Introduce
Ack, thanks.
enabling turbo mode for jobs submitted via
On 6/10/2025 4:36 PM, Stephen Rothwell wrote:
Hi Jeff,
On Tue, 10 Jun 2025 11:59:12 -0600 Jeff Hugo wrote:
pci_printk() was removed with commit 1c8a0ed2043c ("PCI: Remove unused
pci_printk()")
so change to using dev_printk().
Fixes: c11a50b170e7 ("accel/qaic: Add Reliability
On 6/9/2025 9:46 PM, Lukas Wunner wrote:
On Tue, Jun 10, 2025 at 12:48:09PM +1000, Stephen Rothwell wrote:
After merging the drm-misc tree, today's linux-next build (x86_64
allmodconfig) failed like this:
drivers/accel/qaic/qaic_ras.c: In function 'decode_ras_msg':
drivers/accel/qaic/qaic_ras.c
20250610124809.1e1ff...@canb.auug.org.au/
Signed-off-by: Jeff Hugo
---
drivers/accel/qaic/qaic_ras.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/accel/qaic/qaic_ras.c b/drivers/accel/qaic/qaic_ras.c
index 39c6f9cf98cc..914ffc4a9970 100644
---
On 7/1/2025 7:02 AM, Khatri, Sunil wrote:
[AMD Official Use Only - AMD Internal Distribution Only]
I cannot review this message with this restriction. In my opinion, your
email client is not properly configured for interfacing with the community.
-Jeff
On 7/1/2025 12:14 AM, Khatri, Sunil wrote:
On 6/30/2025 8:49 PM, Jeff Hugo wrote:
On 6/30/2025 8:36 AM, Sunil Khatri wrote:
I don't see a cover letter on list. Surely there should be one?
Yes there is one with the first version of patches.
I don't even see a v1 on the list for
On 6/30/2025 8:36 AM, Sunil Khatri wrote:
I don't see a cover letter on list. Surely there should be one?
Looks like you didn't send this to the Accel maintainer. Did you forget
to run the get_maintainers/pl script?
Move the debugfs accel driver code to the drm layer
and it is an intermediat
s own commit (Thomas Zimmermann)
- Misc. cleanups (Thomas Zimmermann and Jeff Hugo)
- Make use of GPL-2.0-only for the copyright notice (Jeff Hugo)
- PM improvements (Nicolas Frattaroli)
v4:
- Use bulk clk API (Krzysztof Kozlowski)
v6:
- Remove mention to NVDLA, as the hardware is only incidentally re
On 7/13/2025 2:38 AM, Tomeu Vizoso wrote:
A XML file was generated with the data from the TRM, and then this
header was generated from it.
The canonical location for the XML file is the Mesa3D repository.
v3:
- Make use of GPL-2.0-only for the copyright notice (Jeff Hugo)
v8:
- Remove full
on Panfrost.
v2:
- Remove hardcoded number of cores
- Misc. style fixes (Jeffrey Hugo)
- Repack IOCTL struct (Jeffrey Hugo)
v3:
- Adapt to a split of the register block in the DT bindings (Nicolas
Frattaroli)
- Make use of GPL-2.0-only for the copyright notice (Jeff Hugo)
- Use drm_* logging
from drm_drv.c and drm_accel.c
to drm_debugfs.c This enables debugfs root node reference
directly drm_debugfs.c and hence enable to create per client-id
directory.
v8: Create drm_accel dentry only if it's config is enabled (Jeff, Hugo)
v8: Merge drm_drv and drm_accel debugfs patches (K
On 7/4/2025 1:55 AM, Sunil Khatri wrote:
add support to add a directory for each client-id
Nitpick. This is the start of a sentence, and therefore proper grammar
would have the first letter capitalized. So, "add support" should be
"Add support".
-Jeff
On 7/21/2025 3:17 AM, Tomeu Vizoso wrote:
This series adds a new driver for the NPU that Rockchip includes in its
newer SoCs, developed by them on the NVDLA base.
In its current form, it supports the specific NPU in the RK3588 SoC.
The userspace driver is part of Mesa and an initial draft can b
On 7/22/2025 4:04 AM, Jacek Lawrynowicz wrote:
Add Karol as a new intel_vpu maintainer.
Signed-off-by: Jacek Lawrynowicz
Reviewed-by: Jeff Hugo
On 7/21/2025 4:08 PM, Carl Vanderlip wrote:
Qualcomm is changing open source email address policy.
LKML and other busy mailing lists use the oss.qualcomm.com domain.
Signed-off-by: Carl Vanderlip
Reviewed-by: Jeff Hugo
On 7/21/2025 9:24 AM, Heiko Stübner wrote:
Hi Jeff,
Am Montag, 21. Juli 2025, 16:55:01 Mitteleuropäische Sommerzeit schrieb Jeff
Hugo:
On 7/21/2025 3:17 AM, Tomeu Vizoso wrote:
This series adds a new driver for the NPU that Rockchip includes in its
newer SoCs, developed by them on the NVDLA
On 7/21/2025 4:08 PM, Carl Vanderlip wrote:
Qualcomm is changing open source email address policy.
LKML and other busy mailing lists use the oss.qualcomm.com domain.
Signed-off-by: Carl Vanderlip
Applied to drm-misc-next
-Jeff
On 7/21/2025 3:17 AM, Tomeu Vizoso wrote:
This series adds a new driver for the NPU that Rockchip includes in its
newer SoCs, developed by them on the NVDLA base.
In its current form, it supports the specific NPU in the RK3588 SoC.
The userspace driver is part of Mesa and an initial draft can b
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