On 5/20/2025 4:27 AM, Tomeu Vizoso wrote:
The NPU cores have their own access to the memory bus, and this isn't
cache coherent with the CPUs.
Add IOCTLs so userspace can mark when the caches need to be flushed, and
also when a writer job needs to be waited for before the buffer can be
accessed from the CPU.
Initially based on the same IOCTLs from the Etnaviv driver.
v2:
- Don't break UABI by reordering the IOCTL IDs (Jeff Hugo)
v3:
- Check that padding fields in IOCTLs are zero (Jeff Hugo)
Signed-off-by: Tomeu Vizoso <to...@tomeuvizoso.net>
Assuming what Lucas pointed out is addressed,
Reviewed-by: Jeff Hugo <jeff.h...@oss.qualcomm.com>
