On Thu Jun 12, 2025 at 11:49 PM JST, Benno Lossin wrote:
> On Thu Jun 12, 2025 at 3:27 PM CEST, Alexandre Courbot wrote:
>> On Thu Jun 12, 2025 at 10:17 PM JST, Alexandre Courbot wrote:
>>> On Wed Jun 4, 2025 at 4:18 PM JST, Benno Lossin wrote:
On Wed Jun 4, 2025 at 2:05 AM CEST, Alexandre Cou
Initialize writeback connector initialising the virtual encoder
and intel connector. We also allocate memory for drm_writeback_connector
but not the drm_connector within it due to a constraint
we need all connectors to be an intel_connector.
The writeback_format arrays is used to tell the user whic
Am Donnerstag, dem 12.06.2025 um 15:31 -0700 schrieb Doug Anderson:
> Hi,
>
> On Thu, Jun 12, 2025 at 10:52 AM Doug Anderson wrote:
> >
> > Hi,
> >
> > On Thu, Jun 12, 2025 at 12:35 AM Jayesh Choudhary
> > wrote:
> > >
> > > > > If refclk is described in devicetree node, then I see that
> >
On 11/06/2025 14:32, Bartosz Golaszewski wrote:
> On Wed, Jun 11, 2025 at 2:01 PM Michal Wilczynski
> wrote:
>>
>>
>>
>> On 6/5/25 10:10, Bartosz Golaszewski wrote:
>>> On Thu, Jun 5, 2025 at 9:47 AM Michal Wilczynski
>>> wrote:
On 6/4/25 14:07, Krzysztof Kozlowski wrote:
On 11/06/2025 14:01, Michal Wilczynski wrote:
>
> However, this leads me back to a fundamental issue with the
> consumer side implementation in the generic pvr_device.c driver. The
> current fallback code is:
>
> /*
> * If the error is -EPROBE_DEFER, it's because the
> * optional sequencer prov
Hi Prabhakar,
> -Original Message-
> From: Prabhakar
> Sent: 30 May 2025 18:19
.castro...@renesas.com>; Prabhakar Mahadev Lad lad...@bp.renesas.com>
> Subject: [PATCH v6 1/4] clk: renesas: rzv2h-cpg: Add support for DSI clocks
>
> From: Lad Prabhakar
>
> Add support for PLLDSI and PLL
Add writeback registers to its own file.
Signed-off-by: Suraj Kandpal
diff --git a/drivers/gpu/drm/i915/display/intel_writeback_reg.h
b/drivers/gpu/drm/i915/display/intel_writeback_reg.h
new file mode 100644
index ..dd872b6f8103
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel
This series is for review comments only and is not tested.
This series added a helper to be able to initialise writeback connector
in a way where drivers can send their own connector and encoder.
Signed-off-by: Suraj Kandpal
Suraj Kandpal (4):
drm/writeback: Add function that takes preallocate
Write a function that takes a preallocated drm_connector instead of
using the one allocated inside the drm writeback connector init
function.
Signed-off-by: Suraj Kandpal
diff --git a/drivers/gpu/drm/drm_writeback.c b/drivers/gpu/drm/drm_writeback.c
index edbeab88ff2b..0d287ab9bded 100644
--- a/
Add some preliminary definitions like, output type and transcoder
related to the writeback functionality.
Signed-off-by: Suraj Kandpal
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index 3b54a62c290a..ae474cbeb791 100644
--- a/drivers/g
Hi Prabhakar,
> -Original Message-
> From: Prabhakar
> Sent: 30 May 2025 18:19
> Subject: [PATCH v6 4/4] drm: renesas: rz-du: mipi_dsi: Add support for
> RZ/V2H(P) SoC
>
> From: Lad Prabhakar
>
> Add DSI support for Renesas RZ/V2H(P) SoC.
>
> Co-developed-by: Fabrizio Castro
> Signe
Hi,
On Tue, Jun 10, 2025 at 06:42:04PM +0300, Imre Deak wrote:
> Hi Maxim, Thomas, Maarten,
>
> could you please ack merging this patchset via drm-intel?
any objection to merge the patchset via drm-intel? If not, could
someone ack it?
Patches 1-4 could be also merged to drm-misc-next instead, b
On Thu Jun 12, 2025 at 10:17 PM JST, Alexandre Courbot wrote:
> On Wed Jun 4, 2025 at 4:18 PM JST, Benno Lossin wrote:
>> On Wed Jun 4, 2025 at 2:05 AM CEST, Alexandre Courbot wrote:
>>> On Wed Jun 4, 2025 at 8:02 AM JST, Benno Lossin wrote:
On Mon Jun 2, 2025 at 3:09 PM CEST, Alexandre Courbo
On 12-06-2025 17:24, Usyskin, Alexander wrote:
Subject: Re: [PATCH v2 05/10] drm/xe/xe_late_bind_fw: Load late binding
firmware
On 6/6/2025 10:57 AM, Badal Nilawar wrote:
Load late binding firmware
v2:
- s/EAGAIN/EBUSY/
- Flush worker in suspend and driver unload (Daniele)
Signed-of
On 6/6/2025 6:30 PM, Jeff Hugo wrote:
On 6/5/2025 10:20 AM, Maciej Falkowski wrote:
From: Andrzej Kacprowski
Introduces a new parameter to the DRM_IVPU_CMDQ_CREATE ioctl,
Introduce
Ack, thanks.
enabling turbo mode for jobs submitted via the command queue.
Turbo mode allows jobs to run a
On 11-06-2025 05:47, Daniele Ceraolo Spurio wrote:
On 6/6/2025 10:57 AM, Badal Nilawar wrote:
Load late binding firmware
v2:
- s/EAGAIN/EBUSY/
- Flush worker in suspend and driver unload (Daniele)
Signed-off-by: Badal Nilawar
---
drivers/gpu/drm/xe/xe_late_bind_fw.c | 121
Hi
Am 06.06.25 um 09:41 schrieb Maxime Ripard:
On Wed, Jun 04, 2025 at 05:45:42PM +0200, Thomas Zimmermann wrote:
Export additional helpers from the format-helper library and open-code
drm_fb_blit() in tests. Prepares for the removal of drm_fb_blit(). Only
sysfb drivers use drm_fb_blit(). The f
Quoting Jani Nikula (2025-06-12 09:46:17-03:00)
>The drm panel funcs should be static, fix it.
>
>Fixes: 3fdd5bfbd638 ("drm/i915/panel: register drm_panel and call
>prepare/unprepare for ICL+ DSI")
>Signed-off-by: Jani Nikula
Reviewed-by: Gustavo Sousa
>---
> drivers/gpu/drm/i915/display/intel
On 6/12/2025 7:31 AM, Falkowski, Maciej wrote:
On 6/6/2025 6:30 PM, Jeff Hugo wrote:
On 6/5/2025 10:20 AM, Maciej Falkowski wrote:
From: Andrzej Kacprowski
Introduces a new parameter to the DRM_IVPU_CMDQ_CREATE ioctl,
Introduce
Ack, thanks.
enabling turbo mode for jobs submitted via th
On 11/06/2025 22:21, Danilo Krummrich wrote:
On Tue, 2025-06-03 at 13:27 +0100, Tvrtko Ursulin wrote:
On 03/06/2025 10:31, Philipp Stanner wrote:
What I am not that ecstatic about is only getting the Suggested-by
credit in 1/6. Given it is basically my patch with some cosmetic
changes
like the
Hi
Am 12.06.25 um 15:29 schrieb Imre Deak:
Hi,
On Tue, Jun 10, 2025 at 06:42:04PM +0300, Imre Deak wrote:
Hi Maxim, Thomas, Maarten,
could you please ack merging this patchset via drm-intel?
any objection to merge the patchset via drm-intel? If not, could
someone ack it?
Sorry for missing
We will use this error in the nova-core driver.
Reviewed-by: Benno Lossin
Signed-off-by: Alexandre Courbot
---
rust/kernel/error.rs | 1 +
1 file changed, 1 insertion(+)
diff --git a/rust/kernel/error.rs b/rust/kernel/error.rs
index
3dee3139fcd4379b94748c0ba1965f4e1865b633..083c7b068cf4e18510
Hi everyone,
The feedback on v4 has been (hopefully) addressed. I guess the main
remaining unknown is the direction of the `num` module ; for this
iteration, following the received feedback I have eschewed the extension
trait and implemented the alignment functions as methods of the new
`PowerOfTw
With all the required pieces in place, load FWSEC-FRTS onto the GSP
falcon, run it, and check that it successfully carved out the WPR2
region out of framebuffer memory.
Reviewed-by: Lyude Paul
Signed-off-by: Alexandre Courbot
---
drivers/gpu/nova-core/falcon.rs | 3 --
drivers/gpu/nova-core/gp
FWSEC-FRTS is run with the desired address of the FRTS region as
parameter, which we need to compute depending on some hardware
parameters.
Do this in a `FbLayout` structure, that will be later extended to
describe more memory regions used to boot the GSP.
Reviewed-by: Lyude Paul
Signed-off-by:
From: Joel Fernandes
Using the support for navigating the VBIOS, add support to extract vBIOS
ucode data required for GSP to boot. The main data extracted from the
vBIOS is the FWSEC-FRTS firmware which runs on the GSP processor. This
firmware runs in high secure mode, and sets up the WPR2 (Write
Since we will need to allocate lots of distinct memory chunks to be
shared between GPU and CPU, introduce a type dedicated to that. It is a
light wrapper around CoherentAllocation.
Reviewed-by: Lyude Paul
Signed-off-by: Alexandre Courbot
---
drivers/gpu/nova-core/dma.rs | 61 +
FWSEC-FRTS is the first firmware we need to run on the GSP falcon in
order to initiate the GSP boot process. Introduce the structure that
describes it.
Reviewed-by: Lyude Paul
Signed-off-by: Alexandre Courbot
---
drivers/gpu/nova-core/firmware.rs | 45 +++
1
Some of the firmwares need to be patched at load-time with a signature.
Add a couple of types and traits that sub-modules can use to implement
this behavior, while ensuring that the correct kind of signature is
applied to the firmware.
Reviewed-by: Lyude Paul
Signed-off-by: Alexandre Courbot
---
Only sysfb drivers use drm_fb_build_fourcc_list(). Move the function
to sysfb helpers and rename it accordingly. Update drivers and tests.
v2:
- select DRM_SYSFB_HELPER (kernel test robot)
Signed-off-by: Thomas Zimmermann
Acked-by: Maxime Ripard
Acked-by: Javier Martinez Canillas
---
drivers/
Export additional helpers from the format-helper library and open-code
drm_fb_blit() in tests. Prepares for the removal of drm_fb_blit(). Only
sysfb drivers use drm_fb_blit(). The function will soon be removed from
format helpers and be refactored within sysfb helpers.
Signed-off-by: Thomas Zimmer
Only sysfb drivers use drm_fb_build_fourcc_list(). The helper will
be moved from format helpers to sysfb helpers. Moving the related
tests to their own test suite.
v2:
- rename filename to match tested code (Maxime)
Signed-off-by: Thomas Zimmermann
Acked-by: Maxime Ripard
---
drivers/gpu/drm/t
The helpers drm_fb_blit() and drm_fb_build_fourcc_list() will be
integrated into sysfb helpers. Update the DRM format-helper tests
accordingly in patches 1 and 2.
The change to drm_fb_build_fourcc_list() is simple enough that we
can apply it here in patch 3.
v2:
- fix test filename (Maxime)
- fix
From: Joel Fernandes
Add support for navigating the VBIOS images required for extracting
ucode data for GSP to boot. Later patches will build on this.
Debug log messages will show the BIOS images:
[102141.013287] NovaCore: Found BIOS image at offset 0x0, size: 0xfe00, type:
PciAt
[102141.08069
Booting the GSP on Ampere requires an intricate dance between the GSP
and SEC2 falcons, where the GSP starts by running the FWSEC firmware to
create the WPR2 region , and then SEC2 loads the actual RISC-V firmware
into the GSP.
Add the common Falcon code and HAL for Ampere GPUs, and instantiate th
From: Joel Fernandes
The PMU table in the FWSEC image has to be located to locate the start
of the Falcon ucode in the same or another FWSEC image. Add support for
the same.
Signed-off-by: Joel Fernandes
Signed-off-by: Alexandre Courbot
---
drivers/gpu/nova-core/vbios.rs | 179 +++
Reserve a page of system memory so sysmembar can perform a read on it if
a system write occurred since the last flush. Do this early as it can be
required to e.g. reset the GPU falcons.
Chipsets capabilities differ in that respect, so this commit also
introduces the FB HAL.
Signed-off-by: Alexand
Some registers (notably scratch registers) don't have a definitive
purpose, but need to be interpreted differently depending on context.
Expand the register!() macro to support a syntax indicating that a
register type should be at the same offset as another one, but under a
different name, and wit
Introduce the `num` module, featuring the `PowerOfTwo` unsigned wrapper
that guarantees (at build-time or runtime) that a value is a power of
two.
Such a property is often useful to maintain. In the context of the
kernel, powers of two are often used to align addresses or sizes up and
down, or to
Add an equivalent to the `fls` (Find Last Set bit) C function to Rust
unsigned types.
It is to be first used by the nova-core driver.
Signed-off-by: Alexandre Courbot
---
rust/kernel/num.rs | 31 +++
1 file changed, 31 insertions(+)
diff --git a/rust/kernel/num.rs b
This macro is pretty complex, and most rules are just helper, so add a
delimiter to indicate when users only interested in using it can stop
reading.
Reviewed-by: Lyude Paul
Signed-off-by: Alexandre Courbot
---
drivers/gpu/nova-core/regs/macros.rs | 2 ++
1 file changed, 2 insertions(+)
diff -
While programming the hardware, we frequently need to busy-wait until
a condition (like a given bit of a register to switch value) happens.
Add a basic `wait_on` helper function to wait on such conditions
expressed as a closure, with a timeout argument.
This is temporary as we will switch to `rea
These properties are very useful to have (and to be used by nova-core)
and should be accessible.
Signed-off-by: Alexandre Courbot
---
rust/kernel/dma.rs | 32 ++--
1 file changed, 26 insertions(+), 6 deletions(-)
diff --git a/rust/kernel/dma.rs b/rust/kernel/dma.rs
i
Upon reset, the GPU executes the GFW (GPU Firmware) in order to
initialize its base parameters such as clocks. The driver must ensure
that this step is completed before using the hardware.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/nova-core/gfw.rs | 39 ++
The Turing+ register address space spans over that range, so increase it
as future patches will access more registers.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/nova-core/driver.rs | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/nova-core/driver.rs b/dr
Although we want to access registers using the provided methods, it is
sometimes needed to use their raw offset, for instance when working with
a register array.
Expose the offset of each register using a type constant to avoid
resorting to hardcoded values.
Reviewed-by: Lyude Paul
Signed-off-by
On 06/10, Markus Elfring wrote:
> From: Markus Elfring
> Date: Tue, 10 Jun 2025 07:42:40 +0200
>
> The label “cleanup” was used to jump to another pointer check despite of
> the detail in the implementation of the function
> “dm_validate_stream_and_context”
> that it was determined already that
Fix the paths that were not absolute to prevent a potential local module
from being picked up.
Reviewed-by: Lyude Paul
Signed-off-by: Alexandre Courbot
---
drivers/gpu/nova-core/regs/macros.rs | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/nova-core
> Subject: Re: [PATCH v6 01/11] mtd: core: always create master device
>
> Hello,
>
> On 11/06/2025 at 10:52:36 GMT, "Usyskin, Alexander"
> wrote:
>
> >> Subject: Re: [PATCH v6 01/11] mtd: core: always create master device
> >>
> >> - Ursprüngliche Mail -
> >> > Von: "Miquel Raynal"
>
> -Original Message-
> From: Murthy, Arun R
> Sent: Thursday, June 12, 2025 11:45 AM
> To: Kandpal, Suraj ;
> nouv...@lists.freedesktop.org; dri-devel@lists.freedesktop.org; intel-
> x...@lists.freedesktop.org; intel-...@lists.freedesktop.org
> Cc: Nautiyal, Ankit K
> Subject: RE: [PAT
Hi,
On Fri, May 23, 2025 at 08:40:41AM +0200, Alexander Stein wrote:
> When checking for unsupported expect an error is printed every time.
> This spams the log for platforms where this is expected, e.g. ls1028a
> having a Vivante (etnaviv) GPU and Mali display processor.
>
> Signed-off-by: Alexa
On 6/12/2025 1:35 PM, Dmitry Baryshkov wrote:
> On Thu, Jun 12, 2025 at 10:50:10AM +0530, Ekansh Gupta wrote:
>>
>> On 5/22/2025 5:43 PM, Dmitry Baryshkov wrote:
>>> On Thu, 22 May 2025 at 08:01, Ekansh Gupta
>>> wrote:
On 5/19/2025 7:04 PM, Dmitry Baryshkov wrote:
> On Mon, May 1
> -Original Message-
> From: Murthy, Arun R
> Sent: Thursday, June 12, 2025 4:43 PM
> To: Kandpal, Suraj ;
> nouv...@lists.freedesktop.org; dri-devel@lists.freedesktop.org; intel-
> x...@lists.freedesktop.org; intel-...@lists.freedesktop.org
> Cc: Nautiyal, Ankit K
> Subject: RE: [PATC
On 6/12/25 12:58, Tvrtko Ursulin wrote:
>
> On 12/06/2025 08:21, Christian König wrote:
>> On 6/11/25 17:29, Tvrtko Ursulin wrote:
>>>
>>> On 11/06/2025 15:21, Christian König wrote:
On 6/11/25 16:00, Tvrtko Ursulin wrote:
> Running the Cyberpunk 2077 benchmark we can observe that the loo
> Subject: Re: [PATCH v2 05/10] drm/xe/xe_late_bind_fw: Load late binding
> firmware
>
>
>
> On 6/6/2025 10:57 AM, Badal Nilawar wrote:
> > Load late binding firmware
> >
> > v2:
> > - s/EAGAIN/EBUSY/
> > - Flush worker in suspend and driver unload (Daniele)
> >
> > Signed-off-by: Badal Nila
Hi Jayesh,
> + /*
> + * After EN is deasserted and an external clock is detected,
> the bridge
> + * will sample GPIO3:1 to determine its frequency. The
> driver will
> + * overwrite this setting. But this is racy. Thus we have to
>
On 6/11/25 13:15, Akhil P Oommen wrote:
Add support for X1-45 GPU found in X1P41200 chipset (8 cpu core
version). X1-45 is a smaller version of X1-85 with lower core count and
smaller memories. From UMD perspective, this is similar to "FD735"
present in Mesa.
Hi Akhil,
when loading the driver
John Keeping writes:
Hello John,
> The number of columns relates to the width, not the height. Use the
> correct variable.
>
> Signed-off-by: John Keeping
> ---
Pushed to drm-misc (drm-misc-fixes). Thanks!
--
Best regards,
Javier Martinez Canillas
Core Platforms
Red Hat
On Wednesday, 11 June 2025 23:47:46 Central European Summer Time Cristian
Ciocaltea wrote:
> Since commit c871a311edf0 ("phy: rockchip: samsung-hdptx: Setup TMDS
> char rate via phy_configure_opts_hdmi"), the workaround of passing the
> PHY rate from DW HDMI QP bridge driver via phy_set_bus_width(
On 03/06/2025 10:31, Philipp Stanner wrote:
Since its inception, the GPU scheduler can leak memory if the driver
calls drm_sched_fini() while there are still jobs in flight.
The simplest way to solve this in a backwards compatible manner is by
adding a new callback, drm_sched_backend_ops.cance
The FWSEC firmware needs to be extracted from the VBIOS and patched with
the desired command, as well as the right signature. Do this so we are
ready to load and run this firmware into the GSP falcon and create the
FRTS region.
[joelagn...@nvidia.com: give better names to FalconAppifHdrV1's fields
On Thu, 2025-06-12 at 15:17 +0100, Tvrtko Ursulin wrote:
>
> On 03/06/2025 10:31, Philipp Stanner wrote:
> > Since its inception, the GPU scheduler can leak memory if the
> > driver
> > calls drm_sched_fini() while there are still jobs in flight.
> >
> > The simplest way to solve this in a backwa
Hi,
Here's the first drm-misc-next PR for 6.17.
Maxime
drm-misc-next-2025-06-12:
drm-misc-next for 6.17:
UAPI Changes:
Cross-subsystem Changes:
Core Changes:
- atomic-helpers: Tune the enable / disable sequence
- bridge: Add destroy hook
- color management: Add helpers for hardware gamma L
On Thu, May 29, 2025 at 04:32:04PM +1000, Alistair Popple wrote:
> Previously dax pages were skipped by the pagewalk code as pud_special() or
> vm_normal_page{_pmd}() would be false for DAX pages. Now that dax pages are
> refcounted normally that is no longer the case, so add explicit checks to
> s
nova-core will need to use SZ_1M, so make the remaining constants
available.
Reviewed-by: Boqun Feng
Signed-off-by: Alexandre Courbot
---
rust/kernel/sizes.rs | 24
1 file changed, 24 insertions(+)
diff --git a/rust/kernel/sizes.rs b/rust/kernel/sizes.rs
index
834c343
On Tue, Jun 03, 2025 at 10:49:32AM +0100, Ashley Smith wrote:
> The timeout logic provided by drm_sched leads to races when we try
> to suspend it while the drm_sched workqueue queues more jobs. Let's
> overhaul the timeout handling in panthor to have our own delayed work
> that's resumed/suspended
Hi Dave, Simona
Two fixes for 6.16-rc2.
Thanks,
Thomas
drm-xe-fixes-2025-06-12:
Driver Changes:
- Fix regression disallowing 64K SVM migration (Maarten)
- Use a bounce buffer for WA BB (Lucas)
The following changes since commit 19272b37aa4f83ca52bdf9c16d5d81bdd1354494:
Linux 6.16-rc1 (2025-0
On Thu, Jun 12, 2025 at 08:56:18PM +0200, Nicolas Frattaroli wrote:
> The era of hand-rolled HIWORD_UPDATE macros is over, at least for those
> drivers that use constant masks.
>
> The Rockchip PCI driver, like many other Rockchip drivers, has its very
> own definition of HIWORD_UPDATE.
>
> Remov
On Thu, Jun 12, 2025 at 08:56:19PM +0200, Nicolas Frattaroli wrote:
> The era of hand-rolled HIWORD_UPDATE macros is over.
>
> Like many other Rockchip drivers, pcie-dw-rockchip brings with it its
> very own flavour of HIWORD_UPDATE. It's occasionally used without a
> constant mask, which complica
On Thu, Jun 12, 2025 at 08:56:17PM +0200, Nicolas Frattaroli wrote:
> The era of hand-rolled HIWORD_UPDATE macros is over, at least for those
> drivers that use constant masks.
>
> Like many other Rockchip drivers, dwmac-rk has its own HIWORD_UPDATE
> macro. Its semantics allow us to redefine it a
On Thu, 12 Jun 2025 20:56:03 +0200 Nicolas Frattaroli wrote:
> Hardware of various vendors, but very notably Rockchip, often uses
> 32-bit registers where the upper 16-bit half of the register is a
> write-enable mask for the lower half.
Please limit the spread of this weirdness to a rockchip or "
On Thursday, 12 June 2025 21:44:15 Central European Summer Time Jakub Kicinski
wrote:
> On Thu, 12 Jun 2025 20:56:03 +0200 Nicolas Frattaroli wrote:
> > Hardware of various vendors, but very notably Rockchip, often uses
> > 32-bit registers where the upper 16-bit half of the register is a
> > writ
On Thu, Jun 12, 2025 at 02:37:28PM -0500, Bjorn Helgaas wrote:
> On Thu, Jun 12, 2025 at 08:56:18PM +0200, Nicolas Frattaroli wrote:
> > The era of hand-rolled HIWORD_UPDATE macros is over, at least for those
> > drivers that use constant masks.
> >
> > The Rockchip PCI driver, like many other Roc
On Thu, 12 Jun 2025 16:10:37 -0400 Yury Norov wrote:
> I don't think that that having HWORD_UPDATE() in bitfield.h is a wrong
> thing. Jakub, if you do, we can just create a new header for it.
Yes, I'd prefer to contain it. This looks very much like a CSR tooling
convention of Rockchip's ASIC deve
Hi,
On Thu, Jun 12, 2025 at 10:52 AM Doug Anderson wrote:
>
> Hi,
>
> On Thu, Jun 12, 2025 at 12:35 AM Jayesh Choudhary wrote:
> >
> > >> If refclk is described in devicetree node, then I see that
> > >> the driver modifies it in every resume call based solely on the
> > >> clock value in dts.
>
On Thu, Jun 12, 2025 at 03:15:31PM +0100, Lorenzo Stoakes wrote:
> On Thu, May 29, 2025 at 04:32:04PM +1000, Alistair Popple wrote:
> > Previously dax pages were skipped by the pagewalk code as pud_special() or
> > vm_normal_page{_pmd}() would be false for DAX pages. Now that dax pages are
> > refc
On Thu, Jun 12, 2025 at 09:00:34AM +0200, Christian König wrote:
> On 6/11/25 17:11, Danilo Krummrich wrote:
> Mhm, reiterating our internal discussion on the mailing list.
>
> I think it would be nicer if we could use negative values for the kernel
> submissions and positive f
On Thu, Jun 12, 2025 at 05:10:23PM +, Kaustabh Chakraborty wrote:
> On 2025-06-12 15:30, Conor Dooley wrote:
> > On Thu, Jun 12, 2025 at 08:22:41PM +0530, Kaustabh Chakraborty wrote:
> >> Samsung S6E8AA5X01 is an AMOLED MIPI DSI panel controller. Document the
> >> compatible and devicetree prop
On Tue, Jun 10, 2025 at 05:42:26PM +0100, Tvrtko Ursulin wrote:
Xe can free some of the data pointed to by the dma-fences it exports. Most
notably the timeline name can get freed if userspace closes the associated
submit queue. At the same time the fence could have been exported to a
third party
On Thu, Jun 12, 2025 at 03:54:51PM +0200, Thomas Zimmermann wrote:
> Hi
>
> Am 12.06.25 um 15:29 schrieb Imre Deak:
> > Hi,
> >
> > On Tue, Jun 10, 2025 at 06:42:04PM +0300, Imre Deak wrote:
> > > Hi Maxim, Thomas, Maarten,
> > >
> > > could you please ack merging this patchset via drm-intel?
>
Hi,
On Thu, Jun 12, 2025 at 12:35 AM Jayesh Choudhary wrote:
>
> >> If refclk is described in devicetree node, then I see that
> >> the driver modifies it in every resume call based solely on the
> >> clock value in dts.
> >
> > Exactly. But that is racy with what the chip itself is doing. I.e.
>
On Thu, Jun 12, 2025 at 05:46:52PM +0100, Tvrtko Ursulin wrote:
On 12/06/2025 06:40, Lucas De Marchi wrote:
On Wed, Jun 11, 2025 at 03:51:24PM -0700, Juston Li wrote:
Add TRACE_GPU_MEM tracepoints for tracking global and per-process GPU
memory usage.
These are required by VSR on Android 12+ f
This series was spawned by [1], where I was asked to move every instance
of HIWORD_UPDATE et al that I could find to a common macro in the same
series that I am introducing said common macro.
The first patch of the series introduces the two new macros in
bitfield.h, called HWORD_UPDATE and HWORD_U
The era of hand-rolled HIWORD_UPDATE macros is over, at least for those
drivers that use constant masks.
Replace the UPDATE macro with bitfield.h's FIELD_PREP, to give us
additional error checking.
Also, replace the HIWORD_UPDATE macro at the same time with bitfield.h's
new HWORD_UPDATE macro, wh
Hardware of various vendors, but very notably Rockchip, often uses
32-bit registers where the upper 16-bit half of the register is a
write-enable mask for the lower half.
This type of hardware setup allows for more granular concurrent register
write access.
Over the years, many drivers have hand-
The era of hand-rolled HIWORD_UPDATE macros is over, at least for those
drivers that use constant masks.
Switch the rockchip grf driver to the HWORD_UPDATE_CONST macro, which
brings with it more error checking while still being able to be used in
initializers.
All HIWORD_UPDATE instances and its
The era of hand-rolled HIWORD_UPDATE macros is over, at least for those
drivers that use constant masks.
Switch to the new HWORD_UPDATE macro in bitfield.h, which has error
checking. Instead of redefining the driver's HIWORD_UPDATE macro in this
case, replace the two only instances of it with the
The era of hand-rolled HIWORD_UPDATE macros is over, at least for those
drivers that use constant masks.
The Rockchip PCI driver, like many other Rockchip drivers, has its very
own definition of HIWORD_UPDATE.
Remove it, and replace its usage with either HWORD_UPDATE, or two new
header local macr
The era of hand-rolled HIWORD_UPDATE macros is over, at least for those
drivers that use constant masks.
Remove this driver's very own HIWORD_UPDATE macro, and replace all
instances of it with equivalent instantiations of HWORD_UPDATE or
HWORD_UPDATE_CONST, depending on whether it's in an initiali
The era of hand-rolled HIWORD_UPDATE macros is over, at least for those
drivers that use constant masks.
Like many other Rockchip drivers, dwmac-rk has its own HIWORD_UPDATE
macro. Its semantics allow us to redefine it as a wrapper to the shared
bitfield.h HWORD_UPDATE macros though.
Replace the
The era of hand-rolled HIWORD_UPDATE macros is over, at least for those
drivers that use constant masks.
Replace the implementation of this driver's HIWORD_UPDATE macro with an
instance of HWORD_UPDATE_CONST. The const variant is chosen here because
some of the header defines are then used in init
The era of hand-rolled HIWORD_UPDATE macros is over, at least for those
drivers that use constant masks.
The Rockchip PCIe PHY driver, used on the RK3399, has its own definition
of HIWORD_UPDATE.
Remove it, and replace instances of it with bitfield.h's HWORD_UPDATE.
To achieve this, some mask def
The era of hand-rolled HIWORD_UPDATE macros is over, at least for those
drivers that use constant masks.
Remove this driver's HIWORD_UPDATE macro, and replace instances of it
with either HWORD_UPDATE or HWORD_UPDATE_CONST, depending on whether
they're in an initializer. This gives us better error
The era of hand-rolled HIWORD_UPDATE macros is over, at least for those
drivers that use constant masks.
Remove VOP2's HIWORD_UPDATE macro from the vop2 header file, and replace
all instances in rockchip_vop2_reg.c (the only user of this particular
HIWORD_UPDATE definition) with equivalent HWORD_U
The era of hand-rolled HIWORD_UPDATE macros is over, at least for those
drivers that use constant masks.
Remove rockchip_lvds.h's own HIWORD_UPDATE macro, and replace all
instances of it with bitfield.h's HWORD_UPDATE macro, which gives us
more error checking.
For the slightly-less-trivial case o
The era of hand-rolled HIWORD_UPDATE macros is over, at least for those
drivers that use constant masks.
Replace the implementation of the rockchip eMMC PHY driver's
HIWORD_UPDATE macro with bitfield.h's HWORD_UPDATE. This makes the
change more easily reviewable.
Signed-off-by: Nicolas Frattaroli
The era of hand-rolled HIWORD_UPDATE macros is over, at least for those
drivers that use constant masks.
Remove this driver's HIWORD_UPDATE macro, and replace all instances of
it with (hopefully) equivalent HWORD_UPDATE instances. To do this, a few
of the defines are being adjusted, as HWORD_UPDAT
The era of hand-rolled HIWORD_UPDATE macros is over, at least for those
drivers that use constant masks.
Replace this driver's HIWORD_UPDATE with the HWORD_UPDATE from
bitfield.h. While at it, disambiguate the write GRF write to SOC_CON7 by
splitting the definition into the individual bitflags. Th
The era of hand-rolled HIWORD_UPDATE macros is over, at least for those
drivers that use constant masks.
The inno-hdmi driver's own HIWORD_UPDATE macro is instantiated only
twice. Remove it, and replace its uses with HWORD_UPDATE. Since
HWORD_UPDATE shifts the value for us, we replace using the ma
The era of hand-rolled HIWORD_UPDATE macros is over, at least for those
drivers that use constant masks.
phy-rockchip-samsung-dcphy is actually an exemplary example, where the
similarities to FIELD_PREP were spotted and the driver local macro has
the same semantics as the new HWORD_UPDATE bitfield
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