On Sun, 27 Apr 2025, Wayne Lin wrote:
> + /*
> + * When I2C write firstly get defer and get ack after
> + * retries by wirte_status_update, we have to return
> + * all data bytes get transferred instead of 0.
> +
On 5/7/25 19:36, T.J. Mercier wrote:
> On Wed, May 7, 2025 at 1:15 AM Christian König
> wrote:
>>
>> On 5/7/25 02:10, T.J. Mercier wrote:
>>> The dmabuf iterator traverses the list of all DMA buffers.
>>>
>>> DMA buffers are refcounted through their associated struct file. A
>>> reference is take
Let the user know what went wrong in drm_gem_fb_afbc_init
failure paths.
Signed-off-by: Andy Yan
---
drivers/gpu/drm/drm_gem_framebuffer_helper.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_gem_framebuffer_helper.c
b/drivers/gpu/drm/drm_gem_frame
Hi,
sorry for the late review. I've been away for a few days.
Am 12.04.25 um 09:00 schrieb Thierry Reding:
From: Thierry Reding
Recent generations of Tegra have moved the display components outside of
host1x, leading to a device that has no CRTCs attached and hence doesn't
support any of the
On Wed, May 07, 2025 at 04:10:07PM +, Biju Das wrote:
> Hi Thierry,
>
> > -Original Message-
> > From: Thierry Reding
> > Sent: 07 May 2025 17:00
> > To: Biju Das
> > Subject: Re: [PATCH] drm/tegra: rgb: Fix the unbound reference count
> >
> > On Wed, Feb 05, 2025 at 11:21:35AM +000
On 5/8/25 11:13, Philipp Stanner wrote:
> On Mon, 2025-04-28 at 16:45 +0200, Christian König wrote:
>> On 4/24/25 15:02, Philipp Stanner wrote:
>>> In nouveau_fence_done(), a fence is checked for being signaled by
>>> manually evaluating the base fence's bits. This can be done in a
>>> canonical ma
On 08/05/2025 07:29, Matthew Brost wrote:
On Fri, May 02, 2025 at 01:32:33PM +0100, Tvrtko Ursulin wrote:
Hi all,
This is another respin of this old work^1 but this version is a total rewrite
and completely changes how the control is done.
This time round the work builds upon the "fair" DRM
On Mon, 2025-04-28 at 16:45 +0200, Christian König wrote:
> On 4/24/25 15:02, Philipp Stanner wrote:
> > In nouveau_fence_done(), a fence is checked for being signaled by
> > manually evaluating the base fence's bits. This can be done in a
> > canonical manner through dma_fence_is_signaled().
> >
Hi Andy,
On Thu, 8 May 2025 at 11:49, Andy Yan wrote:
> Let the user know what went wrong in drm_gem_fb_afbc_init
> failure paths.
Thanks for this, and thanks also for using drm_dbg_kms() to make sure
that userspace can't flood the log with errors.
Reviewed-by: Daniel Stone
Cheers,
Daniel
Hi
Am 07.05.25 um 11:47 schrieb oushixiong1...@163.com:
From: Shixiong Ou
[WHY]
1. Drivers using DRM_GEM_SHADOW_PLANE_HELPER_FUNCS and
DRM_GEM_SHMEM_DRIVER_OPS (e.g., udl, ast) do not require
sg_table import.
They only need dma_buf_vmap() to access the shared buffer's
kernel vi
On Tue, 2025-04-22 at 23:51 +0200, Javier Martinez Canillas wrote:
> Philipp Stanner writes:
>
> Hello Philipp,
>
> > cirrus enables its PCI device with pcim_enable_device(). This,
> > implicitly, switches the function pci_request_regions() into
> > managed
> > mode, where it becomes a devres fu
On Wed, 2025-04-23 at 14:06 +0200, Philipp Stanner wrote:
> vmgfx enables its PCI device with pcim_enable_device(). This,
> implicitly, switches the function pci_request_regions() into managed
> mode, where it becomes a devres function.
>
> The PCI subsystem wants to remove this hybrid nature from
On 07/05/2025 17:07, Adrián Larumbe wrote:
> This change is essentially a Panfrost port of commit a3707f53eb3f
> ("drm/panthor: show device-wide list of DRM GEM objects over DebugFS").
>
> The DebugFS file is almost the same as in Panthor, minus the GEM object
> usage flags, since Panfrost has no
Philipp Stanner writes:
Hello Philipp,
> On Tue, 2025-04-22 at 23:51 +0200, Javier Martinez Canillas wrote:
>> Philipp Stanner writes:
>>
>> Hello Philipp,
>>
>> > cirrus enables its PCI device with pcim_enable_device(). This,
>> > implicitly, switches the function pci_request_regions() into
On Tue, May 06, 2025 at 11:47:31PM +0800, Jun Nie wrote:
> Some display controller support flexible CRTC and DMA, such as the display
> controllers in snapdragon SoCs. CRTC can be implemented with several mixers
> in parallel, and plane fetching can be implemented with several DMA under
> umberala
On 5/6/25 01:38, li...@treblig.org wrote:
> From: "Dr. David Alan Gilbert"
>
> sync_file_debug_add() and sync_file_debug_remove() have been unused
> since 2016's
> commit d4cab38e153d ("staging/android: prepare sync_file for de-staging")
>
> Remove them.
>
> Since sync_file_debug_add was the on
On Thu, 2025-04-24 at 11:55 +0200, Philipp Stanner wrote:
> The unit tests so far took care manually of avoiding memory leaks
> that
> might have occurred when calling drm_sched_fini().
>
> The scheduler now takes care by itself of avoiding memory leaks if
> the
> driver provides the callback
> dr
From: hienhuynh
This patch is based on the commit 73eb5476df72 ("drm: rcar-du: Support
panels connected directly to the DPAD outputs").
The RZ DU driver assumes that a bridge is always connected to the DU
output. This is valid for the HDMI output, but the DPAD output can be
connected directly to
On Tue, 06 May 2025, Melissa Wen wrote:
> Original drm_edid_get_monitor_name encapsulates raw edid in drm_edid and
> then call get_monitor_name. AMD still stores the display name for
> debugging, but it is migrating to drm_edid, on the other hand,
> drm_dp_mst_topology and sil-sii8620 still use th
On Tue, 06 May 2025, Melissa Wen wrote:
> From: Rodrigo Siqueira
>
> As part of the effort of stopping using raw edid, this commit move the
> copy of the edid in DC to a dedicated function that will allow the usage
> of drm_edid in the next steps.
>
> Signed-off-by: Rodrigo Siqueira
> Co-develop
On Tue, 06 May 2025, Melissa Wen wrote:
> AMD driver has a function used to compare if two edid are the same; this
> is useful to some of the link detection algorithms implemented by
> amdgpu. Since the amdgpu function can be helpful for other drivers, this
^
Theres's a non-breaking spac
On Tue, 06 May 2025, Melissa Wen wrote:
> diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
> b/drivers/gpu/drm/amd/display/dc/dc.h
> index c93e074ea736..54f6ed33e373 100644
> --- a/drivers/gpu/drm/amd/display/dc/dc.h
> +++ b/drivers/gpu/drm/amd/display/dc/dc.h
> @@ -46,6 +46,8 @@
>
> #include
On Wed, 30 Apr 2025 at 14:17, Michal Wilczynski
wrote:
>
>
>
> On 4/25/25 10:50, Ulf Hansson wrote:
> > + Bartosz
> >
> > On Mon, 14 Apr 2025 at 20:53, Michal Wilczynski
> > wrote:
> >>
> >> Extend the TH1520 power domain driver to manage GPU related clocks and
> >> resets via generic PM domain s
By default, HPD was disabled on SN65DSI86 bridge. When the driver was
added (commit "a095f15c00e27"), the HPD_DISABLE bit was set in pre-enable
call which was moved to other function calls subsequently.
Later on, commit "c312b0df3b13" added detect utility for DP mode. But with
HPD_DISABLE bit set,
[Public]
> -Original Message-
> From: Jani Nikula
> Sent: Thursday, May 8, 2025 4:19 PM
> To: Lin, Wayne ; dri-devel@lists.freedesktop.org
> Cc: ville.syrj...@linux.intel.com; Limonciello, Mario
> ;
> Wentland, Harry ; Lin, Wayne
> ; sta...@vger.kernel.org
> Subject: Re: [PATCH] drm/dp:
On Thu, 08 May 2025, "Lin, Wayne" wrote:
> [Public]
>
>> -Original Message-
>> From: Jani Nikula
>> Sent: Thursday, May 8, 2025 4:19 PM
>> To: Lin, Wayne ; dri-devel@lists.freedesktop.org
>> Cc: ville.syrj...@linux.intel.com; Limonciello, Mario
>> ;
>> Wentland, Harry ; Lin, Wayne
>> ; s
Hi Dave, Simona,
A final pull request for drm-misc-next. It's been mostly fixes, adding some
panels, and not much new features,
so I feel sending a final drm-misc-next PR is a good idea before switching to
drm-misc-next-fixes,
especially since the previous one landed a bit early.
Cheers,
~Maart
On Thu, 08 May 2025 14:43:04 +0800, Chaoyi Chen wrote:
> From: Chaoyi Chen
>
> Convert cdn-dp-rockchip.txt to yaml.
>
> Tested with:
>
> 1. make ARCH=arm64 dt_binding_check
> DT_SCHEMA_FILES=Documentation/devicetree/bindings/display/rockchip/rockchip,cdn-dp.yaml
>
> 2. make ARCH=arm64 dtbs_
On 08/05/2025 08:43, Chaoyi Chen wrote:
> From: Chaoyi Chen
>
> Convert cdn-dp-rockchip.txt to yaml.
>
> Tested with:
>
> 1. make ARCH=arm64 dt_binding_check
> DT_SCHEMA_FILES=Documentation/devicetree/bindings/display/rockchip/rockchip,cdn-dp.yaml
>
> 2. make ARCH=arm64 dtbs_check
> DT_SCHEM
On Wed, May 07, 2025 at 03:19:19PM GMT, Chris Morgan wrote:
> From: Chris Morgan
>
> I've spoken with Ryan and he agreed to let me take over this series to
> get the display engine working on the Allwinner H616. I've taken his
> previous patch series for Display Engine 3.3 and combined it with th
On Wed, 2025-05-07 at 06:27 +, Khatri, Sunil wrote:
> [AMD Official Use Only - AMD Internal Distribution Only]
>
> Ping ?
Hello,
sry, I was out for a few days.
>
> Not picked yet while patches raised before this are merged.
>
> Regards
> Sunil Khatri
>
> -Original Message-
> From
Hi Philipp,
On 08/05/2025 12:03, Philipp Stanner wrote:
On Thu, 2025-04-24 at 11:55 +0200, Philipp Stanner wrote:
The unit tests so far took care manually of avoiding memory leaks
that
might have occurred when calling drm_sched_fini().
The scheduler now takes care by itself of avoiding memor
Hi Dave and Sima,
Here goes our likely last drm-intel-next PR towards 6.16.
Mostly with patches targeting the full display split.
Thanks,
Rodrigo.
drm-intel-next-2025-05-08:
Non-display related:
- Fix undefined reference to `intel_pxp_gsccs_is_ready_for_sessions'
Display related:
- More work t
Add bindings for the Novatek NT37801 or NT37810 AMOLED DSI panel.
Sources, like downstream DTS, schematics and hardware manuals, use two
model names (NT37801 and NT37810), so choose one and hope it is correct.
Reviewed-by: Linus Walleij
Signed-off-by: Krzysztof Kozlowski
---
.../bindings/displa
Changes in v2:
- Use devm_drm_panel_alloc (Neil)
- Add novatek_nt37801_switch_page (Linus)
- Add Rb tags
- Link to v1:
https://lore.kernel.org/r/20250505-sm8750-display-panel-v1-0-e5b539848...@linaro.org
Add driver for the Novatek NT37801 or NT37810 AMOLED DSI panel, used on
Qualcomm MTP8750 boar
On Thu, May 8, 2025 at 6:40 AM Philipp Stanner wrote:
>
> On Wed, 2025-04-23 at 14:06 +0200, Philipp Stanner wrote:
> > vmgfx enables its PCI device with pcim_enable_device(). This,
> > implicitly, switches the function pci_request_regions() into managed
> > mode, where it becomes a devres functio
On Tue, May 6, 2025 at 11:27 AM Svyatoslav Ryhel wrote:
> R61307 is liquid crystal driver for high-definition amorphous silicon
> (a-Si) panels and is ideal for tablets and smartphones.
>
> Signed-off-by: Svyatoslav Ryhel
I see you have gone the extra mile and deduced the underlying
display con
Hi Krzysztof,
thanks for your patch!
On Mon, May 5, 2025 at 11:16 AM Krzysztof Kozlowski
wrote:
> Add driver for the Novatek NT37801 or NT37810 AMOLED DSI 1440x3200
> panel in CMD mode, used on Qualcomm MTP8750 board (SM8750).
>
> Signed-off-by: Krzysztof Kozlowski
(...)
> +static int novatek
[Public]
> -Original Message-
> From: Jani Nikula
> Sent: Thursday, May 8, 2025 8:16 PM
> To: Lin, Wayne ; dri-devel@lists.freedesktop.org
> Cc: ville.syrj...@linux.intel.com; Limonciello, Mario
> ;
> Wentland, Harry ; sta...@vger.kernel.org
> Subject: RE: [PATCH] drm/dp: Fix Write_Statu
On 08/05/2025 14:54, Linus Walleij wrote:
> (...)
>> +static int novatek_nt37801_on(struct novatek_nt37801 *ctx)
>> +{
>> + struct mipi_dsi_device *dsi = ctx->dsi;
>> + struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi };
>> +
>> + dsi->mode_flags |= MIPI_DSI_MODE_LPM;
>> +
>>
From: Jie Zhang
Add gpu and gmu nodes for qcs8300 chipset.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/qcs8300.dtsi | 91 +++
1 file changed, 91 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
b/arch/ar
From: Jie Zhang
Enable GPU for qcs8300-ride platform and provide path for zap
shader.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
Reviewed-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot
From: Jie Zhang
Document Adreno 623 GMU in the dt-binding specification.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
Reviewed-by: Krzysztof Kozlowski
---
.../devicetree/bindings/display/msm/gmu.yaml | 34 ++
1 file changed, 34 insertions(+)
diff --git a/
This series adds support for A623 GPU found in QCS8300 chipsets. This
GPU IP is very similar to A621 GPU, except for the UBWC configuration
and the GMU firmware.
Both DT patches are for Bjorn and the dt-bindings update for Rob Clark
to pick up.
---
Changes in v3:
- Rebased on top of v6.15-rc5
- D
On Mon, 05 May 2025, Anusha Srivatsa wrote:
> On Mon, May 5, 2025 at 2:54 AM Maxime Ripard wrote:
>
>> Hi Jani,
>>
>> On Tue, Apr 29, 2025 at 12:22:00PM +0300, Jani Nikula wrote:
>> > On Tue, 29 Apr 2025, Maxime Ripard wrote:
>> > > Hi Jani,
>> > >
>> > > On Mon, Apr 28, 2025 at 07:31:50PM +0300
Hi Dave, Sima,
here's the drm-misc-fixes PR for this week.
Best regards
Thomas
drm-misc-fixes-2025-05-08:
Short summary of fixes pull:
drm:
- Fix overflow when generating wedged event
ivpu:
- Increate timeouts
- Fix deadlock in cmdq ioctl
- Unlock mutices in correct order
panel:
- simple: Fix
On 5/7/25 18:09, Marek Szyprowski wrote:
> Use common wrappers operating directly on the struct sg_table objects to
> fix incorrect use of scatterlists sync calls. dma_sync_sg_for_*()
> functions have to be called with the number of elements originally passed
> to dma_map_sg_*() function, not the o
Am Donnerstag, dem 08.05.2025 um 16:56 +0200 schrieb Tomeu Vizoso:
> We should be comparing the last submitted sequence number with that of
> the address space we may be switching to.
>
This isn't the relevant change here though: if we switch the address
space, the comparison is moot, as we do a f
Merged to drm-misc-next
On 5/7/25 10:31, Lizhi Hou wrote:
On 5/7/25 09:29, Mario Limonciello wrote:
On 5/7/2025 11:15 AM, Lizhi Hou wrote:
The latest userspace runtime allows generating commands which do not
have any argument. Remove the corresponding check in driver IOCTL to
enable this use
Hi Biju,
Thanks for your patch.
On Thu, May 08, 2025 at 10:50:35AM +0100, Biju Das wrote:
> From: hienhuynh
>
> This patch is based on the commit 73eb5476df72 ("drm: rcar-du: Support
> panels connected directly to the DPAD outputs").
>
> The RZ DU driver assumes that a bridge is always connecte
On Mon, Apr 7, 2025 at 5:57 AM Neil Armstrong
wrote:
> On 03/04/2025 16:16, Anusha Srivatsa wrote:
> > Start converting drivers to use the API - devm_drm_panel_alloc().
> >
> > Sending next 30 drivers. Sending in batches for easier review.
> >
> > Part 1 of the series : https://patchwork.freedesk
On Tue, May 6, 2025 at 11:27 AM Svyatoslav Ryhel wrote:
> From: Maxim Schwalm
>
> Driver adds support for panels with Renesas R69328 IC
>
> Currently supported compatible is:
> - jdi,dx12d100vm0eaa
>
> Co-developed-by: Svyatoslav Ryhel
> Signed-off-by: Svyatoslav Ryhel
> Signed-off-by: Maxim S
On Tue, May 6, 2025 at 11:27 AM Svyatoslav Ryhel wrote:
> R69328 is liquid crystal driver for high-definition amorphous silicon
> (a-Si) panels and is ideal for tablets and smartphones.
>
> Signed-off-by: Svyatoslav Ryhel
Reviewed-by: Linus Walleij
Yours,
Linus Walleij
On Tue, May 6, 2025 at 11:27 AM Svyatoslav Ryhel wrote:
> R61307 is liquid crystal driver for high-definition amorphous silicon
> (a-Si) panels and is ideal for tablets and smartphones.
>
> Supported compatibles are:
> - hit,tx13d100vm0eaa
> - koe,tx13d100vm0eaa
>
> Signed-off-by: Svyatoslav Ryhe
On Mon, May 5, 2025 at 11:16 AM Krzysztof Kozlowski
wrote:
> Add bindings for the Novatek NT37801 or NT37810 AMOLED DSI panel.
> Sources, like downstream DTS, schematics and hardware manuals, use two
> model names (NT37801 and NT37810), so choose one and hope it is correct.
>
> Signed-off-by: Krz
> -Original Message-
> From: Alex Deucher
> Sent: Wednesday, April 23, 2025 8:51 PM
> To: Borah, Chaitanya Kumar ; Wentland,
> Harry ; Leo (Sunpeng) Li
> Cc: Murthy, Arun R ; dri-
> de...@lists.freedesktop.org; intel-...@lists.freedesktop.org; intel-
> x...@lists.freedesktop.org; alexande
Applied the series.
Thanks!
Alex
On Wed, May 7, 2025 at 1:13 PM wrote:
>
> From: "Dr. David Alan Gilbert"
>
> The previous patch removed smu_mode2_reset_is_support()
> which was the only function to call through the mode2_reset_is_support()
> method pointer.
>
> Remove the remaining functions
We should be comparing the last submitted sequence number with that of
the address space we may be switching to.
Fixes: 27b67278e007 ("drm/etnaviv: rework MMU handling")
Signed-off-by: Tomeu Vizoso
---
drivers/gpu/drm/etnaviv/etnaviv_buffer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
On Wed, May 07, 2025 at 11:19:21AM +0200, Neil Armstrong wrote:
> Convert the Truly NT35597 2K display panel bindings to dt-schema.
>
> The vdispp-supply & vdispn-supply are not marked as required since
> in practice they are not defined in sdm845-mtp.dts which is the
> only used of these bindings
On 03/05/2025 21:59, Maíra Canal wrote:
> Panfrost can skip the reset if TDR has fired before the IRQ handler.
> Currently, since Panfrost doesn't take any action on these scenarios, the
> job is being leaked, considering that `free_job()` won't be called.
>
> To avoid such leaks, use the DRM_GPU_
Add driver for the Novatek NT37801 or NT37810 AMOLED DSI 1440x3200
panel in CMD mode, used on Qualcomm MTP8750 board (SM8750).
Reviewed-by: Neil Armstrong
Reviewed-by: Linus Walleij
Signed-off-by: Krzysztof Kozlowski
---
MAINTAINERS | 6 +
drivers/gpu/drm/pa
On Tue, May 06, 2025 at 11:47:40PM +0800, Jun Nie wrote:
> Currently MAX_CHANNELS_PER_ENC is defined as 2, because 2 channels are
> supported at most in one encoder. The case of 4 channels per encoder is
> to be added. To avoid breaking current WB usage case, use dedicated WB
> definition before 4
On Thu, May 08, 2025 at 04:34:47PM +0200, Krzysztof Kozlowski wrote:
> Add bindings for the Novatek NT37801 or NT37810 AMOLED DSI panel.
> Sources, like downstream DTS, schematics and hardware manuals, use two
> model names (NT37801 and NT37810), so choose one and hope it is correct.
>
> Reviewed-
On 2025-05-08 09:38, Murthy, Arun R wrote:
>> -Original Message-
>> From: Alex Deucher
>> Sent: Wednesday, April 23, 2025 8:51 PM
>> To: Borah, Chaitanya Kumar ; Wentland,
>> Harry ; Leo (Sunpeng) Li
>> Cc: Murthy, Arun R ; dri-
>> de...@lists.freedesktop.org; intel-...@lists.freedesktop.
Hi,
On Thu, 08 May 2025 16:34:46 +0200, Krzysztof Kozlowski wrote:
> Changes in v2:
> - Use devm_drm_panel_alloc (Neil)
> - Add novatek_nt37801_switch_page (Linus)
> - Add Rb tags
> - Link to v1:
> https://lore.kernel.org/r/20250505-sm8750-display-panel-v1-0-e5b539848...@linaro.org
>
> Add drive
Hi,
On Wed, 07 May 2025 11:19:21 +0200, Neil Armstrong wrote:
> Convert the Truly NT35597 2K display panel bindings to dt-schema.
>
> The vdispp-supply & vdispn-supply are not marked as required since
> in practice they are not defined in sdm845-mtp.dts which is the
> only used of these bindings.
Hi Dave, Simona
The probably last drm-xe-next PR towards 6.16.
Almost only fixes, except for the PCIe link downgrade attributes.
Thanks,
Thomas
drm-xe-next-2025-05-08:
UAPI Changes:
- Expose PCIe link downgrade attributes (Raag)
Cross-subsystem Changes:
Core Changes:
- gpusvm has_dma_mapping f
On 5/6/2025 8:47 AM, Jun Nie wrote:
There are 2 pipes in a drm plane at most currently, while 4 pipes are
required for quad-pipe case. Generalize the handling to pipe pair and
ease handling to another pipe pair later. Store pipes in array with
removing dedicated r_pipe.
Signed-off-by: Jun Nie
On 5/6/2025 8:47 AM, Jun Nie wrote:
Currently, SSPPs are assigned to a maximum of two pipes. However,
quad-pipe usage scenarios require four pipes and involve configuring
two stages. In quad-pipe case, the first two pipes share a set of
mixer configurations and enable multi-rect mode when cert
On Thu, May 8, 2025 at 2:13 PM Konrad Dybcio wrote:
>
> From: Konrad Dybcio
>
> The value the UBWC hardware expects is 13 less than the actual value.
> To make it easier to migrate to a common UBWC configuration table,
> defer that logic to the data source (which is currently a number of
> if-els
The dmabuf iterator traverses the list of all DMA buffers.
DMA buffers are refcounted through their associated struct file. A
reference is taken on each buffer as the list is iterated to ensure each
buffer persists for the duration of the bpf program execution without
holding the list mutex.
Sign
This open coded iterator allows for more flexibility when creating BPF
programs. It can support output in formats other than text. With an open
coded iterator, a single BPF program can traverse multiple kernel data
structures (now including dmabufs), allowing for more efficient analysis
of kernel d
Until CONFIG_DMABUF_SYSFS_STATS was added [1] it was only possible to
perform per-buffer accounting with debugfs which is not suitable for
production environments. Eventually we discovered the overhead with
per-buffer sysfs file creation/removal was significantly impacting
allocation and free times
This test creates a udmabuf, and a dmabuf from the system dmabuf heap,
and uses a BPF program that prints dmabuf metadata with the new
dmabuf_iter to verify they can be found.
Signed-off-by: T.J. Mercier
---
tools/testing/selftests/bpf/config| 3 +
.../selftests/bpf/prog_tests/dmab
Rename the debugfs list and mutex so it's clear they are now usable
without the need for CONFIG_DEBUG_FS. The list will always be populated
to support the creation of a BPF iterator for dmabufs.
Signed-off-by: T.J. Mercier
Reviewed-by: Christian König
---
drivers/dma-buf/dma-buf.c | 40
Use the same test buffers as the traditional iterator and a new BPF map
to verify the test buffers can be found with the open coded dmabuf
iterator.
Signed-off-by: T.J. Mercier
---
.../testing/selftests/bpf/bpf_experimental.h | 5 ++
.../selftests/bpf/prog_tests/dmabuf_iter.c| 52 +
On Mon, Apr 7, 2025 at 6:04 AM Neil Armstrong
wrote:
> On 03/04/2025 22:20, Anusha Srivatsa wrote:
> > Start converting drivers to use the API - devm_drm_panel_alloc().
> >
> > Final set of drivers.
> >
> > Part 1 of the conversion :
> https://patchwork.freedesktop.org/series/147082/
> > Part 2 o
On Thu, May 8, 2025 at 11:20 AM T.J. Mercier wrote:
>
> Rename the debugfs list and mutex so it's clear they are now usable
> without the need for CONFIG_DEBUG_FS. The list will always be populated
> to support the creation of a BPF iterator for dmabufs.
>
> Signed-off-by: T.J. Mercier
> Reviewed
ngs: sram: sunxi-sram: Add H616 SRAM C compatible
> > dt-bindings: display: Add R40 and H616 display engine compatibles
> > drm/sun4i: tcon: Add support for R40 LCD
> > arm64: dts: allwinner: h616: add display engine, bus and mixer nodes
> > arm64: dts: allwinner:
On 5/6/2025 8:47 AM, Jun Nie wrote:
The capability stored in sblk and pipe_hw_caps is checked only for
SSPP of the first pipe in the pair with current implementation. That
of the 2nd pipe, r_pipe, is not checked and may violate hardware
capability. Move requirement check to dpu_plane_atomic_ch
On 5/6/2025 8:47 AM, Jun Nie wrote:
Currently MAX_CHANNELS_PER_ENC is defined as 2, because 2 channels are
supported at most in one encoder. The case of 4 channels per encoder is
to be added. To avoid breaking current WB usage case, use dedicated WB
definition before 4 WB usage case is support
From: Konrad Dybcio
The value the UBWC hardware expects is 13 less than the actual value.
To make it easier to migrate to a common UBWC configuration table,
defer that logic to the data source (which is currently a number of
if-else statements with assignments in case of this driver).
Signed-off
From: Konrad Dybcio
Start the great despaghettification by getting a pointer to the common
UBWC configuration, which houses e.g. UBWC versions that we need to
make decisions.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 16 ++--
drivers/gpu/drm/msm/adr
As discussed a lot in the past, the UBWC config must be coherent across
a number of IP blocks (currently display and GPU, but it also may/will
concern camera/video as the drivers evolve).
So far, we've been trying to keep the values reasonable in each of the
two drivers separately, but it really m
From: Konrad Dybcio
Add a file that will serve as a single source of truth for UBWC
configuration data for various multimedia blocks.
Signed-off-by: Konrad Dybcio
---
drivers/soc/qcom/Kconfig | 8 ++
drivers/soc/qcom/Makefile | 1 +
drivers/soc/qcom/ubwc_config.c | 255 +
From: Konrad Dybcio
To reduce room for error, move to fetching the config from a central
source, so that the data programmed into the hardware is consistent
across all multimedia blocks that request it.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/Kconfig | 1 +
drive
From: Konrad Dybcio
It's only necessary for some lower end parts.
Also rename it to min_acc_len_64b to denote that if set, the minimum
access length is 64 bits, 32b otherwise.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 15 ++-
1 file changed, 6 inserti
From: Konrad Dybcio
It's supposed to be on when the UBWC encoder version is >= 4.0.
Drop the per-GPU assignments.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gp
From: Konrad Dybcio
SC8180X (A680) and SA8775P (A663) require a write to that register,
while other SKUs are fine with the default value. Don't overwrite it
needlessly, requiring the developer to read the value back from
hardware just to put it in the driver again, introducing much more room
for
From: Konrad Dybcio
ubwc_swizzle is a bitmask. Check for a bit to make it more obvious.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno
From: Konrad Dybcio
The bit must be set to 1 if the UBWC encoder version is >= 3.0, drop it
as a separate field.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 12 +++-
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6
From: Konrad Dybcio
Instead of setting it on a gpu-per-gpu basis, converge it to the
intended "is A650 family or A7xx".
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 12 +++-
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/msm/ad
From: Konrad Dybcio
On A663 (SA8775P) the value matches exactly.
On A610, the value matches on SM6115, but is different on SM6125. That
turns out not to be a problem, as the bits that differ aren't even
interpreted.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 9 ++
From: Konrad Dybcio
Make use of the SSOT config database, this time including the HBB
which doesn't seem to change between configurations.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/d
From: Konrad Dybcio
This bit is set iff the UBWC version is 1.0. That notably does not
include QCM2290's "no UBWC".
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
On Thu, May 8, 2025 at 11:13 AM Konrad Dybcio wrote:
>
> From: Konrad Dybcio
>
> Start the great despaghettification by getting a pointer to the common
> UBWC configuration, which houses e.g. UBWC versions that we need to
> make decisions.
>
> Signed-off-by: Konrad Dybcio
> ---
> drivers/gpu/dr
On Thu, May 8, 2025 at 2:14 PM Konrad Dybcio wrote:
>
> From: Konrad Dybcio
>
> This bit is set iff the UBWC version is 1.0. That notably does not
> include QCM2290's "no UBWC".
While this is technically true, AFAIK the only difference between UBWC
1.0 and 2.0 is that newer UBWC disables level 1
On Thu, May 8, 2025 at 7:08 PM Lucas Stach wrote:
>
> Am Donnerstag, dem 08.05.2025 um 16:56 +0200 schrieb Tomeu Vizoso:
> > We should be comparing the last submitted sequence number with that of
> > the address space we may be switching to.
> >
> This isn't the relevant change here though: if we
Hi Vitor,
kernel test robot noticed the following build warnings:
[auto build test WARNING on linus/master]
[also build test WARNING on v6.15-rc5 next-20250508]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--bas
On Thu, May 8, 2025 at 2:13 PM Konrad Dybcio wrote:
>
> From: Konrad Dybcio
>
> The bit must be set to 1 if the UBWC encoder version is >= 3.0, drop it
> as a separate field.
For these sorts of things, it's probably best to add a helper to the
common ubwc config header. Other blocks also have bi
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