Hi,
On 24/11/2024 23:29, Sasha Finkelstein via B4 Relay wrote:
From: Sasha Finkelstein
Please use "drm: " and drop gpu from commit title.
This display controller is present on M-series chips and is used
to drive the touchbar display.
Co-developed-by: Janne Grunau
Signed-off-by: Janne Gru
On Sun, 24 Nov 2024, Sasha Finkelstein via B4 Relay
wrote:
> diff --git a/drivers/gpu/drm/adp/adp_drv.c b/drivers/gpu/drm/adp/adp_drv.c
> new file mode 100644
> index
> ..36510194e18161ef6514885c764b2e7085c587e5
> --- /dev/null
> +++ b/drivers/gpu/drm/adp/
On Fri, 22 Nov 2024, Louis Chauvet wrote:
> As an encoder will be a directory in ConfigFS, add the configuration for
> encoder name so we will be able to reflect the configfs directory name in
> the drm name.
>
> Signed-off-by: Louis Chauvet
> ---
> drivers/gpu/drm/vkms/vkms_config.c | 6 ++
On Wed, 2024-09-18 at 15:39 +0200, Christian König wrote:
> Sima requested that in a discussion, just copy&paste my explanation
> from
> the mail.
>
> Signed-off-by: Christian König
> ---
> drivers/gpu/drm/scheduler/sched_entity.c | 17 +++--
> 1 file changed, 15 insertions(+), 2 del
On Mon, Nov 25, 2024 at 05:33:13PM +0800, Liu Ying wrote:
> Add display controller subsystem in i.MX8qxp SoC.
>
> Signed-off-by: Liu Ying
...
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> index 05138326f0a5..35cc82cbbcd1 100644
> ---
> On Mon, Nov 18, 2024 at 01:23:14PM +0530, Arun R Murthy wrote:
> > Expose drm plane function to create formats/modifiers blob. This
> > function can be used to expose list of supported formats/modifiers for
> > sync/async flips.
> >
> > Signed-off-by: Arun R Murthy
> > ---
> > drivers/gpu/drm/d
Hi,
This patch series aims to add Freescale i.MX8qxp Display Controller support.
The controller is comprised of three main components that include a blit
engine for 2D graphics accelerations, display controller for display output
processing, as well as a command sequencer.
Previous patch series
i.MX8qxp Display Controller pixel engine consists of all processing
units that operate in the AXI bus clock domain. Add drivers for
ConstFrame, ExtDst, FetchLayer, FetchWarp and LayerBlend units, as
well as a pixel engine driver, so that two displays with primary
planes can be supported. The pixe
i.MX8qxp Display Controller display engine consists of all processing
units that operate in a display clock domain. Add minimal feature
support with FrameGen and TCon so that the engine can output display
timings. The display engine driver as a master binds FrameGen and
TCon drivers as components
i.MX8qxp Display Controller contains a blit engine for raster graphics.
It may read up to 3 source images from memory and computes one destination
image from it, which is written back to memory.
Signed-off-by: Liu Ying
Reviewed-by: Rob Herring (Arm)
---
v4:
* Collect Rob's R-b tag.
v3:
* New pa
Freescale i.MX8qxp Display Controller is implemented as construction set of
building blocks with unified concept and standardized interfaces. Document
all existing processing units.
Signed-off-by: Liu Ying
Reviewed-by: Rob Herring (Arm)
---
v4:
* Collect Rob's R-b tag.
v3:
* Combine fsl,imx8qx
i.MX8qxp Display Controller contains a command sequencer is designed to
autonomously process command lists.
Signed-off-by: Liu Ying
---
v4:
* Replace "fsl,iram" property with standard "sram" property. (Rob)
v3:
* New patch. (Rob)
.../imx/fsl,imx8qxp-dc-command-sequencer.yaml | 67 +
i.MX8qxp Display Controller pixel engine consists of all processing units
that operate in the AXI bus clock domain. Command sequencer and interrupt
controller of the Display Controller work with AXI bus clock, but they are
not in pixel engine.
Signed-off-by: Liu Ying
Reviewed-by: Rob Herring (Ar
i.MX8qxp Display Controller(DC) is comprised of three main components that
include a blit engine for 2D graphics accelerations, display controller for
display output processing, as well as a command sequencer.
Signed-off-by: Liu Ying
Reviewed-by: Rob Herring (Arm)
---
v4:
* Collect Rob's R-b tag
i.MX8qxp Display Controller contains a AXI performance counter which allows
measurement of average bandwidth and latency during operation.
Signed-off-by: Liu Ying
Reviewed-by: Rob Herring (Arm)
---
v4:
* Collect Rob's R-b tag.
v3:
* New patch. (Rob)
...sl,imx8qxp-dc-axi-performance-counter.ya
i.MX8qxp Display Controller(DC) is comprised of three main components that
include a blit engine for 2D graphics accelerations, display controller for
display output processing, as well as a command sequencer. Add kernel
mode setting support for the display controller part with two CRTCs and
two p
The MIPI-LVDS combo subsystems are peripherals of pixel link MSI
bus in i.MX8qxp display controller subsystem. Add the MIPI-LVDS
combo subsystems.
Signed-off-by: Liu Ying
---
v4:
* No change.
v3:
* No change.
v2:
* New patch. (Francesco)
.../boot/dts/freescale/imx8qxp-ss-dc.dtsi | 4 +
i.MX8qxp Display Controller has a built-in interrupt controller to support
Enable/Status/Preset/Clear interrupt bit. Add driver for it.
Signed-off-by: Liu Ying
---
v4:
* Use regmap to define register map for all registers. (Dmitry)
* Use regmap APIs to access registers. (Dmitry)
* Use devm_kzall
Add myself as the maintainer of i.MX8qxp Display Controller.
Signed-off-by: Liu Ying
---
v4:
* No change.
v3:
* No change.
v2:
* Improve file list. (Frank)
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index cf1d81bd04a7..3a1489236d43 100644
Enable display controller for i.MX8qxp MEK.
Signed-off-by: Liu Ying
---
v4:
* No change.
v3:
* No change.
v2:
* New patch. (Francesco)
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
b/arch/ar
Document SCU controlled display pixel link child nodes.
Signed-off-by: Liu Ying
---
v4:
* No change.
v3:
* No change.
v2:
* New patch as needed by display controller subsystem device tree.
.../devicetree/bindings/firmware/fsl,scu.yaml | 20 +++
1 file changed, 20 insertions(+)
assigned-clock* properties can be used by default now, so allow them.
Signed-off-by: Liu Ying
---
v4:
* No change.
v3:
* No change.
v2:
* New patch as needed by MIPI/LVDS subsystems device tree.
.../devicetree/bindings/phy/mixel,mipi-dsi-phy.yaml | 5 -
1 file changed, 5 deletion
On Fri, 22 Nov 2024, Louis Chauvet wrote:
> As a CRTC will be a directory in ConfigFS, add the name configuration for
> CRTC name so we will be able to reflect the configfs directory name in the
> drm name.
>
> Signed-off-by: Louis Chauvet
> ---
> drivers/gpu/drm/vkms/vkms_config.c | 5 +
>
MX8-DLVDS-LCD1 display module integrates a KOE TX26D202VM0BWA LCD panel
and a touch IC. Add an overlay to support the LCD panel on i.MX8qxp
MEK. mipi_lvds_0_ldb channel0 and mipi_lvds_1_ldb channel1 send odd
and even pixels to the panel respectively.
Signed-off-by: Liu Ying
---
v4:
* No change.
On Fri, 22 Nov 2024, Louis Chauvet wrote:
> To properly test the EDID reading without using the DRM override, add an
> option to configure the EDID for a connector.
>
> Signed-off-by: Louis Chauvet
> ---
> drivers/gpu/drm/vkms/vkms_config.c | 1 +
> drivers/gpu/drm/vkms/vkms_config.h | 2 ++
>
Am 22.11.24 um 17:02 schrieb Raag Jadav:
On Fri, Nov 22, 2024 at 11:09:32AM +0100, Christian König wrote:
Am 22.11.24 um 08:07 schrieb Raag Jadav:
On Mon, Nov 18, 2024 at 08:26:37PM +0530, Aravind Iddamsetty wrote:
On 15/11/24 10:37, Raag Jadav wrote:
Introduce device wedged event, which noti
i.MX8qxp Display Controller display engine consists of all processing units
that operate in a display clock domain.
Signed-off-by: Liu Ying
Reviewed-by: Rob Herring (Arm)
---
v4:
* Collect Rob's R-b tag.
v3:
* No change.
v2:
* Drop fsl,dc-*-id DT properties. (Krzysztof)
* Drop port property. (
Le 25 novembre 2024 09:28:44 UTC, Jani Nikula a
écrit :
>On Fri, 22 Nov 2024, Louis Chauvet wrote:
>> As an encoder will be a directory in ConfigFS, add the configuration for
>> encoder name so we will be able to reflect the configfs directory name in
>> the drm name.
>>
>> Signed-off-by: Lou
On Fri, 22 Nov 2024 11:12:57 +0200, Dmitry Baryshkov wrote:
> If the connector->modes list is empty, then list_first_entry() returns a
> bogus entry. Change that to use list_first_entry_or_null().
>
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Maxime Ripard
Thanks!
Maxime
https://gitlab.freedesktop.org/drm/kernel
> > 28eb75e178d389d325f1666e422bc139804c
> > Compiler: m68k-linux-gcc (GCC) 8.1.0 / GNU ld (GNU Binutils) 2.30
> >
> > ERROR: modpost: "__udivdi3"
> > [drivers/gpu/drm/rockchip/
Hi
Am 23.11.24 um 17:28 schrieb Dmitry Baryshkov:
On Tue, Oct 29, 2024 at 03:34:23PM +0100, Thomas Zimmermann wrote:
The cirrus driver only works on emulated Cirrus hardware. Use the
correct types for encoder and connector.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/tiny/cirrus.c
On 11/24/2024 2:48 PM, Marek Vasut wrote:
The DSI host must be enabled for the panel to be initialized in
prepare(). Set the prepare_prev_first flag to guarantee this.
This fixes the panel operation on NXP i.MX8MP SoC / Samsung DSIM
DSI host.
Hi Marek,
LGTM.
Reviewed-by: Jessica Zhang
Th
On 11/25/24 10:31, Vivek Kasireddy wrote:
> +static void virtgpu_dma_buf_free_obj(struct drm_gem_object *obj)
> +{
> + struct virtio_gpu_object *bo = gem_to_virtio_gpu_obj(obj);
> + struct virtio_gpu_device *vgdev = obj->dev->dev_private;
> + struct dma_buf_attachment *attach = obj->imp
On Mon, Nov 25, 2024 at 10:03:00PM +0530, Akhil P Oommen wrote:
> There are a few chipsets which don't have system cache a.k.a LLC.
> Currently, the assumption in the driver is that the system cache
> availability correlates with the presence of GMU or RPMH, which
> is not true. For instance, Snapd
On 11/25/24 19:27, Dmitry Osipenko wrote:
> On 11/25/24 10:31, Vivek Kasireddy wrote:
>> +static void virtgpu_dma_buf_free_obj(struct drm_gem_object *obj)
>> +{
>> +struct virtio_gpu_object *bo = gem_to_virtio_gpu_obj(obj);
>> +struct virtio_gpu_device *vgdev = obj->dev->dev_private;
>> +
On 11/25/24 1:21 PM, Konrad Dybcio wrote:
On 24.11.2024 11:00 AM, Maud Spierings via B4 Relay wrote:
From: Maud Spierings
The Asus vivobook s15 uses the ATNA56AC03 panel.
This panel is controlled by the atna33xc20 driver instead of the generic
edp-panel driver
Signed-off-by: Maud Spierings
-
On Mon, Nov 25, 2024 at 02:33:35AM +0100, Marek Vasut wrote:
> Add Multi-Inno Technology MI0700A2T-30 7" 800x480 LVDS panel
> compatible string.
>
> Signed-off-by: Marek Vasut
> ---
> Cc: Conor Dooley
Acked-by: Conor Dooley
signature.asc
Description: PGP signature
From: Maud Spierings
The Asus vivobook s15 uses the ATNA56AC03 panel.
This panel is controlled by the atna33xc20 driver instead of the generic
edp-panel driver
Signed-off-by: Maud Spierings
---
.../arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts | 18 +-
1 file changed, 17 i
Improves several parts of the devicetree:
1. The eDP panel bindings
2. Add a lid switch
3. Add bluetooth and describe wlan (depends on [1])
[1]:
https://lore.kernel.org/all/20241007-x1e80100-pwrseq-qcp-v1-0-f7166510a...@linaro.org/
---
I seem to get a warning that the pci17cb vendor is undocumen
From: Maud Spierings
Add bluetooth for the asus vivobook s15
Describe wlan configuration
Signed-off-by: Maud Spierings
---
.../boot/dts/qcom/x1e80100-asus-vivobook-s15.dts | 164 +
1 file changed, 164 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100-asus-vivo
From: Maud Spierings
Add the lid switch for the Asus vivobook s15
Reviewed-by: Konrad Dybcio
Signed-off-by: Maud Spierings
---
.../boot/dts/qcom/x1e80100-asus-vivobook-s15.dts| 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100-asus-
Hi Andy,
Yes, the issue can be reproduced with the details in patch 2/3 [1].
[1]:
https://lore.kernel.org/linux-arm-kernel/20241115162120.83990-3-detlev.casan...@collabora.com/T/#m82b38f4a83c4793bb82919bf736b2f6bd804a283
Detlev.
On Monday, 25 November 2024 02:55:41 EST Andy Yan wrote:
> Hello
From: Zichen Xie
Like commit b0b0d811eac6 ("drm/mediatek: Fix coverity issue with
unintentional integer overflow"), directly multiply args->pitch and
args->height may lead to integer overflow. Add a cast to avoid it.
Signed-off-by: Zichen Xie
---
drivers/gpu/drm/xen/xen_drm_front.c | 2 +-
1 f
Tested working.
Tested-by: Ian Forbes
On Thu, Nov 21, 2024 at 4:27 AM Christian König
wrote:
>
> Start switching over vmwgfx to drm_exec as well. Replacing some
> unnecessary complex calls with just just single BO dma_resv locking.
>
> No intentional functional change, but only compile tested f
Breaks userspace command submission. Here's the log with lock debugging on.
```
[ 20.438106]
[ 20.439696] WARNING: lock held when returning to user space!
[ 20.441730] 6.12.0+ #11 Not tainted
[ 20.442389]
On 11/25/24 10:31, Vivek Kasireddy wrote:
> struct drm_gem_object *virtgpu_gem_prime_import(struct drm_device *dev,
> struct dma_buf *buf)
> {
> + struct virtio_gpu_device *vgdev = dev->dev_private;
> + struct dma_buf_attachment *attach;
> +
From: Zichen Xie
Like commit b0b0d811eac6 ("drm/mediatek: Fix coverity issue with
unintentional integer overflow"), directly multiply pitch and
args->height may lead to integer overflow. Add a cast to avoid it.
Signed-off-by: Zichen Xie
---
drivers/gpu/drm/qxl/qxl_dumb.c | 2 +-
1 file changed
On Mon, Nov 25, 2024 at 05:19:54PM +0100, Christian König wrote:
> Am 25.11.24 um 16:29 schrieb Matthew Brost:
> > On Fri, Nov 15, 2024 at 10:27:59AM -0800, Matthew Brost wrote:
> > > [SNIP]
> > > We use this interface to read a BO marked with a dumpable flag during a
> > > GPU hang in our error ca
Hi,
On Sun, Nov 24, 2024 at 5:20 AM Jens Glathe via B4 Relay
wrote:
>
> From: Jens Glathe
>
> Seems to be like NV140DRM-N61 but with touch. Haven't disassembled
> the lid to look.
>
> Due to lack of information, use the delay_200_500_e200 timings like
> many other BOE panels do for now.
>
> The
Il 22/11/24 07:23, CK Hu (胡俊光) ha scritto:
Hi, Angelo:
On Fri, 2024-11-22 at 11:54 +0800, CK Hu wrote:
Hi, Angelo:
On Wed, 2024-11-20 at 13:44 +0100, AngeloGioacchino Del Regno wrote:
External email : Please do not click links or open attachments until you have
verified the sender or the con
Il 22/11/24 08:23, CK Hu (胡俊光) ha scritto:
Hi, Angelo:
On Wed, 2024-11-20 at 13:44 +0100, AngeloGioacchino Del Regno wrote:
External email : Please do not click links or open attachments until you have
verified the sender or the content.
Add support for the DPI block found in the MT8195 and
Hi,
On Sun, Nov 24, 2024 at 2:01 AM Maud Spierings via B4 Relay
wrote:
>
> From: Maud Spierings
>
> The Samsung ATNA56AC03 panel is an AMOLED eDP panel.
> It is similar to the ATNA33xc20 except it is larger and has a different
> resolution.
>
> Signed-off-by: Maud Spierings
> ---
> Documentati
On 11/14/24 1:46 AM, Dave Airlie wrote:
From: Dave Airlie
When this code moved to non-coherent allocator the sync was put too
early for some firmwares which called the setup function, move the
sync down after the setup function.
Reported-by: Diogo Ivo
Do you have a link of where this issue
On Mon, Nov 25, 2024 at 10:07:03PM +0530, Parthiban Nallathambi wrote:
> GE8300 in Allwinner A133 have reset control from the ccu.
> Add the resets property as optional one to control it.
There's no specific compatible here for an a133, but the binding
requires one. Where is your dts patch?
>
>
Fix the MST sideband message body length check, which must be at least 1
byte accounting for the message body CRC (aka message data CRC) at the
end of the message.
This fixes a case where an MST branch device returns a header with a
correct header CRC (indicating a correctly received body length),
Reviewed-by: Lyude Paul
On Mon, 2024-11-25 at 22:53 +0200, Imre Deak wrote:
> Fix the MST sideband message body length check, which must be at least 1
> byte accounting for the message body CRC (aka message data CRC) at the
> end of the message.
>
> This fixes a case where an MST branch device r
Am Sat, 23 Nov 2024 18:14:05 +
schrieb Mithil Bavishi :
> > > + no-map;
> > > + reg = <0xA000 0x20>;
> >
> > If used for ramoops, then there should be a compatible = "ramoops"
> > see Documentation/devicetree/bindings/reserved-memory/ramoops.yaml
> >
On Mon, 25 Nov 2024 at 15:17, Maxime Ripard wrote:
>
> On Fri, Nov 22, 2024 at 03:32:57PM +0200, Dmitry Baryshkov wrote:
> > On Tue, Nov 12, 2024 at 03:05:37AM +0100, Marek Vasut wrote:
> > > The Pixel PLL is not very capable and may come up with wildly inaccurate
> > > clock. Since DPI panels are
On Mon, 25 Nov 2024 at 09:39, fange zhang wrote:
>
>
>
> On 2024/11/22 18:22, Dmitry Baryshkov wrote:
> > On Fri, Nov 22, 2024 at 05:56:52PM +0800, Fange Zhang wrote:
> >> From: Li Liu
> >>
> >> Add display MDSS and DSI configuration for QCS615 RIDE board.
> >> QCS615 has a DP port, and DP suppor
On Mon, 25 Nov 2024 at 04:31, fange zhang wrote:
>
>
>
> On 2024/11/22 18:10, Dmitry Baryshkov wrote:
> > On Fri, Nov 22, 2024 at 05:56:50PM +0800, Fange Zhang wrote:
> >> From: Li Liu
> >>
> >> Add support for DSI 2.3.1 (block used on SM6150).
> >>
> >> Signed-off-by: Li Liu
> >> Signed-off-by:
Hi,
On 24/11/2024 19:18, Aradhya Bhatia wrote:
Hi Tomi, Devarsh,
On 10/21/24 19:37, Tomi Valkeinen wrote:
It has been observed that sometimes DSS will trigger an interrupt and
the top level interrupt (DISPC_IRQSTATUS) is not zero, but the VP and
VID level interrupt-statuses are zero.
Does th
Add display controller subsystem in i.MX8qxp SoC.
Signed-off-by: Liu Ying
---
v4:
* No change.
v3:
* No change.
v2:
* New patch. (Krzysztof)
.../arm64/boot/dts/freescale/imx8-ss-dc0.dtsi | 408 ++
.../boot/dts/freescale/imx8qxp-ss-dc.dtsi | 236 ++
arch/arm64/boot/
Hi Christian,
On Mon, Nov 25, 2024 at 11:39:58AM +0100, Christian Göttsche wrote:
> From: Christian Göttsche
>
> capable() calls refer to enabled LSMs whether to permit or deny the
> request. This is relevant in connection with SELinux, where a
> capability check results in a policy decision an
This still has the bug that I originally reported at:
https://github.com/AsahiLinux/linux/issues/258
On Sun, Nov 24, 2024 at 11:29:25PM +0100, Sasha Finkelstein via B4 Relay wrote:
> +static int adp_probe(struct platform_device *pdev)
> +{
> + struct adp_drv_private *adp;
> + int err;
> +
On Sat, Nov 23, 2024 at 06:28:30PM +0200, Dmitry Baryshkov wrote:
> On Tue, Oct 29, 2024 at 03:34:23PM +0100, Thomas Zimmermann wrote:
> > The cirrus driver only works on emulated Cirrus hardware. Use the
> > correct types for encoder and connector.
> > connector = &cirrus->connector;
> >
On 2024-11-24 14:29, Sasha Levin wrote:
> From: Ausef Yousof
>
> [ Upstream commit d7b86a002cf7e1b55ec311c11264f70d079860b9 ]
>
> This reverts commit 4f01a68751194d05280d659a65758c09e4af04d6.
Which was patch 16 in this series...
--
Earthling Michel Dänzer \GNOME / Xwayland / Me
On Fri, 22 Nov 2024 11:13:06 +0200, Dmitry Baryshkov wrote:
> Replace sun4i_hdmi_connector_atomic_check(), which performs just TMDS
> char rate check, with drm_atomic_helper_connector_hdmi_check(), which
> performs additional checks basing on the HDMI Connector's state.
>
> Suggested-by: Maxime Ri
On Fri, Nov 22, 2024 at 11:12:58AM +0200, Dmitry Baryshkov wrote:
> As pointed out by Maxime, the drm_atomic_helper_connector_hdmi_init()
> isn't a good name for a function inside KUnit tests. Rename it to
> drm_kunit_helper_connector_hdmi_init().
>
> Suggested-by: Maxime Ripard
> Signed-off-by:
Hi,
On 24/11/2024 23:29, Sasha Finkelstein via B4 Relay wrote:
From: Sasha Finkelstein
This is the display panel used for the touchbar on laptops that have it.
Co-developed-by: Nick Chan
Signed-off-by: Nick Chan
Signed-off-by: Sasha Finkelstein
---
drivers/gpu/drm/adp/panel-summit.c | 10
On Fri, 22 Nov 2024 11:12:59 +0200, Dmitry Baryshkov wrote:
> The set_connector_edid() function returns a bogus 0, performing the
> check on the connector->funcs->fill_modes() result internally. Make the
> function pass the fill_modes()'s return value to the caller and move
> corresponding checks t
i.MX8qxp Display Controller has a built-in interrupt controller to support
Enable/Status/Preset/Clear interrupt bit.
Signed-off-by: Liu Ying
Reviewed-by: Rob Herring (Arm)
---
v4:
* No change.
v3:
* Collect Rob's R-b tag.
v2:
* Drop unneeded "|". (Krzysztof)
.../fsl,imx8qxp-dc-intc.yaml
Il 22/11/24 10:20, Maxime Ripard ha scritto:
Hi,
On Wed, Nov 20, 2024 at 01:45:12PM +0100, AngeloGioacchino Del Regno wrote:
Add support for the newer HDMI-TX (Encoder) v2 and DDC v2 IPs
found in MediaTek's MT8195, MT8188 SoC and their variants, and
including support for display modes up to 4k6
On Mon, Nov 25, 2024 at 10:40:22AM +0100, AngeloGioacchino Del Regno wrote:
> Il 22/11/24 10:20, Maxime Ripard ha scritto:
> > Hi,
> >
> > On Wed, Nov 20, 2024 at 01:45:12PM +0100, AngeloGioacchino Del Regno wrote:
> > > Add support for the newer HDMI-TX (Encoder) v2 and DDC v2 IPs
> > > found in
Le 25 novembre 2024 09:45:04 UTC, Jani Nikula a
écrit :
>On Fri, 22 Nov 2024, Louis Chauvet wrote:
>> To properly test the EDID reading without using the DRM override, add an
>> option to configure the EDID for a connector.
>>
>> Signed-off-by: Louis Chauvet
>> ---
>> drivers/gpu/drm/vkms/v
Am 25.11.24 um 06:56 schrieb Aravind Iddamsetty:
On 22/11/24 21:32, Raag Jadav wrote:
On Fri, Nov 22, 2024 at 11:09:32AM +0100, Christian König wrote:
Am 22.11.24 um 08:07 schrieb Raag Jadav:
On Mon, Nov 18, 2024 at 08:26:37PM +0530, Aravind Iddamsetty wrote:
On 15/11/24 10:37, Raag Jadav wro
On 24.11.2024 11:00 AM, Maud Spierings via B4 Relay wrote:
> From: Maud Spierings
>
> The Asus vivobook s15 uses the ATNA56AC03 panel.
> This panel is controlled by the atna33xc20 driver instead of the generic
> edp-panel driver
>
> Signed-off-by: Maud Spierings
> ---
> arch/arm64/boot/dts/qco
On 24.11.2024 11:00 AM, Maud Spierings via B4 Relay wrote:
> From: Maud Spierings
>
> Add the lid switch for the Asus vivobook s15
>
> Signed-off-by: Maud Spierings
> ---
Reviewed-by: Konrad Dybcio
Konrad
Hi,
Thanks. Applied to https://gitlab.freedesktop.org/drm/misc/kernel.git
(drm-misc-next)
[1/1] drm/lsdc: Request PCI BAR
https://gitlab.freedesktop.org/drm/misc/kernel/-/commit/ca053ee3c6a7a877754e6f444ce5f520e3c0a856
On 2024/11/25 22:02, Philipp Stanner wrote:
lsdc currently just io
On 25/11/2024 15:14, Hector Martin wrote:
>>> +
>>> + "#address-cells":
>>> +const: 1
>>> +
>>> + "#size-cells":
>>> +const: 0
>>> +
>>> +additionalProperties: true
>>
>> This cannot be true. Must be false.
>>
>>> +
>>> +required:
>>> + - compatible
>>> + - reg
>>> + - interrupts
>>
>>
On Fri, 22 Nov 2024 17:27:56 +0100, Louis Chauvet wrote:
> The current VKMS driver uses non-managed function to create connectors. It
> is not an issue yet, but in order to support multiple devices easily,
> convert this code to use drm and device managed helpers.
>
> Signed-off-by: Louis Chauvet
On Fri, Nov 22, 2024 at 05:27:59PM +0100, Louis Chauvet wrote:
> Currently drm_writeback_connector are created by
> drm_writeback_connector_init or drm_writeback_connector_init_with_encoder.
> Both of the function uses drm_connector_init and drm_encoder_init, but
> there is no way to properly clean
On Fri, 22 Nov 2024 17:27:57 +0100, Louis Chauvet wrote:
> The current VKMS driver uses non-managed function to create encoders. It
> is not an issue yet, but in order to support multiple devices easily,
> convert this code to use drm and device managed helpers.
>
> Signed-off-by: Louis Chauvet
>
On Fri, 22 Nov 2024 17:27:58 +0100, Louis Chauvet wrote:
> The current VKMS driver uses managed function to create crtc, but
> don't use it to properly clean the crtc workqueue. It is not an
> issue yet, but in order to support multiple devices easily,
> convert this code to use drm and device mana
p),%rcx# 0xd0647
10: f7 d8 neg%eax
12: 64 89 01mov%eax,%fs:(%rcx)
15: 48 rex.W
The kernel config and materials to reproduce are available at:
https://download.01.org/0day-ci/archive/20241125/202411252029.30061fde-...@int
On November 25, 2024 4:28:00 PM GMT+01:00, Maxime Ripard
wrote:
>On Mon, Nov 25, 2024 at 11:24:25PM +0900, Hector Martin wrote:
>>
>>
>> On 2024/11/25 20:24, Sasha Finkelstein wrote:
>> > On Mon, 25 Nov 2024 at 09:50, Neil Armstrong
>> > wrote:
>> >>
>> >> So this controller only supports a s
On Wed, Nov 20, 2024 at 08:32:45PM +0800, Zhang He wrote:
> in function `i915_gem_gtt_reserve` @node comment,
> i915_vma has no `mode` member, `i915_vma.node` is the correct name
>
> Signed-off-by: Zhang He
Reviewed-by: Rodrigo Vivi
and pushed to drm-intel-next. Thanks for the patch
> ---
>
Hi Sean,
On Mon, Nov 25, 2024 at 02:49:26PM +0100, Sean Nyekjaer wrote:
> Check if the required pixel clock is in within .5% range of the
> desired pixel clock.
> This will match the requirement for HDMI where a .5% tolerance is allowed.
>
> Signed-off-by: Sean Nyekjaer
> ---
> drivers/gpu/drm/
On Mon, 25 Nov 2024 14:49:28 +0100, Sean Nyekjaer wrote:
> When using the DSI interface via DSI2LVDS bridge, it seems a bit harsh
> to reguire the requested and the actual px clock to be within
> 50Hz. A typical LVDS display requires the px clock to be within +-10%.
>
> In case for HDMI .5% tolera
On Mon, 25 Nov 2024 14:49:27 +0100, Sean Nyekjaer wrote:
> Use new helper function for HDMI mode validation
>
> Signed-off-by: Sean Nyekjaer
Reviewed-by: Maxime Ripard
Thanks!
Maxime
On Mon, Nov 25, 2024 at 9:50 PM Sean Nyekjaer wrote:
>
> Use new helper function for HDMI mode validation
This is a bit misleading since this is actually the DPI or parallel
output encoder, not HDMI. HDMI is in drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
and drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
Chen
lsdc currently just ioremaps its PCI BAR with pcim_iomap(). Performing
a region regquest additionally can make the driver more robust.
Replace pcim_iomap() with the managed function pcim_iomap_region() which
performs the request and ioremaps the BAR.
Signed-off-by: Philipp Stanner
Reviewed-by: S
Hi Hector,
On 25/11/2024 15:24, Hector Martin wrote:
On 2024/11/25 20:24, Sasha Finkelstein wrote:
On Mon, 25 Nov 2024 at 09:50, Neil Armstrong wrote:
So this controller only supports a single mode ???
Most likely. On all devices it is connected to a single built-in display.
More s
From: Carlos Song
Add eDMA mode support for LPI2C.
There are some differences between TX DMA mode and RX DMA mode.
LPI2C MTDR register is Controller Transmit Data Register.
When lpi2c send data, it is tx cmd register and tx data fifo.
When lpi2c receive data, it is just a rx cmd register. LPI2C
Check if the required pixel clock is in within .5% range of the
desired pixel clock.
This will match the requirement for HDMI where a .5% tolerance is allowed.
Signed-off-by: Sean Nyekjaer
---
drivers/gpu/drm/drm_modes.c | 34 ++
include/drm/drm_modes.h | 2 +
-commit: 28eb75e178d389d325f1666e422bc139804c
change-id: 20241125-dsi-relax-1414baf6cd74
Best regards,
--
Sean Nyekjaer
When using the DSI interface via DSI2LVDS bridge, it seems a bit harsh
to reguire the requested and the actual px clock to be within
50Hz. A typical LVDS display requires the px clock to be within +-10%.
In case for HDMI .5% tolerance is required.
Signed-off-by: Sean Nyekjaer
---
drivers/gpu/dr
Use new helper function for HDMI mode validation
Signed-off-by: Sean Nyekjaer
---
drivers/gpu/drm/sun4i/sun4i_rgb.c | 22 --
1 file changed, 4 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_rgb.c
b/drivers/gpu/drm/sun4i/sun4i_rgb.c
index
dfb6acc42f
On 2024/11/25 16:45, Krzysztof Kozlowski wrote:
> On Sun, Nov 24, 2024 at 11:29:24PM +0100, Sasha Finkelstein wrote:
>> Add bindings for a secondary display controller present on certain
>> Apple laptops.
>>
>> Signed-off-by: Sasha Finkelstein
>> ---
>> .../bindings/display/apple,display-pipe.yam
On 2024/11/25 20:24, Sasha Finkelstein wrote:
> On Mon, 25 Nov 2024 at 09:50, Neil Armstrong
> wrote:
>>
>> So this controller only supports a single mode ???
>>
> Most likely. On all devices it is connected to a single built-in display.
More specifically, the controller obviously support
Il 21/11/24 22:02, Rob Herring ha scritto:
On Wed, Nov 20, 2024 at 01:45:06PM +0100, AngeloGioacchino Del Regno wrote:
Add a binding for the Display Data Channel (DDC) IP in MediaTek
SoCs with version 2 HDMI TX IP.
Signed-off-by: AngeloGioacchino Del Regno
---
.../mediatek/mediatek,mt8195-h
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