Am 26.10.23 um 21:32 schrieb Alex Deucher:
On Thu, Oct 26, 2023 at 1:45 PM Luben Tuikov wrote:
Update the GPU Scheduler maintainer email.
Cc: Alex Deucher
Cc: Christian König
Cc: Daniel Vetter
Cc: Dave Airlie
Cc: AMD Graphics
Cc: Direct Rendering Infrastructure - Development
Signed-off-
On Thu, 26 Oct 2023, Zhanjun Dong wrote:
> gt wedged is fatal error, skip the pxp init on this situation.
More information is needed in the commit message. When do you encounter
this situation?
I'll note that nobody checks intel_pxp_init() return status, so this
silently skips PXP.
BR,
Jani.
>
Hi Danilo,
On Tue, 24 Oct 2023 00:57:47 +0200
Danilo Krummrich wrote:
> > > +
> > > + /**
> > > + * @update_job_credits: Called once the scheduler is considering this
> > > + * job for execution.
> > > + *
> > > + * Drivers may use this to update the job's submission credits, which is
> > >
Hi Danilo,
On Thu, 26 Oct 2023 18:13:00 +0200
Danilo Krummrich wrote:
> +
> + /**
> + * @update_job_credits: Called once the scheduler is considering this
> + * job for execution.
> + *
> + * Drivers may use this to update the job's submission credits, which is
> + *
drm-misc-next-2023-10-27:
drm-misc-next for v6.7-rc1:
drm-misc-next-2023-10-19 + following:
UAPI Changes:
Cross-subsystem Changes:
- Convert fbdev drivers to use fbdev i/o mem helpers.
Core Changes:
- Use cross-references for macros in docs.
- Make drm_client_buffer_addb use addfb2.
- Add NV20
Am 26.10.23 um 18:13 schrieb Danilo Krummrich:
Currently, job flow control is implemented simply by limiting the number
of jobs in flight. Therefore, a scheduler is initialized with a credit
limit that corresponds to the number of jobs which can be sent to the
hardware.
This implies that for
Add panel identification entry for
- AUO B116XTN02 family (product ID:0x235c)
- BOE NT116WHM-N21,836X2 (product ID:0x09c3)
- BOE NV116WHM-N49 V8.0 (product ID:0x0979)
Signed-off-by: Sheng-Liang Pan
---
drivers/gpu/drm/panel/panel-edp.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/driv
On Fri, 27 Oct 2023 09:22:12 +0200
Christian König wrote:
> > +
> > + /**
> > +* @update_job_credits: Called once the scheduler is considering this
> > +* job for execution.
> > +*
> > +* Drivers may use this to update the job's submission credits, which is
> > +* useful to
Am 27.10.23 um 09:32 schrieb Boris Brezillon:
On Fri, 27 Oct 2023 09:22:12 +0200
Christian König wrote:
+
+ /**
+* @update_job_credits: Called once the scheduler is considering this
+* job for execution.
+*
+* Drivers may use this to update the job's submi
On Fri, 27 Oct 2023 09:35:01 +0200
Christian König wrote:
> Am 27.10.23 um 09:32 schrieb Boris Brezillon:
> > On Fri, 27 Oct 2023 09:22:12 +0200
> > Christian König wrote:
> >
> >>> +
> >>> + /**
> >>> + * @update_job_credits: Called once the scheduler is considering this
> >>> + * job for e
Am 27.10.23 um 09:39 schrieb Boris Brezillon:
On Fri, 27 Oct 2023 09:35:01 +0200
Christian König wrote:
Am 27.10.23 um 09:32 schrieb Boris Brezillon:
On Fri, 27 Oct 2023 09:22:12 +0200
Christian König wrote:
+
+ /**
+* @update_job_credits: Called once the scheduler is consi
On Thu, 2023-10-26 at 10:18 +0530, Vijayanand Jitta wrote:
>
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
>
>
> On 10/20/2023 3:29 PM, Yong Wu (吴勇) wrote:
> > On Thu, 2023-10-19 at 10:15 +0530, Vijayanand Jitta wrot
Hi David, Daniel,
On Tue, Oct 24, 2023 at 12:08 PM Geert Uytterhoeven
wrote:
> On Mon, Oct 16, 2023 at 11:59 AM Geert Uytterhoeven
> wrote:
> > The following changes since commit 389af786f92ecdff35883551d54bf4e507ffcccb:
> >
> > Merge tag 'drm-intel-next-2023-09-29' of
> > git://anongit.freede
Hi,
On 21/10/2023 00:52, Javier Martinez Canillas wrote:
Avoid a possible uninitialized use of the crtc_state variable in function
ssd132x_primary_plane_atomic_check() and avoid the following Smatch warn:
drivers/gpu/drm/solomon/ssd130x.c:921 ssd132x_primary_plane_atomic_check()
error
On Fri, 27 Oct 2023 09:44:13 +0200
Christian König wrote:
> Am 27.10.23 um 09:39 schrieb Boris Brezillon:
> > On Fri, 27 Oct 2023 09:35:01 +0200
> > Christian König wrote:
> >
> >> Am 27.10.23 um 09:32 schrieb Boris Brezillon:
> >>> On Fri, 27 Oct 2023 09:22:12 +0200
> >>> Christian König w
Hi Danilo,
On Thu, 26 Oct 2023 18:13:00 +0200
Danilo Krummrich wrote:
> Currently, job flow control is implemented simply by limiting the number
> of jobs in flight. Therefore, a scheduler is initialized with a credit
> limit that corresponds to the number of jobs which can be sent to the
> hard
On 10/26/23 21:25, Alex Goins wrote:
> On Thu, 26 Oct 2023, Sebastian Wick wrote:
>> On Thu, Oct 26, 2023 at 11:57:47AM +0300, Pekka Paalanen wrote:
>>> On Wed, 25 Oct 2023 15:16:08 -0500 (CDT)
>>> Alex Goins wrote:
>>>
Despite being programmable, the LUTs are updated in a manner that is less
Am 27.10.23 um 10:22 schrieb Boris Brezillon:
On Fri, 27 Oct 2023 09:44:13 +0200
Christian König wrote:
Am 27.10.23 um 09:39 schrieb Boris Brezillon:
On Fri, 27 Oct 2023 09:35:01 +0200
Christian König wrote:
Am 27.10.23 um 09:32 schrieb Boris Brezillon:
On Fri, 27 Oct 2023 09:22:12 +02
In order to introduce a pwm api which can be used from atomic context,
we will need two functions for applying pwm changes:
int pwm_apply_cansleep(struct pwm *, struct pwm_state *);
int pwm_apply_atomic(struct pwm *, struct pwm_state *);
This commit just deals with renaming pwm_ap
Rob Herring writes:
> On Sat, 21 Oct 2023 00:30:17 +0200, Javier Martinez Canillas wrote:
>> This is a leftover from when the binding schema had the compatible string
>> property enum as a 'oneOf' child and the '-' was not removed when 'oneOf'
>> got dropped during the binding review process.
>>
Jocelyn Falempe writes:
> Hi,
>
> On 21/10/2023 00:52, Javier Martinez Canillas wrote:
>> Avoid a possible uninitialized use of the crtc_state variable in function
>> ssd132x_primary_plane_atomic_check() and avoid the following Smatch warn:
>>
>> drivers/gpu/drm/solomon/ssd130x.c:921
>> ss
On Thu, Oct 26, 2023 at 09:11:53PM +0200, Frieder Schrempf wrote:
> [You don't often get email from frieder.schre...@kontron.de. Learn why this
> is important at https://aka.ms/LearnAboutSenderIdentification ]
>
> On 26.10.23 13:30, Emil Abildgaard Svendsen wrote:
> > [Sie erhalten nicht häufig E
On Thu, Oct 26, 2023 at 11:49:00AM -0300, Fabio Estevam wrote:
> Hi Emil,
>
> On Thu, Oct 26, 2023 at 11:47 AM Emil Abildgaard Svendsen
> wrote:
> >
> > Currently reading EDID only works because usually only two EDID blocks
> > of 128 bytes is used. Where an EDID segment holds 256 bytes or two ED
On Thu, 26 Oct 2023, Emil Abildgaard Svendsen wrote:
> Currently reading EDID only works because usually only two EDID blocks
> of 128 bytes is used. Where an EDID segment holds 256 bytes or two EDID
> blocks. And the first EDID segment read works fine but E-EDID specifies
> up to 128 segments.
>
On Fri, Oct 27, 2023 at 10:59:25AM +0200, Michel Dänzer wrote:
> On 10/26/23 21:25, Alex Goins wrote:
> > On Thu, 26 Oct 2023, Sebastian Wick wrote:
> >> On Thu, Oct 26, 2023 at 11:57:47AM +0300, Pekka Paalanen wrote:
> >>> On Wed, 25 Oct 2023 15:16:08 -0500 (CDT)
> >>> Alex Goins wrote:
> >>>
> >
Hi Christian,
On Fri, 27 Oct 2023 11:06:44 +0200
Christian König wrote:
> Am 27.10.23 um 10:22 schrieb Boris Brezillon:
> > On Fri, 27 Oct 2023 09:44:13 +0200
> > Christian König wrote:
> >
> >> Am 27.10.23 um 09:39 schrieb Boris Brezillon:
> >>> On Fri, 27 Oct 2023 09:35:01 +0200
> >>> Chr
On 10/26/23 22:44, chentao wrote:
From: Kunwu Chan
There is a typo in the kernel documentation for function
drm_atomic_helper_wait_for_dependencies. Fix it.
Signed-off-by: Kunwu Chan
Applied, thanks!
---
drivers/gpu/drm/drm_atomic_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 d
Since drm_get_format_info() may return NULL, so a judgement of return
value is needed to add.
Signed-off-by: Peng Hao
---
drivers/gpu/drm/drm_framebuffer.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/drm_framebuffer.c
b/drivers/gpu/drm/drm_framebuffer.c
index aff3746
On Fri, 27 Oct 2023 12:01:32 +0200
Sebastian Wick wrote:
> On Fri, Oct 27, 2023 at 10:59:25AM +0200, Michel Dänzer wrote:
> > On 10/26/23 21:25, Alex Goins wrote:
> > > On Thu, 26 Oct 2023, Sebastian Wick wrote:
> > >> On Thu, Oct 26, 2023 at 11:57:47AM +0300, Pekka Paalanen wrote:
> > >>>
The init_imstt() function calls framebuffer_release() on error and then
the probe() function calls it again. It should only be done in probe.
Fixes: 518ecb6a209f ("fbdev: imsttfb: Fix error path of imsttfb_probe()")
Signed-off-by: Dan Carpenter
---
drivers/video/fbdev/imsttfb.c | 6 +-
1 fi
I've re-written the error handling but the bug is that if init_imstt()
fails we need to call iounmap(par->cmap_regs).
Fixes: c75f5a550610 ("fbdev: imsttfb: Fix use after free bug in imsttfb_probe")
Signed-off-by: Dan Carpenter
---
drivers/video/fbdev/imsttfb.c | 29 -
On Tue, Oct 24, 2023 at 01:22:17PM +0300, Imre Deak wrote:
> Add helpers drivers can use to calculate the BW allocation overhead -
> due to SSC, FEC, DSC and data alignment on symbol cycles - and the
> channel coding efficiency - due to the 8b/10b, 128b/132b encoding. On
> 128b/132b links the FEC o
Currently reading EDID only works because usually only two EDID blocks
of 128 bytes is used. Where an EDID segment holds 256 bytes or two EDID
blocks. And the first EDID segment read works fine but E-EDID specifies
up to 128 segments.
The logic is broken so change EDID segment index to multiple of
Change check of DDC status. Instead of silently not reading EDID when in
"IDLE" state [1]. Always read EDID but add a debug log when DDC
controller is in reset.
[1]
ADV7511 Programming Guide: Table 11: DDCController Status:
0xC8 [3:0] DDC Controller State
In Reset (No Hot Plug D
Hi Doug,
Many thanks for your reply.
> Hi,
>
> On Thu, Oct 26, 2023 at 7:37 AM Jonas Mark (BT-FS/ENG1-GRB)
> wrote:
> >
> > Hi,
> >
> > We have a parallel LCD panel which is driven by panel/panel-simple.
> The power-off sequence specified in the datasheet requires that the
> enable-gpio must be
On Fri, Oct 27, 2023 at 05:19:12PM +0800, Peng Hao wrote:
> Since drm_get_format_info() may return NULL,
Not in this case since we already checked it earlier.
> so a judgement of return
> value is needed to add.
>
> Signed-off-by: Peng Hao
> ---
> drivers/gpu/drm/drm_framebuffer.c | 4
>
Am Fr., 27. Okt. 2023 um 12:01 Uhr schrieb Sebastian Wick <
sebastian.w...@redhat.com>:
> On Fri, Oct 27, 2023 at 10:59:25AM +0200, Michel Dänzer wrote:
> > On 10/26/23 21:25, Alex Goins wrote:
> > > On Thu, 26 Oct 2023, Sebastian Wick wrote:
> > >> On Thu, Oct 26, 2023 at 11:57:47AM +0300, Pekka
On Fri, Oct 27, 2023 at 12:51:07PM +0300, Jani Nikula wrote:
> On Thu, 26 Oct 2023, Emil Abildgaard Svendsen wrote:
> > Currently reading EDID only works because usually only two EDID blocks
> > of 128 bytes is used. Where an EDID segment holds 256 bytes or two EDID
> > blocks. And the first EDID
On 25/10/2023 09:34, Neil Armstrong wrote:
> Document the DSI PHY on the SM8650 Platform.
>
> Signed-off-by: Neil Armstrong
Reviewed-by: Krzysztof Kozlowski
Best regards,
Krzysztof
On 25/10/2023 09:35, Neil Armstrong wrote:
> Document the DSI Controller on the SM8650 Platform.
>
> Signed-off-by: Neil Armstrong
Reviewed-by: Krzysztof Kozlowski
Best regards,
Krzysztof
On 25/10/2023 09:35, Neil Armstrong wrote:
> Document the DPU Display Controller on the SM8650 Platform.
>
> Signed-off-by: Neil Armstrong
> ---
Reviewed-by: Krzysztof Kozlowski
Best regards,
Krzysztof
On 25/10/2023 09:35, Neil Armstrong wrote:
> Document the Mobile Display Subsystem (MDSS) on the SM8650 Platform.
>
> Signed-off-by: Neil Armstrong
> ---
> .../bindings/display/msm/qcom,sm8650-mdss.yaml | 322
> +
> 1 file changed, 322 insertions(+)
>
Reviewed-by: Krzy
I'm afraid that would not be very useful. It indeed depends on the refresh
rate, but also on how close to vblank the compositor does its commits / on
what the latency requirements for the currently shown content are.
When the compositor presents a fullscreen video with frames that are queued
up in
On Fri, Oct 20, 2023 at 05:11:24PM +0300, Dan Carpenter wrote:
> On Fri, Oct 20, 2023 at 02:55:37PM +0300, Ville Syrjälä wrote:
> > On Fri, Oct 20, 2023 at 02:39:04PM +0300, Dan Carpenter wrote:
> > > On Wed, Oct 18, 2023 at 05:17:42PM +0300, Dan Carpenter wrote:
> > > > drivers/gpu/drm/drm_rect.c
When i915 perf interface is not available dereferencing it will lead to
NULL dereferences.
Fix this by using DRM_DEBUG() which the scenario before the commit in
the Fixes tag.
Fixes: 2fec539112e8 ("i915/perf: Replace DRM_DEBUG with driver specific drm_dbg
call")
Signed-off-by: Harshit Mogalapall
Add helpers drivers can use to calculate the BW allocation overhead -
due to SSC, FEC, DSC and data alignment on symbol cycles - and the
channel coding efficiency - due to the 8b/10b, 128b/132b encoding. On
128b/132b links the FEC overhead is part of the coding efficiency, so
not accounted for in t
On 27.10.2023 16:07, Harshit Mogalapalli wrote:
When i915 perf interface is not available dereferencing it will lead to
NULL dereferences.
Fix this by using DRM_DEBUG() which the scenario before the commit in
the Fixes tag.
Fixes: 2fec539112e8 ("i915/perf: Replace DRM_DEBUG with driver speci
Reviewed-by: Simon Ser
Have you seen the comment on top?
* Atomic drivers should never call this function directly, the core will read
* out property values through the various ->atomic_get_property callbacks.
It seems like atomic drivers shouldn't call drm_object_property_get_value()
at all?
On Thursday, October 19th, 2023 at 23:21, Harry Wentland
wrote:
> +++ b/drivers/gpu/drm/vkms/Kconfig
> @@ -0,0 +1,15 @@
> +# SPDX-License-Identifier: GPL-2.0+
It seems like the original Kconfig uses GPL-2.0-only. I think it'd be
safer to just re-use the exact same license here?
With that fixed
On 10/24/2023 10:53 AM, Stanislaw Gruszka wrote:
From: Jacek Lawrynowicz
IP reset has to followed by ivpu_pll_disable() to properly enter
reset state.
Fixes: 828d63042aec ("accel/ivpu: Don't enter d0i3 during FLR")
Cc: sta...@vger.kernel.org
Signed-off-by: Jacek Lawrynowicz
Reviewed-by: Stani
On 10/27/23 10:25, Boris Brezillon wrote:
Hi Danilo,
On Thu, 26 Oct 2023 18:13:00 +0200
Danilo Krummrich wrote:
Currently, job flow control is implemented simply by limiting the number
of jobs in flight. Therefore, a scheduler is initialized with a credit
limit that corresponds to the number
Hi,
On Fri, Oct 27, 2023 at 5:30 AM Jonas Mark (BT-FS/ENG1-GRB)
wrote:
>
> > I think I've looked at this exact case before and then realized that
> > there's a better solution. At least in all cases I looked at the
> > "enable-gpio" you're talking about was actually better modeled as a
> > _backl
On 2023-10-27 04:25, Boris Brezillon wrote:
> Hi Danilo,
>
> On Thu, 26 Oct 2023 18:13:00 +0200
> Danilo Krummrich wrote:
>
>> Currently, job flow control is implemented simply by limiting the number
>> of jobs in flight. Therefore, a scheduler is initialized with a credit
>> limit that correspo
On 10/27/23 09:17, Boris Brezillon wrote:
Hi Danilo,
On Thu, 26 Oct 2023 18:13:00 +0200
Danilo Krummrich wrote:
+
+ /**
+* @update_job_credits: Called once the scheduler is considering this
+* job for execution.
+*
+* Drivers may use this to update the jo
On 10/25/2023 3:43 AM, Stanislaw Gruszka wrote:
From: Krystian Pradzynski
Bump boot API to 4.20
Bump JSM API to 3.15
Signed-off-by: Krystian Pradzynski
Reviewed-by: Stanislaw Gruszka
Signed-off-by: Stanislaw Gruszka
---
drivers/accel/ivpu/ivpu_jsm_msg.c | 17 ++
drivers/accel/ivpu/vpu_b
$SUBJECT has a spelling error of "declaration"
On 10/25/2023 3:43 AM, Stanislaw Gruszka wrote:
Cleanup drm_driver declaration leftover.
Reviewed-by: Krystian Pradzynski
Signed-off-by: Stanislaw Gruszka
Reviewed-by: Jeffrey Hugo
On 10/25/2023 3:43 AM, Stanislaw Gruszka wrote:
From: Tomasz Rusinowicz
Add new debugfs file to set dvfs_mode FW boot parameter and restart
the FW to allow experimenting with DVFS (dynamic voltage & frequency
scaling).
Signed-off-by: Tomasz Rusinowicz
Signed-off-by: Stanislaw Gruszka
Revie
On 10/25/2023 3:43 AM, Stanislaw Gruszka wrote:
From: Karol Wachowski
Setting a non-zero work point resets the IP hence IP_RESET
trigger is redundant.
Signed-off-by: Karol Wachowski
Reviewed-by: Stanislaw Gruszka
Signed-off-by: Stanislaw Gruszka
Reviewed-by: Jeffrey Hugo
On 10/25/2023 3:43 AM, Stanislaw Gruszka wrote:
From: Andrzej Kacprowski
Add test_mode = 3 that add VPU_JOB_FLAGS_NULL_SUBMISSION_MASK
flag to the job send to the VPU device. Then the VPU will process
the job but won't execute commands (except the command to signal
the fence).
This can b used
Hi Luben,
On 10/26/23 23:13, Luben Tuikov wrote:
On 2023-10-26 12:13, Danilo Krummrich wrote:
Currently, job flow control is implemented simply by limiting the number
of jobs in flight. Therefore, a scheduler is initialized with a credit
limit that corresponds to the number of jobs which can be
On 10/25/2023 3:43 AM, Stanislaw Gruszka wrote:
From: Karol Wachowski
Change meaning of test_mode module parameter from integer value
to bitmask allowing setting different test features with corresponding
bits.
Signed-off-by: Karol Wachowski
Reviewed-by: Stanislaw Gruszka
Signed-off-by: Stan
On 10/27/23 03:03, Luben Tuikov wrote:
On 2023-10-26 17:13, Luben Tuikov wrote:
On 2023-10-26 12:13, Danilo Krummrich wrote:
Currently, job flow control is implemented simply by limiting the number
of jobs in flight. Therefore, a scheduler is initialized with a credit
limit that corresponds to
On 27/10/2023 15:11, Andrzej Hajda wrote:
On 27.10.2023 16:07, Harshit Mogalapalli wrote:
When i915 perf interface is not available dereferencing it will lead to
NULL dereferences.
Fix this by using DRM_DEBUG() which the scenario before the commit in
the Fixes tag.
Fixes: 2fec539112e8 ("i915
On 10/25/2023 3:43 AM, Stanislaw Gruszka wrote:
From: Karol Wachowski
Split ivpu_ipc_send_receive() implementation to have a version
that does not call pm_runtime_resume_and_get(). That implementation
can be invoked when device is up and runtime resume is prohibited
(for example at the end of b
On 10/25/2023 3:43 AM, Stanislaw Gruszka wrote:
From: Andrzej Kacprowski
The firmware needs to know the time spend in D0i3/D3 to
spent?
calculate telemetry data. The D0i3/D3 residency time is
calculated by the driver and passed to the firmware
in the boot parameters.
The driver also passes
Hi Danilo,
On 2023-10-27 10:45, Danilo Krummrich wrote:
> Hi Luben,
>
> On 10/26/23 23:13, Luben Tuikov wrote:
>> On 2023-10-26 12:13, Danilo Krummrich wrote:
>>> Currently, job flow control is implemented simply by limiting the number
>>> of jobs in flight. Therefore, a scheduler is initialized
On 10/25/2023 3:43 AM, Stanislaw Gruszka wrote:
From: Andrzej Kacprowski
The driver needs to capture the D0i3 entry timestamp to
calculate D0i3 residency time.
The D0i3 residency time and the VPU timestamp are passed
to the firmware at D0i3 exit (warm boot).
Signed-off-by: Andrzej Kacprowski
On 10/27/23 16:59, Luben Tuikov wrote:
Hi Danilo,
On 2023-10-27 10:45, Danilo Krummrich wrote:
Hi Luben,
On 10/26/23 23:13, Luben Tuikov wrote:
On 2023-10-26 12:13, Danilo Krummrich wrote:
Currently, job flow control is implemented simply by limiting the number
of jobs in flight. Therefore,
On 10/25/2023 3:43 AM, Stanislaw Gruszka wrote:
From: Andrzej Kacprowski
Currently the VPU firmware prepares for D0i3 every time the VPU
is entering D0i2 Idle state. This is not optimal as we might not
enter D0i3 every time we enter D0i2 Idle and this preparation
is quite costly.
This optimiza
On 10/25/2023 3:43 AM, Stanislaw Gruszka wrote:
From: Andrzej Kacprowski
The VPU needs non zero time to enter IDLE state after responding to
D0i3 entry message. If the driver does not wait for the VPU to enter
IDLE state it could cause warm boot failures.
Signed-off-by: Andrzej Kacprowski
Rev
From: Arnd Bergmann
The usage count of struct dev_pm_info is an implementation detail that
is only available if CONFIG_PM is enabled, so printing it in a debug message
causes a build failure in configurations without PM:
In file included from include/linux/device.h:15,
from incl
On 10/16/2023 11:00 AM, Jeffrey Hugo wrote:
From: Carl Vanderlip
Several virtualization use-cases either don't support 32 MultiMSIs
(Xen/VMware) or have significant drawbacks to their use (KVM's vIOMMU,
which is required to support 32 MSI, needs to allocate an alternate
system memory space for
Add support for drawing the SMPTE and tiles test patterns in buffers
using big-endian formats.
For now this is limited to XRGB1555 and RGB565, which are the most
common big-endian formats.
Signed-off-by: Geert Uytterhoeven
---
v4:
- No changes,
v3:
- Increase indentation after definition of
DRM formats are defined to be little-endian, unless the
DRM_FORMAT_BIG_ENDIAN flag is set. Hence writes of multi-byte pixel
values need to take endianness into account.
Introduce a swap32() helper to byteswap 32-bit values, and a
cpu_to_le32() helper to convert 32-bit values from CPU-endian to
li
When specifying a frame buffer format like "RG16_BE" (big-endian RG16),
modetest still uses the little-endian variant, as the format string is
truncated to four characters.
Fix this by increasing the format string size to 8 bytes (7 characters +
NUL terminator).
Signed-off-by: Geert Uytterhoeven
Add support for creating buffers using big-endian formats.
For now this is limited to XRGB1555 and RGB565, which are the most
common big-endian formats.
Signed-off-by: Geert Uytterhoeven
---
v4:
- No changes,
v3:
- No changes,
v2:
- New.
---
tests/modetest/buffers.c | 4
1 file cha
Cairo always uses native byte order for rendering.
Hence if the byte order of the frame buffer differs from the byte order
of the CPU, the frame buffer contents need to be byteswapped twice: once
before rendering, to convert to native byte order, and a second time
after rendering, to restore the f
Add support for rendering the crosshairs in a buffer using the
big-endian RGB565 format.
Signed-off-by: Geert Uytterhoeven
---
v4:
- No changes,
v3:
- No changes,
v2:
- New.
---
tests/util/pattern.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/util/pattern.c b/tests/util/pat
DRM formats are defined to be little-endian, unless the
DRM_FORMAT_BIG_ENDIAN flag is set. Hence writes of multi-byte pixel
values need to take endianness into account.
Introduce a swap16() helper to byteswap 16-bit values, and a
cpu_to_le16() helper to convert 16-bit values from CPU-endian to
li
Signed-off-by: Geert Uytterhoeven
---
v4:
- No changes,
v3:
- Update for suffix change from "be" to "_BE", cfr. commit
ffb9375a505700ad ("xf86drm: handle DRM_FORMAT_BIG_ENDIAN in
drmGetFormatName()"),
v2:
- New.
---
tests/util/format.c | 3 +++
1 file changed, 3 insertions(+)
dif
Hi all,
This patch series fixes some endianness issues in libdrm.
It has been tested on ARAnyM using a work-in-progress Atari DRM driver.
After this, the smpte and tiles modetest patterns and the pwetty markers
are rendered correctly using the XR24, RG16, and RG16BE formats on
big-endian s
The endianness of the target is currently determined based on
preprocessor symbols. Unfortunately some symbols checked are wrong
(sparc64-linux-gnu-gcc does not define __BIG_ENDIAN__ or SPARC), and
several checks for big-endian architectures are missing.
Fix this by introducing a new preprocessor
On Tue, Oct 24, 2023 at 01:22:17PM +0300, Imre Deak wrote:
> Add helpers drivers can use to calculate the BW allocation overhead -
> due to SSC, FEC, DSC and data alignment on symbol cycles - and the
> channel coding efficiency - due to the 8b/10b, 128b/132b encoding. On
> 128b/132b links the FEC o
[AMD Official Use Only - General]
Thanks,
Reviewed-by: Bhawanpreet Lakha
From: Yuran Pereira
Sent: October 26, 2023 5:25 PM
To: airl...@gmail.com
Cc: Yuran Pereira ; Wentland, Harry
; Li, Sun peng (Leo) ; Siqueira,
Rodrigo ; Deucher, Alexander
; Koenig, Chr
On 10/26/23 17:25, Yuran Pereira wrote:
Since `pr_config` is not initialized after its declaration, the
following operations with `replay_enable_option` may be performed
when `replay_enable_option` is holding junk values which could
possibly lead to undefined behaviour
```
...
pr_confi
Also, please write the tagline in present tense.
On 10/27/23 11:53, Hamza Mahfooz wrote:
On 10/26/23 17:25, Yuran Pereira wrote:
Since `pr_config` is not initialized after its declaration, the
following operations with `replay_enable_option` may be performed
when `replay_enable_option` is holdin
[AMD Official Use Only - General]
There was a consensus to use memset instead of {0}. I remember making changes
related to that previously.
Bhawan
From: Mahfooz, Hamza
Sent: October 27, 2023 11:53 AM
To: Yuran Pereira ; airl...@gmail.com
Cc: Li, Sun peng (Le
On 10/22/2023 5:06 AM, Stanislaw Gruszka wrote:
On Mon, Oct 16, 2023 at 11:01:13AM -0600, Jeffrey Hugo wrote:
From: Ajit Pal Singh
Device and Host have a time synchronization mechanism that happens once
during boot when device is in SBL mode. After that, in mission-mode there
is no timesync. I
On 10/27/23 11:55, Lakha, Bhawanpreet wrote:
[AMD Official Use Only - General]
There was a consensus to use memset instead of {0}. I remember making
changes related to that previously.
Hm, seems like it's used rather consistently in the DM and in DC
though.
Bhawan
--
On 10/16/2023 11:01 AM, Jeffrey Hugo wrote:
AIC100 supports a timesync mechanism that allows AIC100 to timestamp
device logs with a host based time. This becomes useful for putting host
logs in a unified timeline with device logs for debugging and performance
profiling. The mechanism consists of
On Fri, 27 Oct 2023 16:34:26 +0200
Danilo Krummrich wrote:
> On 10/27/23 09:17, Boris Brezillon wrote:
> > Hi Danilo,
> >
> > On Thu, 26 Oct 2023 18:13:00 +0200
> > Danilo Krummrich wrote:
> >
> >> +
> >> + /**
> >> + * @update_job_credits: Called once the scheduler is considering this
>
On Fri, 27 Oct 2023 16:23:24 +0200
Danilo Krummrich wrote:
> On 10/27/23 10:25, Boris Brezillon wrote:
> > Hi Danilo,
> >
> > On Thu, 26 Oct 2023 18:13:00 +0200
> > Danilo Krummrich wrote:
> >
> >> Currently, job flow control is implemented simply by limiting the number
> >> of jobs in fligh
Sequential DMA bursts improve NIC/RAM usage thanks to the basic NIC
hardware optimizations available when performing in-order sequential
accesses. This can be further enforced with the IPU DMA locking
mechanism which basically prevents any other IP to access the
interconnect for a longer time while
On Fri, Oct 27, 2023 at 06:48:44PM +0300, Ville Syrjälä wrote:
> On Tue, Oct 24, 2023 at 01:22:17PM +0300, Imre Deak wrote:
> > Add helpers drivers can use to calculate the BW allocation overhead -
> > due to SSC, FEC, DSC and data alignment on symbol cycles - and the
> > channel coding efficiency
On Fri, 27 Oct 2023 10:32:52 -0400
Luben Tuikov wrote:
> On 2023-10-27 04:25, Boris Brezillon wrote:
> > Hi Danilo,
> >
> > On Thu, 26 Oct 2023 18:13:00 +0200
> > Danilo Krummrich wrote:
> >
> >> Currently, job flow control is implemented simply by limiting the number
> >> of jobs in flight.
From: Pranjal Ramajor Asha Kanojiya
Add support to partially execute a slice which is resized to zero.
Executing a zero size slice in a BO should mean that there is no DMA
transfers involved but you should still configure doorbell and semaphores.
For example consider a BO of size 18K and it is s
Hi,
On Thu, Oct 26, 2023 at 8:05 PM Sheng-Liang Pan
wrote:
>
> Add panel identification entry for
> - AUO B116XTN02 family (product ID:0x235c)
> - BOE NT116WHM-N21,836X2 (product ID:0x09c3)
> - BOE NV116WHM-N49 V8.0 (product ID:0x0979)
>
> Signed-off-by: Sheng-Liang Pan
>
> ---
>
> drivers/gpu
From: Rob Clark
Simplify the exec path (removing a legacy optimization) and convert to
drm_exec. One drm_exec patch to allow passing in the expected # of GEM
objects to avoid re-allocation.
I'd be a bit happier if I could avoid the extra objects table allocation
in drm_exec in the first place,
From: Rob Clark
This was a small optimization for pre-soft-pin userspace. But mesa
switched to soft-pin nearly 5yrs ago. So lets drop the optimization
and simplify the code.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_gem.h| 2 --
drivers/gpu/drm/msm/msm_gem_submit.c | 44 +
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