[PATCH 02/22] drm: Create Color Management query properties

DRM color management is written to extract the color correction capabilities of various platforms, and every platform can showcase its capabilities using the query properties. Different hardwares can have different no of coefficients for palette correction. Also the correction can be applied after

[PATCH 00/22] Color Management for DRM

This patch set adds Color Manager implementation in DRM layer. Color Manager is an extension in DRM framework to support color correction/enhancement. Various Hardware platforms can support several color correction capabilities. Color Manager provides abstraction of these capabilities and allows a

[PATCH 03/22] drm: Add color correction blobs in CRTC state

This patch adds new variables in CRTC state, to hold respective color correction blobs. These blobs will be required during the atomic commit for writing the color correction values in correction registers. Signed-off-by: Shashank Sharma Signed-off-by: Kausal Malladi --- drivers/gpu/drm/drm_ato

[PATCH 01/22] drm: Create Color Management DRM properties

Color Management is an extension to DRM framework. It allows abstraction of hardware color correction and enhancement capabilities by virtue of DRM properties. There are two major types of color correction supported by DRM color manager: - CTM: color transformation matrix, properties where a corre

[PATCH 04/22] drm: Add set property support for color manager

As per DRM color manager design, if a userspace wants to set a correction blob, it prepares it and sends the blob_id to kernel via set_property call. DRM framework takes this blob_id, gets the blob, and saves it in the CRTC state, so that, during the atomic_commit, the color correction values from

[PATCH 05/22] drm: Add get property support for color manager

As per the DRM get_property implementation for a blob, framework is supposed to return the blob_id to the caller. All the color management blobs are saved in CRTC state during the set call. This patch adds get_property support for color management properties, by referring to the existing blob for

[PATCH 06/22] drm: Add drm structures for palette color property

This patch adds new structures in DRM layer for Palette color correction.These structures will be used by user space agents to configure appropriate number of samples and Palette LUT for a platform. Signed-off-by: Shashank Sharma Signed-off-by: Kausal Malladi --- include/uapi/drm/drm.h | 26 +++

[PATCH 07/22] drm: Add structure to set/get a CTM color property

Color Manager framework defines a DRM property for color space transformation and Gamut mapping. This property is called CTM (Color Transformation Matrix). This patch adds a new structure in DRM layer for CTM. This structure can be used by all user space agents to configure CTM coefficients for co

[PATCH 08/22] drm/i915: Add set property interface for CRTC

This patch adds set property interface for intel CRTC. This interface will be used for set operation on any DRM properties. Signed-off-by: Shashank Sharma Signed-off-by: Kausal Malladi --- drivers/gpu/drm/i915/intel_display.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i

[PATCH 09/22] drm/i915: Create color management files

This patch create new files intel_color_manager.c which will contain the core color correction code for I915 driver and its header intel_color_manager.h The per color property patches coming up in this patch series will fill the appropriate functions in this file. Signed-off-by: Shashank Sharma

[PATCH 10/22] drm/i915: Register color correction capabilities

>From DRM color management: DRM color manager supports these color properties: 1. "ctm": Color transformation matrix property, where a color transformation matrix of 9 correction values gets applied as correction. 2. "palette_before_ctm": for corrections which get

[PATCH 11/22] drm/i915: CHV: Load gamma color correction values

DRM color manager allows the driver to showcase its best color correction capabilities using the specific query property cm_coeff_after_ctm_property. The driver must loads the no. of coefficients for color correction as per the platform capability during the init time. This patch adds no of coeffi

[PATCH 12/22] drm/i915: CHV: Load degamma color correction values

DRM color manager allows the driver to showcase its best color correction capabilities using the specific query property cm_coeff_before_ctm_property. The driver must loads the no. of coefficients for color correction as per the platform capability during the init time. This patch adds no of coeff

[PATCH 13/22] drm/i915: CHV: Pipe level Gamma correction

CHV/BSW platform supports two different pipe level gamma correction modes, which are: 1. Legacy 8-bit mode 2. 10-bit CGM (Color Gamut Mapping) mode This patch does the following: 1. Attaches Gamma property to CRTC 3. Adds the core Gamma correction function for CHV/BSW 4. Adds Gamma correction macr

[PATCH 14/22] drm/i915: CHV: Pipe level degamma correction

CHV/BSW supports Degamma color correction, which linearizes all the non-linear color values. This will be applied before Color Transformation. This patch does the following: 1. Attach deGamma property to CRTC 2. Add the core function to program DeGamma correction values for CHV/BSW platform 2.

[PATCH 15/22] drm/i915: CHV: Pipe level CSC correction

CHV/BSW supports Color Space Conversion (CSC) using a 3x3 matrix that needs to be programmed into CGM (Color Gamut Mapping) registers. This patch does the following: 1. Attaches CSC property to CRTC 2. Adds the core function to program CSC correction values 3. Adds CSC correction macros Signed-of

[PATCH 16/22] drm/i915: Commit color correction to CRTC

The color correction blob values are loaded during set_property calls. This patch adds a function to find the blob and apply the correction values to the display registers, during the atomic commit call. Signed-off-by: Shashank Sharma Signed-off-by: Kausal Malladi --- drivers/gpu/drm/i915/intel

[PATCH 17/22] drm/i915: Attach color properties to CRTC

Function intel_attach_color_properties_to_crtc attaches a color property to its CRTC object. This patch calls this function from crtc initialization sequence. Signed-off-by: Shashank Sharma Signed-off-by: Kausal Malladi --- drivers/gpu/drm/i915/intel_display.c | 1 + drivers/gpu/drm/i915/intel_

[PATCH 18/22] drm/i915: BDW: Load gamma correction values

I915 color manager registers pipe gamma correction as palette correction after CTM property. For BDW and higher platforms, split gamma correction is the best gamma correction. This patch adds the no of coefficients(512) for split gamma correction as "num_samples_after_ctm" parameter in device info

[PATCH 19/22] drm/i915: BDW: Pipe level Gamma correction

BDW/SKL/BXT platforms support various Gamma correction modes which are: 1. Legacy 8-bit mode 2. 10-bit Split Gamma mode 3. 12-bit mode This patch does the following: 1. Adds the core function to program Gamma correction values for BDW/SKL/BXT platforms 2. Adds Gamma correction macros/defines S

[PATCH 20/22] drm/i915: BDW: Load degamma correction values

I915 color manager registers pipe degamma correction as palette correction before CTM, DRM property. This patch adds the no of coefficients(65) for degamma correction as "num_samples_before_ctm" parameter in device info structures, for BDW and higher platforms. Signed-off-by: Shashank Sharma Sig

[PATCH 21/22] drm/i915: BDW: Pipe level degamma correction

BDW/SKL/BXT supports Degamma color correction feature, which linearizes the non-linearity due to gamma encoded color values. This will be applied before Color Transformation. This patch does the following: 1. Adds the core function to program DeGamma correction values for BDW/SKL/BXT platform 2

[PATCH 22/22] drm/i915: BDW: Pipe level CSC correction

BDW/SKL/BXT support Color Space Conversion (CSC) using a 3x3 matrix that needs to be programmed into respective CSC registers. This patch does the following: 1. Adds the core function to program CSC correction values for BDW/SKL/BXT platform 2. Adds CSC correction macros/defines Signed-off-by:

[Intel-gfx] [PATCH 01/22] drm: Create Color Management DRM properties

7-22 1158 62f2104f Keith Packard 2013-07-22 1159 /* whether async page flip is supported or not */ 62f2104f Keith Packard 2013-07-22 1160 bool async_page_flip; 8716ed4e Alex Deucher 2014-02-12 1161 e3eb3250 Rob Clark 2015-02-05 1162 /* whether the driver supports fb modifiers */ e3eb3250 Rob Clark 2015-02-05 1163 bool allow_fb_modifiers; e3eb3250 Rob Clark 2015-02-05 1164 8716ed4e Alex Deucher2014-02-12 1165 /* cursor size */ 8716ed4e Alex Deucher2014-02-12 1166 uint32_t cursor_width, cursor_height; f453ba04 Dave Airlie 2008-11-07 @1167 }; f453ba04 Dave Airlie 2008-11-07 1168 dd275956 Rob Clark 2014-11-25 1169 /** dd275956 Rob Clark 2014-11-25 1170 * drm_for_each_plane_mask - iterate over planes specified by bitmask dd275956 Rob Clark 2014-11-25 1171 * @plane: the loop cursor dd275956 Rob Clark 2014-11-25 1172 * @dev: the DRM device dd275956 Rob Clark 2014-11-25 1173 * @plane_mask: bitmask of plane indices dd275956 Rob Clark 2014-11-25 1174 * dd275956 Rob Clark 2014-11-25 1175 * Iterate over all planes specified by bitmask. :: The code at line 1167 was first introduced by commit :: f453ba0460742ad027ae0c4c7d61e62817b3e7ef DRM: add mode setting support :: TO: Dave Airlie :: CC: Dave Airlie --- 0-DAY kernel test infrastructureOpen Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation -- next part -- A non-text attachment was scrubbed... Name: .config.gz Type: application/octet-stream Size: 6144 bytes Desc: not available URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20151010/0cb74201/attachment-0001.obj>

[Intel-gfx] [PATCH 02/22] drm: Create Color Management query properties

kard 2013-07-22 1164 bool async_page_flip; 8716ed4e Alex Deucher 2014-02-12 1165 e3eb3250 Rob Clark 2015-02-05 1166 /* whether the driver supports fb modifiers */ e3eb3250 Rob Clark 2015-02-05 1167 bool allow_fb_modifiers; e3eb3250 Rob Clark 2015-02-05 1168 8716ed4e Alex Deucher2014-02-12 1169 /* cursor size */ 8716ed4e Alex Deucher2014-02-12 1170 uint32_t cursor_width, cursor_height; f453ba04 Dave Airlie 2008-11-07 @1171 }; f453ba04 Dave Airlie 2008-11-07 1172 dd275956 Rob Clark 2014-11-25 1173 /** dd275956 Rob Clark 2014-11-25 1174 * drm_for_each_plane_mask - iterate over planes specified by bitmask dd275956 Rob Clark 2014-11-25 1175 * @plane: the loop cursor dd275956 Rob Clark 2014-11-25 1176 * @dev: the DRM device dd275956 Rob Clark 2014-11-25 1177 * @plane_mask: bitmask of plane indices dd275956 Rob Clark 2014-11-25 1178 * dd275956 Rob Clark 2014-11-25 1179 * Iterate over all planes specified by bitmask. :: The code at line 1171 was first introduced by commit :: f453ba0460742ad027ae0c4c7d61e62817b3e7ef DRM: add mode setting support :: TO: Dave Airlie :: CC: Dave Airlie --- 0-DAY kernel test infrastructureOpen Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation -- next part -- A non-text attachment was scrubbed... Name: .config.gz Type: application/octet-stream Size: 6144 bytes Desc: not available URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20151010/d716a370/attachment-0001.obj>

[Intel-gfx] [PATCH 03/22] drm: Add color correction blobs in CRTC state

f453ba04 Dave Airlie2008-11-07 317 /** 3bf0401c Daniel Vetter 2014-10-27 318 * struct drm_crtc_funcs - control CRTCs for a given device f453ba04 Dave Airlie2008-11-07 319 * @save: save CRTC state 3b02ab88 Laurent Pinchart 2012-05-17 320 * @restore: restore CRTC state 715f59cc Christopher Harvey 2013-04-05 321 * @reset: reset CRTC after state has been invalidated (e.g. resume) 3b02ab88 Laurent Pinchart 2012-05-17 322 * @cursor_set: setup the cursor 2c0c33d4 Daniel Vetter 2014-10-27 323 * @cursor_set2: setup the cursor with hotspot, superseeds @cursor_set if set :: The code at line 315 was first introduced by commit :: 144ecb97cd57d2a61cc455730a3337e413499cae drm: Add atomic driver interface definitions for objects :: TO: Daniel Vetter :: CC: Daniel Vetter --- 0-DAY kernel test infrastructureOpen Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation -- next part -- A non-text attachment was scrubbed... Name: .config.gz Type: application/octet-stream Size: 6144 bytes Desc: not available URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20151010/28c25e4b/attachment.obj>

[Intel-gfx] [PATCH 04/22] drm: Add set property support for color manager

call 396 * 397 * Set a color correction blob (originating from a set blob property) on the 398 * desired CRTC state. This function will take reference of the blob property 399 * in the CRTC state, finds the blob based on blob_id (which comes from 400 * set_property call) and set the blob at the proper place. 401 * 402 * RETURNS: 403 * Zero on success, error code on failure. 404 */ 405 int drm_atomic_crtc_set_blob(struct drm_device *dev, 406 struct drm_property_blob **state_blob, uint32_t blob_id) > 407 { 408 struct drm_property_blob *blob; 409 410 blob = drm_property_lookup_blob(dev, blob_id); 411 if (!blob) { 412 DRM_DEBUG_KMS("Invalid Blob ID\n"); 413 return -EINVAL; 414 } 415 --- 0-DAY kernel test infrastructureOpen Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation -- next part -- A non-text attachment was scrubbed... Name: .config.gz Type: application/octet-stream Size: 6144 bytes Desc: not available URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20151010/7bcd19eb/attachment-0001.obj>

[PATCH 13/22] drm/i915: CHV: Pipe level Gamma correction

Hi Shashank, On 9 October 2015 at 20:29, Shashank Sharma wrote: > CHV/BSW platform supports two different pipe level gamma > correction modes, which are: > 1. Legacy 8-bit mode > 2. 10-bit CGM (Color Gamut Mapping) mode > > This patch does the following: > 1. Attaches Gamma property to CRTC > 3.

[PATCH 14/22] drm/i915: CHV: Pipe level degamma correction

Hi Shashank, On 9 October 2015 at 20:29, Shashank Sharma wrote: > CHV/BSW supports Degamma color correction, which linearizes all > the non-linear color values. This will be applied before Color > Transformation. > > This patch does the following: > 1. Attach deGamma property to CRTC > 2. Add th

[PATCH 16/22] drm/i915: Commit color correction to CRTC

Hi Shashank, On 9 October 2015 at 20:29, Shashank Sharma wrote: > The color correction blob values are loaded during set_property > calls. This patch adds a function to find the blob and apply the > correction values to the display registers, during the atomic > commit call. > > Signed-off-by: S

[PATCH 19/22] drm/i915: BDW: Pipe level Gamma correction

Hi Shashank, On 9 October 2015 at 20:29, Shashank Sharma wrote: [snip] > diff --git a/drivers/gpu/drm/i915/intel_color_manager.c > b/drivers/gpu/drm/i915/intel_color_manager.c > index d5315b2..74f8fc3 100644 > --- a/drivers/gpu/drm/i915/intel_color_manager.c > +++ b/drivers/gpu/drm/i915/intel_c

[PATCH 15/22] drm/i915: CHV: Pipe level CSC correction

On 9 October 2015 at 20:29, Shashank Sharma wrote: > CHV/BSW supports Color Space Conversion (CSC) using a 3x3 matrix > that needs to be programmed into CGM (Color Gamut Mapping) registers. > > This patch does the following: > 1. Attaches CSC property to CRTC > 2. Adds the core function to progra

[PATCH 17/22] drm/i915: Attach color properties to CRTC

On 9 October 2015 at 20:29, Shashank Sharma wrote: > Function intel_attach_color_properties_to_crtc attaches a > color property to its CRTC object. This patch calls this > function from crtc initialization sequence. > > Signed-off-by: Shashank Sharma > Signed-off-by: Kausal Malladi Maybe squash

[PATCH 21/22] drm/i915: BDW: Pipe level degamma correction

Hi Shashank, On 9 October 2015 at 20:29, Shashank Sharma wrote: > BDW/SKL/BXT supports Degamma color correction feature, which > linearizes the non-linearity due to gamma encoded color values. > This will be applied before Color Transformation. > > This patch does the following: > 1. Adds the co

[PATCH 22/22] drm/i915: BDW: Pipe level CSC correction

Hi Shashank, On 9 October 2015 at 20:29, Shashank Sharma wrote: > BDW/SKL/BXT support Color Space Conversion (CSC) using a 3x3 matrix > that needs to be programmed into respective CSC registers. > > This patch does the following: > 1. Adds the core function to program CSC correction values for >

[Intel-gfx] [PATCH v5 1/2] drm/dp: Add a drm_aux-dev module for reading/writing dpcd registers.

rm_dp_dpcd_read(aux_dev->aux, *offset, localbuf, todo); 183 if (res <= 0) --- 0-DAY kernel test infrastructureOpen Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation -- next part -- A non-text attachment was scrubbed... Name: .config.gz Type: application/octet-stream Size: 36227 bytes Desc: not available URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20151010/8a5d919a/attachment-0001.obj>

[PATCH 03/22] drm: Add color correction blobs in CRTC state

Thanks for the review comments, Emil. Regards Shashank On 10/10/2015 3:53 AM, Emil Velikov wrote: > Hi Shashank, > > On 9 October 2015 at 20:28, Shashank Sharma > wrote: >> This patch adds new variables in CRTC state, to hold respective color >> correction blobs. These blobs will be required dur

[PATCH 04/22] drm: Add set property support for color manager

Regards Shashank On 10/10/2015 3:55 AM, Emil Velikov wrote: > Hi Shashank, > > On 9 October 2015 at 20:28, Shashank Sharma > wrote: >> As per DRM color manager design, if a userspace wants to set a correction >> blob, it prepares it and sends the blob_id to kernel via set_property >> call. DRM f

[PATCH 09/22] drm/i915: Create color management files

Regards Shashank On 10/10/2015 4:17 AM, Emil Velikov wrote: > Hi Shashank, > > On 9 October 2015 at 20:28, Shashank Sharma > wrote: > [snip] >> + >> +/* Color management bit utilities */ >> +#define GET_BIT_MASK(n) ((1 << n) - 1) >> + >> +/* Read bits of a word from bit no. 'start'(lsb) till 'n'

[PATCH 10/22] drm/i915: Register color correction capabilities

Regards Shashank On 10/10/2015 3:51 AM, Emil Velikov wrote: > Hi Shashank, > > On 9 October 2015 at 20:29, Shashank Sharma > wrote: >> From DRM color management: >> >> DRM color manager supports these color properties: >> 1. "ctm": Color transformation matrix proper

[PATCH 13/22] drm/i915: CHV: Pipe level Gamma correction

Regards Shashank On 10/10/2015 4:37 AM, Emil Velikov wrote: > Hi Shashank, > > On 9 October 2015 at 20:29, Shashank Sharma > wrote: >> CHV/BSW platform supports two different pipe level gamma >> correction modes, which are: >> 1. Legacy 8-bit mode >> 2. 10-bit CGM (Color Gamut Mapping) mode >> >

[PATCH 14/22] drm/i915: CHV: Pipe level degamma correction

Regards Shashank On 10/10/2015 4:41 AM, Emil Velikov wrote: > Hi Shashank, > > On 9 October 2015 at 20:29, Shashank Sharma > wrote: >> CHV/BSW supports Degamma color correction, which linearizes all >> the non-linear color values. This will be applied before Color >> Transformation. >> >> This p

[PATCH 16/22] drm/i915: Commit color correction to CRTC

Regards Shashank On 10/10/2015 4:54 AM, Emil Velikov wrote: > Hi Shashank, > > On 9 October 2015 at 20:29, Shashank Sharma > wrote: >> The color correction blob values are loaded during set_property >> calls. This patch adds a function to find the blob and apply the >> correction values to the d

[PATCH 19/22] drm/i915: BDW: Pipe level Gamma correction

Regards Shashank On 10/10/2015 5:09 AM, Emil Velikov wrote: > Hi Shashank, > > On 9 October 2015 at 20:29, Shashank Sharma > wrote: > [snip] >> diff --git a/drivers/gpu/drm/i915/intel_color_manager.c >> b/drivers/gpu/drm/i915/intel_color_manager.c >> index d5315b2..74f8fc3 100644 >> --- a/drive

[PATCH 15/22] drm/i915: CHV: Pipe level CSC correction

Regards Shashank On 10/10/2015 5:13 AM, Emil Velikov wrote: > On 9 October 2015 at 20:29, Shashank Sharma > wrote: >> CHV/BSW supports Color Space Conversion (CSC) using a 3x3 matrix >> that needs to be programmed into CGM (Color Gamut Mapping) registers. >> >> This patch does the following: >>

[PATCH 17/22] drm/i915: Attach color properties to CRTC

Regards Shashank On 10/10/2015 5:15 AM, Emil Velikov wrote: > On 9 October 2015 at 20:29, Shashank Sharma > wrote: >> Function intel_attach_color_properties_to_crtc attaches a >> color property to its CRTC object. This patch calls this >> function from crtc initialization sequence. >> >> Signed-

[PATCH 21/22] drm/i915: BDW: Pipe level degamma correction

Regards Shashank On 10/10/2015 5:19 AM, Emil Velikov wrote: > Hi Shashank, > > On 9 October 2015 at 20:29, Shashank Sharma > wrote: >> BDW/SKL/BXT supports Degamma color correction feature, which >> linearizes the non-linearity due to gamma encoded color values. >> This will be applied before Co

[PATCH 22/22] drm/i915: BDW: Pipe level CSC correction

Regards Shashank On 10/10/2015 5:24 AM, Emil Velikov wrote: > Hi Shashank, > > On 9 October 2015 at 20:29, Shashank Sharma > wrote: >> BDW/SKL/BXT support Color Space Conversion (CSC) using a 3x3 matrix >> that needs to be programmed into respective CSC registers. >> >> This patch does the follo

[Bug 91278] Tonga GPU lock/reset fail with Unigine Valley

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[Bug 91278] Tonga GPU lock/reset fail with Unigine Valley

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4.2-rc4 kernel warnings on HSW laptop

Hi, I noticed that a HSW laptop gets a few new warnings since 4.2-rc kernels. One error messages pops at each boot time: Console: switching to colour dummy device 80x25 [drm] Replacing VGA console driver [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). [drm] Driver supports precis

[PATCH 05/10] drm/bridge: Add Synopsys DesignWare MIPI DSI host controller driver

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[Bug 91278] Tonga GPU lock/reset fail with Unigine Valley

s it hung. So it looks like there's something in the scheduler that either makes it not happen as often, or not at all (will need to confirm this). -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed

[PATCH 05/10] drm/bridge: Add Synopsys DesignWare MIPI DSI host controller driver

const struct mipi_dsi_msg *msg) --- 0-DAY kernel test infrastructureOpen Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation -- next part -- A non-text attachment was scrubbed... Name:

[Bug 91733] [SKL/HSW] Ogles1conform pntszary.c fails

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[PATCH] nouveau: fix OpenFirmware support

Hi Laurent, On Sat, Oct 10, 2015 at 9:27 AM, Laurent Vivier wrote: > On PowerMac G5 (and I think on all OpenFirmware platforms), nvbios_pcirTp() > returns NULL. But in fact the OpenFirmware has given us the size > we can store in image->size. > > This size is stored in bios->size by of_init() as

v4.3-rc4: i915: ThinkPad Yoga 12: *ERROR* The master control interrupt lied (SDE)!

The Debian 3.16.0 kernel does not emit the error, but I have not attempted a bisection. The warning was added by: 38cc46d drm/i915/bdw: Ack interrupts before handling them (GEN8) 2014-06-18 (1 year, 4 months ago), Oscar Mateo Follows: v3.15-rc8 Preceedes: 3.17-rc1 This is not present in v3.16,

[PATCH] nouveau: fix OpenFirmware support

On Sat, Oct 10, 2015 at 3:29 PM, Laurent Vivier wrote: > > > Le 10/10/2015 20:41, Ilia Mirkin a écrit : >> Hi Laurent, >> >> On Sat, Oct 10, 2015 at 9:27 AM, Laurent Vivier wrote: >>> On PowerMac G5 (and I think on all OpenFirmware platforms), nvbios_pcirTp() >>> returns NULL. But in fact the Op

[Bug 91930] Program with GtkGLArea widget does not redraw

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[Bug 91516] Hang on Dota 2 Reborn with Unsafe Math

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[PATCH] nouveau: fix OpenFirmware support

On Sat, Oct 10, 2015 at 7:45 PM, Laurent Vivier wrote: > > > Le 10/10/2015 21:56, Ilia Mirkin a écrit : >> On Sat, Oct 10, 2015 at 3:29 PM, Laurent Vivier wrote: >>> >>> >>> Le 10/10/2015 20:41, Ilia Mirkin a écrit : Hi Laurent, On Sat, Oct 10, 2015 at 9:27 AM, Laurent Vivier >

[PATCH RFC 1/5] drm/doc: Remove TODO about drm_vblank_pre/post_modeset()

Necessary for Daniel's rename commit to apply cleanly. Signed-off-by: Lukas Wunner --- Documentation/DocBook/drm.tmpl | 2 -- 1 file changed, 2 deletions(-) diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl index 308b141..da1060c 100644 --- a/Documentation/DocBook/drm

[PATCH 06/10] drm: rockchip: Support Synopsys DesignWare MIPI DSI host controller

Add support for Synopsys DesignWare MIPI DSI host controller which is embedded in the rk3288 SoCs. Signed-off-by: Chris Zhong --- drivers/gpu/drm/rockchip/Kconfig| 10 + drivers/gpu/drm/rockchip/Makefile | 1 + drivers/gpu/drm/rockchip/dw_mipi_dsi_rockchip.c | 2

[PATCH 09/10] drm/panel: simple: Add support for BOE TV080WUM-NL0

This adds support for the BOE TV080WUM-NL0 1200x1920 mipi panel to the DRM simple panel driver. Signed-off-by: Chris Zhong --- drivers/gpu/drm/panel/panel-simple.c | 33 + 1 file changed, 33 insertions(+) diff --git a/drivers/gpu/drm/panel/panel-simple.c b/driv

[PATCH v2 2/2] drm/nouveau: increase max pixel clock to 225 MHZ for HDMI

The Nvidia blob allows a pixel clock up to 225 MHz in version 346.59, but only allowed 165MHz in version 295 for HDMI connections. This was tested with a GF114 (Nvidia GTX 560 TI) and a HDMI monitor which used 225 MHz pixel clock and a signal link DVI monitor with a pixel clock of less than 165 MHz

[PATCH v5 0/17] Add Analogix Core Display Port Driver

Hi Javier, On 10/08/2015 08:40 AM, Yakir Yang wrote: > On 10/07/2015 07:25 PM, Javier Martinez Canillas wrote: >> On 10/07/2015 01:05 PM, Yakir Yang wrote: >>> On 10/07/2015 05:26 PM, Javier Martinez Canillas wrote: On 10/07/2015 11:02 AM, Yakir Yang wrote: > On 10/07/2015 04:46 PM, Javie

[PATCH v6 04/17] drm: bridge: analogix/dp: remove duplicate configuration of link rate and link count

link_rate and lane_count already configured in analogix_dp_set_link_train(), so we don't need to config those repeatly after training finished, just remove them out. Beside Display Port 1.2 already support 5.4Gbps link rate, the maximum sets would change from {1.62Gbps, 2.7Gbps} to {1.62Gbps, 2.7G

[PATCH v6 08/17] drm: rockchip: dp: add rockchip platform dp driver

Rockchip have three clocks for dp controller, we leave pclk_edp to analogix_dp driver control, and keep the sclk_edp_24m and sclk_edp in platform driver. Signed-off-by: Yakir Yang --- Changes in v6: None Changes in v5: - Remove the empty line at the end of document, and correct the endpoint num

[PATCH v3 1/7] drm/vc4: Add devicetree bindings for VC4.

re Size: 819 bytes Desc: not available URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20151010/151bf951/attachment-0001.sig>

[PATCH 03/10] drm/dsi: Add a helper to get bits per pixel of MIPI DSI pixel format

From: Liu Ying Signed-off-by: Liu Ying Acked-by: Thierry Reding Signed-off-by: Chris Zhong --- include/drm/drm_mipi_dsi.h | 14 ++ 1 file changed, 14 insertions(+) diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h index f1d8d0d..3662021 100644 --- a/include/dr

[PATCH 05/10] drm/bridge: Add Synopsys DesignWare MIPI DSI host controller driver

add Synopsys DesignWare MIPI DSI host controller driver support. Signed-off-by: Chris Zhong --- drivers/gpu/drm/bridge/Kconfig | 10 + drivers/gpu/drm/bridge/Makefile |1 + drivers/gpu/drm/bridge/dw_mipi_dsi.c | 1055 ++ include/drm/bridge/dw_mip

[PATCH v2 1/2] drm/nouveau: activate dual link TMDS links only when possible

Without this patch a pixel clock rate above 165 MHz on a TMDS link is assumed to be dual link. This is true for DVI, but not for HDMI. HDMI supports no dual link, but it supports pixel clock rates above 165 MHz. Only activate Dual Link mode when it is actual possible. Signed-off-by: Hauke Mehrtens

[PATCH v6 02/17] drm: bridge: analogix/dp: split exynos dp driver to bridge directory

Split the dp core driver from exynos directory to bridge directory, and rename the core driver to analogix_dp_*, rename the platform code to exynos_dp. Beside the new analogix_dp driver would export four hooks. "analogix_dp_bind()" and "analogix_dp_unbind()" "analogix_dp_detect()" and "analogix_dp

[PATCH v6 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range

Both hsync/vsync polarity and interlace mode can be parsed from drm display mode, and dynamic_range and ycbcr_coeff can be judge by the video code. But presumably Exynos still relies on the DT properties, so take good use of mode_fixup() in to achieve the compatibility hacks. Signed-off-by: Yakir

[PATCH] MAINTAINERS: add maintainer for the atmel-hlcdc DRM driver

On 09/10/2015 at 22:37:33 +0200, Boris Brezillon wrote : > Add myself as the maintainer of the atmel-hlcdc DRM driver. > > Signed-off-by: Boris Brezillon > --- > MAINTAINERS | 7 +++ > 1 file changed, 7 insertions(+) > > diff --git a/MAINTAINERS b/MAINTAINERS > index 797236b..11173b5 100644

[PATCH v6 07/17] ARM: dts: exynos/dp: remove some properties that deprecated by analogix_dp driver

After exynos_dp have been split the common IP code into analogix_dp driver, the analogix_dp driver have deprecated some Samsung platform properties which could be dynamically parsed from EDID/MODE/DPCD message, so this is an update for Exynos DTS file for dp-controller. Beside the backward compati

[PATCH v6 10/17] phy: Add driver for rockchip Display Port PHY

This phy driver would control the Rockchip DisplayPort module phy clock and phy power, it is relate to analogix_dp-rockchip dp driver. If you want DP works rightly on rockchip platform, then you should select both of them. Signed-off-by: Yakir Yang --- Changes in v6: None Changes in v5: - Remove

[PATCH] nouveau: fix OpenFirmware support

On PowerMac G5 (and I think on all OpenFirmware platforms), nvbios_pcirTp() returns NULL. But in fact the OpenFirmware has given us the size we can store in image->size. This size is stored in bios->size by of_init() as there is no way to retrieve it otherwise. And as we know the size, copy all da

[PATCH v2 0/2] drm/nouveau: add support for 2560x1440@56 over HDMI

These patches are adding support for outputting 2560x1440 at 56 over HDMI. This needs a pixel clock of 225 MHz which was not supported before. This was tested in a dual monitor setup with a GF114 (GTX 560 TI) and one HDMI monitor running with 2560x1440 at 56 and one DVI monitor running with 1920x1

[PATCH v6 0/17] Add Analogix Core Display Port Driver

Hi all, The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller share the same IP, so a lot of parts can be re-used. I split the common code into bridge directory, then rk3288 and exynos only need to keep some platform code. Cause I can't find the exact IP name of exynos dp contro

[PATCH v6 01/17] drm: exynos: dp: convert to drm bridge mode

In order to move exynos dp code to bridge directory, we need to convert driver drm bridge mode first. As dp driver already have a ptn3460 bridge, so we need to move ptn bridge to the next bridge of dp bridge. Signed-off-by: Yakir Yang --- Changes in v6: - Fix the wrong code in previous series, an

[PATCH v6 03/17] drm: bridge: analogix/dp: fix some obvious code style

Fix some obvious alignment problems, like alignment and line over 80 characters problems, make this easy to be maintained later. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Yakir Yang --- Changes in v6: None Changes in v5: - Resequence this patch after analogix_dp driver have been split fr

[PATCH v6 09/17] Documentation: drm/bridge: add document for analogix_dp

Rockchip DP driver is a helper driver of analogix_dp coder driver, so most of the DT property should be descriped in analogix_dp document. Signed-off-by: Yakir Yang --- Changes in v6: None Changes in v5: - Split binding doc's from driver changes. (Rob) - Add eDP hotplug pinctrl property. (Heiko)

[PATCH v6 11/17] Documentation: phy: add document for rockchip dp phy

This phy driver is binded with the Rockchip DisplayPort driver, here are the brief properties: edp_phy: edp-phy at ff770274 { compatible = "rockchip,rk3288-dp-phy"; rockchip,grf = <&grf>; clocks = <&cru SCLK_EDP_24M>; clock-nam

[PATCH 00/10] Add mipi dsi support for rk3288

The rk3288 MIPI DSI is a Synopsys DesignWare MIPI DSI host controller IP. This series adds support for a Synopsys DesignWare MIPI DSI host controller DRM bridge driver and a rockchip MIPI DSI specific DRM driver. This series also includes a DRM panel driver for BOE TV080WUM-NL0 panel. This panel o

[PATCH 02/10] drm/rockchip: return a true clock rate to adjusted_mode

Sometimes the clock driver can not set a accurate clock_rate for vop, get the true rate of vop_dclk and set it back to adjusted_mode, since the mipi dsi driver need to use the clock to make the calculation of Blanking. Signed-off-by: Chris Zhong --- drivers/gpu/drm/rockchip/rockchip_drm_vop.c |

[PATCH v6 06/17] Documentation: drm/bridge: add document for analogix_dp

Analogix dp driver is split from exynos dp driver, so we just make an copy of exynos_dp.txt, and then simplify exynos_dp.txt Beside update some exynos dtsi file with the latest change according to the devicetree binding documents. Signed-off-by: Yakir Yang --- Changes in v6: None Changes in v5:

[PATCH] nouveau: fix OpenFirmware support

Le 10/10/2015 20:41, Ilia Mirkin a écrit : > Hi Laurent, > > On Sat, Oct 10, 2015 at 9:27 AM, Laurent Vivier wrote: >> On PowerMac G5 (and I think on all OpenFirmware platforms), nvbios_pcirTp() >> returns NULL. But in fact the OpenFirmware has given us the size >> we can store in image->size.