Regards
Shashank
On 10/10/2015 4:41 AM, Emil Velikov wrote:
> Hi Shashank,
>
> On 9 October 2015 at 20:29, Shashank Sharma <shashank.sharma at intel.com>
> wrote:
>> CHV/BSW supports Degamma color correction, which linearizes all
>> the non-linear color values. This will be applied before Color
>> Transformation.
>>
>> This patch does the following:
>> 1. Attach deGamma property to CRTC
>> 2. Add the core function to program DeGamma correction values for
>> CHV/BSW platform
>> 2. Add DeGamma correction macros/defines
>>
>> Signed-off-by: Shashank Sharma <shashank.sharma at intel.com>
>> Signed-off-by: Kausal Malladi <kausalmalladi at gmail.com>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 6 ++
>> drivers/gpu/drm/i915/intel_color_manager.c | 93
>> ++++++++++++++++++++++++++++++
>> drivers/gpu/drm/i915/intel_color_manager.h | 5 ++
>> 3 files changed, 104 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h
>> index 885ac8a..c32e35d 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -8050,4 +8050,10 @@ enum skl_disp_power_wells {
>> #define _PIPE_GAMMA_BASE(pipe) \
>> (_PIPE3(pipe, PIPEA_CGM_GAMMA, PIPEB_CGM_GAMMA, PIPEC_CGM_GAMMA))
>>
>> +#define PIPEA_CGM_DEGAMMA (VLV_DISPLAY_BASE + 0x66000)
>> +#define PIPEB_CGM_DEGAMMA (VLV_DISPLAY_BASE + 0x68000)
>> +#define PIPEC_CGM_DEGAMMA (VLV_DISPLAY_BASE + 0x6A000)
>> +#define _PIPE_DEGAMMA_BASE(pipe) \
>> + (_PIPE3(pipe, PIPEA_CGM_DEGAMMA, PIPEB_CGM_DEGAMMA,
>> PIPEC_CGM_DEGAMMA))
>> +
>> #endif /* _I915_REG_H_ */
>> diff --git a/drivers/gpu/drm/i915/intel_color_manager.c
>> b/drivers/gpu/drm/i915/intel_color_manager.c
>> index cf381b8..bbfe185 100644
>> --- a/drivers/gpu/drm/i915/intel_color_manager.c
>> +++ b/drivers/gpu/drm/i915/intel_color_manager.c
>> @@ -27,6 +27,93 @@
>>
>> #include "intel_color_manager.h"
>>
>> +static int chv_set_degamma(struct drm_device *dev,
>> + struct drm_property_blob *blob, struct drm_crtc *crtc)
>> +{
>> + u16 red_fract, green_fract, blue_fract;
>> + u32 red, green, blue;
>> + u32 num_samples;
>> + u32 word = 0;
>> + u32 count = 0;
>> + u32 cgm_control_reg = 0;
>> + u32 cgm_degamma_reg = 0;
>> + int length;
>> + int ret = 0;
>> + enum pipe pipe;
>> + struct drm_palette *degamma_data;
>> + struct drm_i915_private *dev_priv = dev->dev_private;
>> + struct drm_r32g32b32 *correction_values = NULL;
> Most of the above initializations can go.
Agree.
>
>> +
>> + if (WARN_ON(!blob))
>> + return -EINVAL;
>> +
>> + degamma_data = (struct drm_palette *)blob->data;
>> + pipe = to_intel_crtc(crtc)->pipe;
>> + num_samples = degamma_data->num_samples;
>> + length = num_samples * sizeof(struct drm_r32g32b32);
> This can overflow.
Agree
>
>> +
>> + if (num_samples == GAMMA_DISABLE_VALS) {
> You've opted for switch statements in other patches. Why the if else
> ladder in here ?
As a general programming rule, we tend to switch to switch, when no of
if-else conditions is > 3, here its just 3, enable/disable/invalid so
kept as if/else condition for simpler code.
>
>> + /* Disable DeGamma functionality on Pipe - CGM Block */
>> + cgm_control_reg = I915_READ(_PIPE_CGM_CONTROL(pipe));
>> + cgm_control_reg &= ~CGM_DEGAMMA_EN;
>> + I915_WRITE(_PIPE_CGM_CONTROL(pipe), cgm_control_reg);
>> + DRM_DEBUG_DRIVER("DeGamma disabled on Pipe %c\n",
>> + pipe_name(pipe));
>> + ret = 0;
> Drop the ret variable through the function ?
Agree
>
>> + } else if (num_samples == CHV_DEGAMMA_MAX_VALS) {
>> + cgm_degamma_reg = _PIPE_DEGAMMA_BASE(pipe);
>> +
>> + count = 0;
>> + correction_values = (struct drm_r32g32b32
>> *)°amma_data->lut;
>> + while (count < CHV_DEGAMMA_MAX_VALS) {
> For loop ?
Will pass, prefer while.
>
> Regards,
> Emil
>
