[PATCH V10 3/5] drm/mediatek: using new factor for tvdpll in MT2701

From: Wangyan Wang This is the second step to make MT2701 HDMI stable. The factor depends on the divider of DPI in MT2701, therefore, we should fix this factor to the right and new one. Test: search ok Reviewed-by: CK Hu Signed-off-by: Wangyan Wang --- drivers/gpu/drm/mediatek/mtk_dpi.c | 8

[PATCH V9 1/5] drm/mediatek: remove flag CLK_SET_RATE_PARENT for mt2701 hdmi phy to not propagate rate change to parent

From: Wangyan Wang This is the first step to make MT2701 hdmi stable. The parent rate of hdmi phy had set by DPI driver. We should not set or change the parent rate of MT2701 hdmi phy, as a result we should remove the flags of "CLK_SET_RATE_PARENT" from the clock of MT2701 hdmi phy.

[PATCH V10 5/5] drm/mediatek: no change parent rate in round_rate() for mt2701 hdmi phy

From: Wangyan Wang This is the third step to make MT2701 HDMI stable. We should not change the rate of parent for hdmi phy when doing round_rate for this clock. The parent clock of hdmi phy must be the same as it. We change it when doing set_rate only. Signed-off-by: Wangyan Wang --- drivers

[PATCH V10 1/5] drm/mediatek: remove flag CLK_SET_RATE_PARENT for mt2701 hdmi phy to not propagate rate change to parent

From: Wangyan Wang This is the first step to make MT2701 hdmi stable. The parent rate of hdmi phy had set by DPI driver. We should not set or change the parent rate of MT2701 hdmi phy, as a result we should remove the flags of "CLK_SET_RATE_PARENT" from the clock of MT2701 hdmi phy.

[PATCH V9 3/5] drm/mediatek: using new factor for tvdpll in MT2701

From: Wangyan Wang This is the second step to make MT2701 HDMI stable. The factor depends on the divider of DPI in MT2701, therefore, we should fix this factor to the right and new one. Test: search ok Reviewed-by: CK Hu Signed-off-by: Wangyan Wang --- drivers/gpu/drm/mediatek/mtk_dpi.c | 8

[PATCH V10 0/5] make mt7623 clock of hdmi stable

From: Wangyan Wang V10 adopt maintainer's suggestion. Here is the change list between V9 & V10 1. Align the first character to the right of '(' in mtk_hdmi_phy_clk_get_data() of "drm/mediatek: remove flag ..." 2. Align the first character to the right of '(

[PATCH V9 5/5] drm/mediatek: no change parent rate in round_rate() for mt2701 hdmi phy

From: Wangyan Wang This is the third step to make MT2701 HDMI stable. We should not change the rate of parent for hdmi phy when doing round_rate for this clock. The parent clock of hdmi phy must be the same as it. We change it when doing set_rate only. Signed-off-by: Wangyan Wang --- drivers

[PATCH V9 4/5] drm/mediatek: make implementation of recalc_rate() to match the definition

From: Wangyan Wang Recalculate the rate of this clock, by querying hardware to make implementation of recalc_rate() to match the definition. Signed-off-by: Wangyan Wang --- drivers/gpu/drm/mediatek/mtk_hdmi_phy.c| 8 -- drivers/gpu/drm/mediatek/mtk_hdmi_phy.h| 2

[PATCH V9 2/5] drm/mediatek: fix the rate and divder of hdmi phy for MT2701

From: Wangyan Wang Due to a clerical error,there is one zero less for 1280. Fix it for 12800 Fixes: 0fc721b2968e ("drm/mediatek: add hdmi driver for MT2701 and MT7623") Reviewed-by: CK Hu Signed-off-by: Wangyan Wang --- drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 4 ++

[PATCH V10 4/5] drm/mediatek: make implementation of recalc_rate() to match the definition

From: Wangyan Wang Recalculate the rate of this clock, by querying hardware to make implementation of recalc_rate() to match the definition. Signed-off-by: Wangyan Wang --- drivers/gpu/drm/mediatek/mtk_hdmi_phy.c| 8 -- drivers/gpu/drm/mediatek/mtk_hdmi_phy.h| 2

[PATCH V9 0/5] make mt7623 clock of hdmi stable

From: Wangyan Wang V9 adopt maintainer's suggestion. Here is the change list between V8 & V9 1. Align the first character to the right of '(' in mtk_hdmi_phy_clk_get_data() of "drm/mediatek: remove flag ..." 2. Align the first character to the right of '('

[PATCH V10 2/5] drm/mediatek: fix the rate and divder of hdmi phy for MT2701

From: Wangyan Wang Due to a clerical error,there is one zero less for 1280. Fix it for 12800 Fixes: 0fc721b2968e ("drm/mediatek: add hdmi driver for MT2701 and MT7623") Reviewed-by: CK Hu Signed-off-by: Wangyan Wang --- drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 4 ++

[PATCH V8 5/5] drm/mediatek: make implementation of recalc_rate() to match the definition

From: Wangyan Wang Recalculate the rate of this clock, by querying hardware to make implementation of recalc_rate() to match the definition. Signed-off-by: Wangyan Wang --- drivers/gpu/drm/mediatek/mtk_hdmi_phy.c| 8 -- drivers/gpu/drm/mediatek/mtk_hdmi_phy.h| 2

[PATCH V8 2/5] drm/mediatek: fix the rate and divder of hdmi phy for MT2701

From: Wangyan Wang Due to a clerical error,there is one zero less for 1280. Fix it for 12800 Fixes: 0fc721b2968e ("drm/mediatek: add hdmi driver for MT2701 and MT7623") Reviewed-by: CK Hu Signed-off-by: Wangyan Wang --- drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 4 ++

[PATCH V8 3/5] drm/mediatek: using new factor for tvdpll in MT2701

From: Wangyan Wang This is the second step to make MT2701 HDMI stable. The factor depends on the divider of DPI in MT2701, therefore, we should fix this factor to the right and new one. Signed-off-by: Wangyan Wang --- drivers/gpu/drm/mediatek/mtk_dpi.c | 8 +++- 1 file changed, 3

[PATCH V8 0/5] make mt7623 clock of hdmi stable

From: Wangyan Wang V8 adopt maintainer's suggestion. Here is the change list between V7 & V8 1. Make title more clear in patch commit message. 2. To make MT2701 HDMI stable, TVDPLL should not be adjusted and it's the parent clock of HDMI phy, so HDMI phy could not adjust parent r

[PATCH V8 4/5] drm/mediatek: no change parent rate in round_rate() for mt2701 hdmi phy

From: Wangyan Wang This is the third step to make MT2701 HDMI stable. We should not change the rate of parent for hdmi phy when doing round_rate for this clock. The parent clock of hdmi phy must be the same as it. We change it when doing set_rate only. Signed-off-by: Wangyan Wang --- drivers

[PATCH V8 1/5] drm/mediatek: remove flag CLK_SET_RATE_PARENT for mt2701 hdmi phy to not propagate rate change to parent

From: Wangyan Wang This is the first step to make MT2701 hdmi stable. The parent rate of hdmi phy had set by DPI driver. We should not set or change the parent rate of MT2701 hdmi phy, as a result we should remove the flags of "CLK_SET_RATE_PARENT" from the clock of MT2701 hdmi phy.

[PATCH V7 3/6] drm/mediatek: using different flags of clk for HDMI phy

From: chunhui dai The parent rate of hdmi phy had set by DPI driver. We should not set or change the parent rate of MT2701 hdmi phy, as a result we should remove the flags of "CLK_SET_RATE_PARENT" from the clock of MT2701 hdmi phy. Signed-off-by: chunhui dai Signed-off-by: wa

[PATCH V7 5/6] drm/mediatek: using new factor for tvdpll in MT2701

From: chunhui dai The factor depends on the divider of DPI in MT2701, therefore, we should fix this factor to the right and new one. Signed-off-by: chunhui dai Signed-off-by: wangyan wang --- drivers/gpu/drm/mediatek/mtk_dpi.c | 8 +++- 1 file changed, 3 insertions(+), 5 deletions

[PATCH V7 0/6] make mt7623 clock of hdmi stable

From: Wangyan Wang V7 adopt maintainer's suggestion. Here is the change list between V6 & V7 1. use readl directly & delete hdmi_phy->pll_rate in mtk_hdmi_pll_recalc_rate(). in "drm/mediatek: recalculate hdmi ..." 2. detele mtk_hdmi_phy_read() in mtk_hdmi_phy.c. in &

[PATCH V7 6/6] drm/mediatek: fix the rate of parent for hdmi phy in MT2701

From: chunhui dai We should not change the rate of parent for hdmi phy when doing round_rate for this clock. The parent clock of hdmi phy must be the same as it. We change it when doing set_rate only. Signed-off-by: chunhui dai Signed-off-by: wangyan wang --- drivers/gpu/drm/mediatek

[PATCH V7 1/6] drm/mediatek: recalculate hdmi phy clock of MT2701 by querying hardware

From: chunhui dai Recalculate the rate of this clock, by querying hardware. Signed-off-by: chunhui dai Signed-off-by: wangyan wang --- drivers/gpu/drm/mediatek/mtk_hdmi_phy.c| 7 ++ drivers/gpu/drm/mediatek/mtk_hdmi_phy.h| 3 +-- drivers/gpu/drm/mediatek

[PATCH V7 2/6] drm/mediatek: move the setting of fixed divider

From: chunhui dai move the setting of fixed divider from enable/disable to the function of setting rate. the patch is for hdmi pll divider, the divder should be configured before clock calculation to ensure the clock is right. Signed-off-by: chunhui dai Signed-off-by: wangyan wang

[PATCH V7 4/6] drm/mediatek: fix the rate and divder of hdmi phy for MT2701

From: chunhui dai Fixes: 0fc721b2968e ("drm/mediatek: add hdmi driver for MT2701 and MT7623") Reviewed-by: CK Hu Signed-off-by: chunhui dai Signed-off-by: wangyan wang --- drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) di

[PATCH V6 6/8] clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel

From: chunhui dai The MUX clock of dpi1_sel should select the closet clock for itself. We could add this flag to enable this function of MUX in CCF. Signed-off-by: chunhui dai Signed-off-by: wangyan wang --- drivers/clk/mediatek/clk-mt2701.c | 4 ++-- 1 file changed, 2 insertions(+), 2

[PATCH V6 7/8] drm/mediatek: using new factor for tvdpll in MT2701

From: chunhui dai The factor depends on the divider of DPI in MT2701, therefore, we should fix this factor to the right and new one. Signed-off-by: chunhui dai Signed-off-by: wangyan wang --- drivers/gpu/drm/mediatek/mtk_dpi.c | 8 +++- 1 file changed, 3 insertions(+), 5 deletions

[PATCH V6 5/8] clk: mediatek: add MUX_GATE_FLAGS_2

From: chunhui dai Add MUX_GATE_FLAGS_2 for the clock which needs to set two falgs. Such as some mux need to set the flags of "CLK_MUX_ROUND_CLOSEST". Signed-off-by: chunhui dai Signed-off-by: wangyan wang --- drivers/clk/mediatek/clk-mtk.c | 2 +- drivers/clk/mediatek/clk-

[PATCH V6 4/8] drm/mediatek: fix the rate and divder of hdmi phy for MT2701

From: chunhui dai Due to a clerical error,there is one zero less for 1280. Fix it for 12800. Fixes: 0fc721b2968e ("drm/mediatek: add hdmi driver for MT2701 and MT7623") Reviewed-by: CK Hu Signed-off-by: chunhui dai Signed-off-by: wangyan wang --- drivers/gpu/dr

[PATCH V6 2/8] drm/mediatek: move the setting of fixed divider

From: chunhui dai move the setting of fixed divider from enable/disable to the function of setting rate. the patch is for hdmi pll divider, the divder should be configured before clock calculation to ensure the clock is right. Signed-off-by: chunhui dai Signed-off-by: wangyan wang

[PATCH V6 8/8] drm/mediatek: fix the rate of parent for hdmi phy in MT2701

From: chunhui dai We should not change the rate of parent for hdmi phy when doing round_rate for this clock. The parent clock of hdmi phy must be the same as it. We change it when doing set_rate only. Signed-off-by: chunhui dai Signed-off-by: wangyan wang --- drivers/gpu/drm/mediatek

[PATCH V6 0/8] make mt7623 clock of hdmi stable

From: Wangyan Wang V6 adopt maintainer's suggestion. Here is the change list between V5 & V6 1. change "unsigned char mux_flags;" to "u8 mux_flags;" to match with the struct in " clk: mediatek: add MUX_GATE_FLAGS_2". chunhui dai (8): drm/mediatek:

[PATCH v6 1/8] drm/mediatek: recalculate hdmi phy clock of MT2701 by querying hardware

From: chunhui dai Recalculate the rate of this clock, by querying hardware. Signed-off-by: chunhui dai Signed-off-by: wangyan wang --- drivers/gpu/drm/mediatek/mtk_hdmi_phy.c| 7 ++ drivers/gpu/drm/mediatek/mtk_hdmi_phy.h| 3 +-- drivers/gpu/drm/mediatek

[PATCH V6 3/8] drm/mediatek: using different flags of clk for HDMI phy

From: chunhui dai The parent rate of hdmi phy had set by DPI driver. We should not set or change the parent rate of MT2701 hdmi phy, as a result we should remove the flags of "CLK_SET_RATE_PARENT" from the clock of MT2701 hdmi phy. Signed-off-by: chunhui dai Signed-off-by: wa

[PATCH V5 4/8] drm/mediatek: fix the rate and divder of hdmi phy for MT2701

From: chunhui dai Due to a clerical error,there is one zero less for 1280. Fix it for 12800. Fixes: 0fc721b2968e ("drm/mediatek: add hdmi driver for MT2701 and MT7623") Reviewed-by: CK Hu Signed-off-by: chunhui dai Signed-off-by: wangyan wang --- drivers/gpu/dr

[PATCH V5 2/8] drm/mediatek: move the setting of fixed divider

From: chunhui dai move the setting of fixed divider from enable/disable to the function of setting rate. the patch is for hdmi pll divider, the divder should be configured before clock calculation to ensure the clock is right. Signed-off-by: chunhui dai Signed-off-by: wangyan wang

[PATCH V5 0/8] make mt7623 clock of hdmi stable

From: Wangyan Wang V4 adopt maintainer's suggestion. Here is the change list between V4 & V5 1. add Reviewed-by:CK Hu in " drm/mediatek: fix the rate ..." commit message. 2. describe the reason why mt7623 clock of hdmi is more stable than before. the tvdpll should be st

[PATCH V5 6/8] clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel

From: chunhui dai The MUX clock of dpi1_sel should select the closet clock for itself. We could add this flag to enable this function of MUX in CCF. Signed-off-by: chunhui dai Signed-off-by: wangyan wang --- drivers/clk/mediatek/clk-mt2701.c | 4 ++-- 1 file changed, 2 insertions(+), 2

[PATCH V5 8/8] drm/mediatek: fix the rate of parent for hdmi phy in MT2701

From: chunhui dai We should not change the rate of parent for hdmi phy when doing round_rate for this clock. The parent clock of hdmi phy must be the same as it. We change it when doing set_rate only. Signed-off-by: chunhui dai Signed-off-by: wangyan wang --- drivers/gpu/drm/mediatek

[PATCH V5 7/8] drm/mediatek: using new factor for tvdpll in MT2701

From: chunhui dai The factor depends on the divider of DPI in MT2701, therefore, we should fix this factor to the right and new one. Signed-off-by: chunhui dai Signed-off-by: wangyan wang --- drivers/gpu/drm/mediatek/mtk_dpi.c | 8 +++- 1 file changed, 3 insertions(+), 5 deletions

[PATCH V5 3/8] drm/mediatek: using different flags of clk for HDMI phy

From: chunhui dai The parent rate of hdmi phy had set by DPI driver. We should not set or change the parent rate of MT2701 hdmi phy, as a result we should remove the flags of "CLK_SET_RATE_PARENT" from the clock of MT2701 hdmi phy. Signed-off-by: chunhui dai Signed-off-by: wa

[PATCH V5 5/8] clk: mediatek: add MUX_GATE_FLAGS_2

From: chunhui dai Add MUX_GATE_FLAGS_2 for the clock which needs to set two falgs. Such as some mux need to set the flags of "CLK_MUX_ROUND_CLOSEST". Signed-off-by: chunhui dai Signed-off-by: wangyan wang --- drivers/clk/mediatek/clk-mtk.c | 2 +- drivers/clk/mediatek/clk-

[PATCH v5 1/8] drm/mediatek: recalculate hdmi phy clock of MT2701 by querying hardware

From: chunhui dai Recalculate the rate of this clock, by querying hardware. Signed-off-by: chunhui dai Signed-off-by: wangyan wang --- drivers/gpu/drm/mediatek/mtk_hdmi_phy.c| 7 ++ drivers/gpu/drm/mediatek/mtk_hdmi_phy.h| 3 +-- drivers/gpu/drm/mediatek