From: Wangyan Wang <wangyan.w...@mediatek.com>
V6 adopt maintainer's suggestion.
Here is the change list between V5 & V6
1. change "unsigned char mux_flags;" to "u8 mux_flags;" to
match with the struct in " clk: mediatek: add MUX_GATE_FLAGS_2".
chunhui dai (8):
drm/mediatek: recalculate hdmi phy clock of MT2701 by querying
hardware
drm/mediatek: move the setting of fixed divider
drm/mediatek: using different flags of clk for HDMI phy
drm/mediatek: fix the rate and divder of hdmi phy for MT2701
clk: mediatek: add MUX_GATE_FLAGS_2
clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel
drm/mediatek: using new factor for tvdpll in MT2701
drm/mediatek: fix the rate of parent for hdmi phy in MT2701
drivers/clk/mediatek/clk-mt2701.c | 4 +-
drivers/clk/mediatek/clk-mtk.c | 2 +-
drivers/clk/mediatek/clk-mtk.h | 20 ++++++---
drivers/gpu/drm/mediatek/mtk_dpi.c | 8 ++--
drivers/gpu/drm/mediatek/mtk_hdmi_phy.c | 34 ++++------------
drivers/gpu/drm/mediatek/mtk_hdmi_phy.h | 7 +---
drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 56 +++++++++++++++++++++++---
drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 23 +++++++++++
8 files changed, 102 insertions(+), 52 deletions(-)
--
2.14.1
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