Since the mailbox driver data can be obtained using cmdq_get_mbox_priv()
and all CMDQ users have transitioned to cmdq_get_mbox_priv(),
cmdq_get_shift_pa() can be removed.
Fixes: 0858fde496f8 ("mailbox: cmdq: variablize address shift in platform")
Signed-off-by: Jason-JH Lin
---
drive
_jump()")
Signed-off-by: Jason-JH Lin
---
drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c
b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c
index e5ccf673e152..aa245bf7e
physical address
is the only option to achieve the same functionality.
This commit adds a pa_base parsing flow to the cmdq_client_reg structure
to handle hardware without subsys ID support.
Signed-off-by: Jason-JH Lin
---
drivers/soc/mediatek/mtk-cmdq-helper.c | 15 +--
include/linux/soc
thread for the host VM.
2. VM_CPR_GSIZE
It is used to allocate the CPR SRAM size to each VM. Each VM has 4-bit
configuration, where setting bit 0-3 to configures the size of host VM.
This setting must be configured before the VM configuration to prevent
resource leakage.
Signed-off-by: Jason-JH
cmdq_pkt_write_mask_pa() and
cmdq_pkt_write_mask_subsys().
The original cmdq_pkt_write() and cmdq_pkt_write_mask() will be removed
after all CMDQ users have migrated to the new APIs.
Signed-off-by: Jason-JH Lin
---
drivers/soc/mediatek/mtk-cmdq-helper.c | 41 +
include/linux/soc/mediatek
subsys ID is invalid, the flow will call cmdq_pkt_write_pa() and
cmdq_pkt_write_mask_pa() to achieve the same functionality.
Signed-off-by: Jason-JH Lin
---
drivers/soc/mediatek/mtk-mmsys.c | 12 +---
drivers/soc/mediatek/mtk-mutex.c | 8 ++--
2 files changed, 15 insertions(+), 5
address when generating instructions to ensure GCE accesses the correct
DRAM address. CMDQ users can then call CMDQ helper APIs as usual.
Signed-off-by: Jason-JH Lin
---
drivers/soc/mediatek/mtk-cmdq-helper.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/soc
("soc: mediatek: cmdq: Add parameter shift_pa to
cmdq_pkt_jump()")
Signed-off-by: Jason-JH Lin
---
include/linux/soc/mediatek/mtk-cmdq.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/linux/soc/mediatek/mtk-cmdq.h
b/include/linux/soc/mediatek/mtk-cmdq.h
index 0c
the cmdq_mbox_priv of
cmdq_pkt and add the mminfra_offset to the DRAM address in GCE
instructions.
Signed-off-by: Jason-JH Lin
---
drivers/mailbox/mtk-cmdq-mailbox.c | 6 --
include/linux/mailbox/mtk-cmdq-mailbox.h | 1 +
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/driv
cmdq_pkt_write_mask_pa()
to achieve the same functionality.
Signed-off-by: Jason-JH Lin
---
drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 24 ++--
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
index
no longer in use.
Signed-off-by: Jason-JH Lin
---
drivers/soc/mediatek/mtk-cmdq-helper.c | 49 ++
include/linux/soc/mediatek/mtk-cmdq.h | 35 --
2 files changed, 18 insertions(+), 66 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c
b
tform")
Signed-off-by: Jason-JH Lin
---
drivers/mailbox/mtk-cmdq-mailbox.c | 8
include/linux/mailbox/mtk-cmdq-mailbox.h | 18 ++
2 files changed, 26 insertions(+)
diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c
b/drivers/mailbox/mtk-cmdq-mailbox.c
index a3
Add cmdq_get_mbox_priv() in cmdq_pkt_create() to ensure getting private
data before generating GCE instructions.
Fixes: 0858fde496f8 ("mailbox: cmdq: variablize address shift in platform")
Signed-off-by: Jason-JH Lin
---
drivers/soc/mediatek/mtk-cmdq-helper.c | 1 +
1 file changed, 1
subsys ID is invalid, the flow will call cmdq_pkt_write_pa() and
cmdq_pkt_write_mask_pa() to achieve the same functionality.
Signed-off-by: Jason-JH Lin
---
.../platform/mediatek/mdp3/mtk-mdp3-cmdq.c| 14 +++-
.../platform/mediatek/mdp3/mtk-mdp3-comp.h| 70 ++-
2 files
Since all users have migrated to the new cmdq_pkt_jump* APIs without
shift_pa, the wrapper APIs cmdq_pkt_jump() and cmdq_pkt_jump_rel_temp()
can be removed.
Fixes: ade176534112 ("soc: mediatek: cmdq: Add parameter shift_pa to
cmdq_pkt_jump()")
Signed-off-by: Jason-JH Lin
---
include
meter shift_pa to
cmdq_pkt_jump()")
Signed-off-by: Jason-JH Lin
---
drivers/soc/mediatek/mtk-cmdq-helper.c | 8
include/linux/soc/mediatek/mtk-cmdq.h | 20
2 files changed, 12 insertions(+), 16 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c
("mailbox: cmdq: variablize address shift in platform")
Signed-off-by: Jason-JH Lin
---
drivers/mailbox/mtk-cmdq-mailbox.c | 43
include/linux/mailbox/mtk-cmdq-mailbox.h | 10 ++
2 files changed, 39 insertions(+), 14 deletions(-)
diff --git a/drivers/mailbo
in dt-bindings.
2. Remove the pa_base parameter of CMDQ APIs and related modification.
3. Move subsys checking to client drivers and use 2 alternative
CMDQ APIs to achieve the same functionality.
---
Jason-JH Lin (20):
arm64: dts: mediatek: Add GCE header for MT8196
mailbox: mtk-cmdq: Refine
Add GCE header define for GCE Thread Priority and GCE Event IDs
that used in the MT8196 dtsi.
Signed-off-by: Jason-JH Lin
---
arch/arm64/boot/dts/mediatek/mt8196-gce.h | 612 ++
1 file changed, 612 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt8196-gce.h
. gce_vm: For GCE hardware virtualization control
Currently, the first version of the mt8196 mailbox controller only
requires setting the VM-related registers to enable the permissions
of a host VM.
Signed-off-by: Jason-JH Lin
---
drivers/mailbox/mtk-cmdq-mailbox.c | 12
1 file
pa to
cmdq_pkt_jump()")
Signed-off-by: Jason-JH Lin
---
drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c | 2 +-
drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c | 2 --
drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h | 1 -
3 files changed, 1 insertion(+), 4 deletions(-)
diff --git
thread for the host VM.
2. VM_CPR_GSIZE
It is used to allocate the CPR SRAM size to each VM. Each VM has 4-bit
configuration, where setting bit 0-3 to configures the size of host VM.
This setting must be configured before the VM configuration to prevent
resource leakage.
Signed-off-by: Jason-JH
. gce_vm: For GCE hardware virtualization control
Currently, the first version of the mt8196 mailbox controller only
requires setting the VM-related registers to enable the permissions
of a host VM.
Signed-off-by: Jason-JH Lin
---
drivers/mailbox/mtk-cmdq-mailbox.c | 12
1 file
Add cmdq_get_mbox_priv() in cmdq_pkt_create() to ensure getting private
data before generating GCE instructions.
Fixes: 0858fde496f8 ("mailbox: cmdq: variablize address shift in platform")
Signed-off-by: Jason-JH Lin
---
drivers/soc/mediatek/mtk-cmdq-helper.c | 1 +
1 file changed, 1
meter shift_pa to
cmdq_pkt_jump()")
Signed-off-by: Jason-JH Lin
---
drivers/soc/mediatek/mtk-cmdq-helper.c | 8
include/linux/soc/mediatek/mtk-cmdq.h | 20
2 files changed, 12 insertions(+), 16 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c
no longer in use.
Signed-off-by: Jason-JH Lin
---
drivers/soc/mediatek/mtk-cmdq-helper.c | 49 ++
include/linux/soc/mediatek/mtk-cmdq.h | 35 --
2 files changed, 18 insertions(+), 66 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c
b
_jump()")
Signed-off-by: Jason-JH Lin
---
drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c
b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c
index e5ccf673e152..aa245bf7e
subsys ID is invalid, the flow will call cmdq_pkt_write_pa() and
cmdq_pkt_write_mask_pa() to achieve the same functionality.
Signed-off-by: Jason-JH Lin
---
drivers/soc/mediatek/mtk-mmsys.c | 12 +---
drivers/soc/mediatek/mtk-mutex.c | 8 ++--
2 files changed, 15 insertions(+), 5
("mailbox: cmdq: variablize address shift in platform")
Signed-off-by: Jason-JH Lin
---
drivers/mailbox/mtk-cmdq-mailbox.c | 43
include/linux/mailbox/mtk-cmdq-mailbox.h | 10 ++
2 files changed, 39 insertions(+), 14 deletions(-)
diff --git a/drivers/mailbo
the cmdq_mbox_priv of
cmdq_pkt and add the mminfra_offset to the DRAM address in GCE
instructions.
Signed-off-by: Jason-JH Lin
---
drivers/mailbox/mtk-cmdq-mailbox.c | 6 --
include/linux/mailbox/mtk-cmdq-mailbox.h | 1 +
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/driv
pa to
cmdq_pkt_jump()")
Signed-off-by: Jason-JH Lin
---
drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c | 2 +-
drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c | 2 --
drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h | 1 -
3 files changed, 1 insertion(+), 4 deletions(-)
diff --git
address when generating instructions to ensure GCE accesses the correct
DRAM address. CMDQ users can then call CMDQ helper APIs as usual.
Signed-off-by: Jason-JH Lin
---
drivers/soc/mediatek/mtk-cmdq-helper.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/soc
Add GCE header define for GCE Thread Priority and GCE Event IDs
that used in the MT8196 dtsi.
Signed-off-by: Jason-JH Lin
---
arch/arm64/boot/dts/mediatek/mt8196-gce.h | 612 ++
1 file changed, 612 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt8196-gce.h
Since all users have migrated to the new cmdq_pkt_jump* APIs without
shift_pa, the wrapper APIs cmdq_pkt_jump() and cmdq_pkt_jump_rel_temp()
can be removed.
Fixes: ade176534112 ("soc: mediatek: cmdq: Add parameter shift_pa to
cmdq_pkt_jump()")
Signed-off-by: Jason-JH Lin
---
include
cmdq_pkt_write_mask_pa() and
cmdq_pkt_write_mask_subsys().
The original cmdq_pkt_write() and cmdq_pkt_write_mask() will be removed
after all CMDQ users have migrated to the new APIs.
Signed-off-by: Jason-JH Lin
---
drivers/soc/mediatek/mtk-cmdq-helper.c | 41 +
include/linux/soc/mediatek
("soc: mediatek: cmdq: Add parameter shift_pa to
cmdq_pkt_jump()")
Signed-off-by: Jason-JH Lin
---
include/linux/soc/mediatek/mtk-cmdq.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/linux/soc/mediatek/mtk-cmdq.h
b/include/linux/soc/mediatek/mtk-cmdq.h
index 0c
cmdq_pkt_write_mask_pa()
to achieve the same functionality.
Signed-off-by: Jason-JH Lin
---
drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 24 ++--
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
index
subsys ID is invalid, the flow will call cmdq_pkt_write_pa() and
cmdq_pkt_write_mask_pa() to achieve the same functionality.
Signed-off-by: Jason-JH Lin
---
.../platform/mediatek/mdp3/mtk-mdp3-cmdq.c| 14 +++-
.../platform/mediatek/mdp3/mtk-mdp3-comp.h| 70 ++-
2 files
physical address
is the only option to achieve the same functionality.
This commit adds a pa_base parsing flow to the cmdq_client_reg structure
to handle hardware without subsys ID support.
Signed-off-by: Jason-JH Lin
---
drivers/soc/mediatek/mtk-cmdq-helper.c | 15 +--
include/linux/soc
2 alternative
CMDQ APIs to achieve the same functionality.
Jason-JH Lin (19):
arm64: dts: mediatek: Add GCE header for MT8196
mailbox: mtk-cmdq: Refine DMA address handling for the command buffer
mailbox: mtk-cmdq: Add cmdq private data to cmdq_pkt for generating
instruction
soc
tform")
Signed-off-by: Jason-JH Lin
---
drivers/mailbox/mtk-cmdq-mailbox.c | 6 +++---
include/linux/mailbox/mtk-cmdq-mailbox.h | 18 --
2 files changed, 15 insertions(+), 9 deletions(-)
diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c
b/drivers/mailbox/mtk-cmdq-mailb
after the GCE clocks are enabled.
Move this function into cmdq_runtime_resume() and cmdq_runtime_suspend()
to ensure it is called when the GCE clock is enabled.
Fixes: 7abd037aa581 ("mailbox: mtk-cmdq: add gce ddr enable support flow")
Signed-off-by: Jason-JH Lin
---
drivers/mailbo
. As a result, no page flip
event is sent back to user space, and the screen does not update.
Fixes: da03801ad08f ("drm/mediatek: Move mtk_crtc_finish_page_flip() to
ddp_cmdq_cb()")
Signed-off-by: Jason-JH Lin
---
drivers/gpu/drm/mediatek/mtk_crtc.c | 5 +++--
1 file changed, 3 insert
.
---
Jason-JH Lin (8):
dt-bindings: mailbox: mediatek: Add support for MT8196 GCE mailbox
arm64: dts: mediatek: Add GCE header for MT8196
mailbox: mtk-cmdq: Add driver data to support for MT8196
soc: mediatek: mtk-cmdq: Add pa_base parsing for unsupported subsys ID
hardware
soc: mediatek
: Jason-JH Lin
---
.../platform/mediatek/mdp3/mtk-mdp3-cmdq.c| 18 -
.../platform/mediatek/mdp3/mtk-mdp3-comp.h| 79 ++-
2 files changed, 77 insertions(+), 20 deletions(-)
diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c
b/drivers/media/platform/mediatek
Add the compatible name and iommus property for MT8196.
In MT8196, all command buffers allocated and used by the GCE device
work with IOMMU.
Signed-off-by: Jason-JH Lin
---
.../devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml | 4
1 file changed, 4 insertions(+)
diff --git
a
Add GCE header define for GCE Thread priority and GCE event IDs
that used in the MT8196 dtsi.
Signed-off-by: Jason-JH Lin
---
arch/arm64/boot/dts/mediatek/mt8196-gce.h | 612 ++
1 file changed, 612 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt8196-gce.h
To support hardware without subsys IDs on new SoCs, add a programming
flow that checks whether the subsys ID is valid. If the subsys ID is
invalid, the flow will call 2 alternative CMDQ APIs:
cmdq_pkt_assign() and cmdq_pkt_write_s_value() to achieve the same
functionality.
Signed-off-by: Jason-JH
parsing flow to the cmdq_client_reg structure
for these unsupported subsys ID hardware.
Signed-off-by: Jason-JH Lin
---
drivers/soc/mediatek/mtk-cmdq-helper.c | 18 --
include/linux/soc/mediatek/mtk-cmdq.h | 3 +++
2 files changed, 19 insertions(+), 2 deletions(-)
diff --git a
the mbox API to get the
mminfra_offset value of the SoC, and then add it to the DRAM address
when generating instructions to ensure GCE accesses the correct DRAM
address.
Signed-off-by: Jason-JH Lin
---
drivers/soc/mediatek/mtk-cmdq-helper.c | 35 --
1 file changed, 33
accessing DRAM,
GCE needs to configure the DMA address to be less than 35 bits.
Signed-off-by: Jason-JH Lin
---
drivers/mailbox/mtk-cmdq-mailbox.c | 90 +---
include/linux/mailbox/mtk-cmdq-mailbox.h | 2 +
2 files changed, 84 insertions(+), 8 deletions(-)
diff --git a
To support hardware without subsys IDs on new SoCs, add a programming
flow that checks whether the subsys ID is valid. If the subsys ID is
invalid, the flow will call 2 alternative CMDQ APIs:
cmdq_pkt_assign() and cmdq_pkt_write_s_value() to achieve the same
functionality.
Signed-off-by: Jason-JH
From: Hsiao Chien Sung
Modify rules for both MT8195 and MT8188.
Hardware capabilities include color formats and AFBC are
changed since MT8195, stop using the settings of MT8183.
Acked-by: Rob Herring
Reviewed-by: AngeloGioacchino Del Regno
Reviewed-by: CK Hu
Signed-off-by: Hsiao Chien Sung
This patch series updates the compatible strings for the MediaTek OVL
in the MT8188 dts and the corresponding dt-binding.
The changes ensure that the MT8188 OVL device is correctly identified
and managed by the appropriate drivers.
The first patch is adding the MT8188 compatible strings, refer to:
The OVL hardware capabilities have changed starting from MT8195,
making the MT8183 compatible no longer applicable.
Therefore, it is necessary to remove the MT8183 compatible for OVL.
Reviewed-by: AngeloGioacchino Del Regno
Signed-off-by: Jason-JH.Lin
---
arch/arm64/boot/dts/mediatek/mt8195.dt
Add compatible strings for the MDP3 OVL hardware components in
MediaTek's MT8188 SoC and it is compatible with the existing
MT8195 MDP OVL components.
Signed-off-by: Jason-JH.Lin
Suggested-by: AngeloGioacchino Del Regno
---
.../devicetree/bindings/display/mediatek/mediatek,ovl.yaml | 3 +++
The OVL hardware capabilities have changed starting from MT8195,
making the MT8183 compatible no longer applicable.
Therefore, it is necessary to update the OVL compatible from MT8183 to
MT8195.
Reviewed-by: AngeloGioacchino Del Regno
Signed-off-by: Jason-JH.Lin
---
arch/arm64/boot/dts/mediate
From: Jason-jh Lin
This patch series adds support for the MediaTek MT8196 SoC in the CMDQ
driver and related subsystems. The changes include adding compatible
names and properties, updating driver data to accommodate hardware
changes, and modifying the usage of CMDQ APIs to support non-subsys ID
MT8196 has 3 new hardware configuration compared with the previous SoC,
which correspond to the 3 new driver data:
1. mminfra_offset: For GCE data plane control
Since GCE has been moved into mminfra, GCE needs to append the
mminfra offset to the DRAM address when accessing the DRAM.
2. gce_
To support hardware without subsys IDs on new SoCs, add a programming
flow that checks whether the subsys ID is valid. If the subsys ID is
invalid, the flow will call 2 alternative CMDQ APIs:
cmdq_pkt_assign() and cmdq_pkt_write_s_value() to achieve the same
functionality.
Signed-off-by: Jason-JH.
1. Add compatible name and iommus property to mediatek,gce-mailbox.yaml
for MT8196.
- The compatible name "mediatek,mt8196-gce-mailbox" is added to
ensure that the device tree can correctly identify and configure
the GCE mailbox for the MT8196 SoC.
- The iommus property is adde
When GCE executes instructions, the corresponding hardware register
can be found through the subsys ID. For hardware that does not support
subsys ID, its subsys ID will be set to invalid value and its physical
address needs to be used to generate GCE instructions.
This commit adds a pa_base parsin
To support hardware without subsys IDs on new SoCs, add a programming
flow that checks whether the subsys ID is valid. If the subsys ID is
invalid, the flow will call 2 alternative CMDQ APIs:
cmdq_pkt_assign() and cmdq_pkt_write_s_mask_value() to achieve the
same functionality.
Signed-off-by: Jaso
Since GCE has been moved to mminfra in MT8196, all transactions from
mminfra to DRAM will have their addresses adjusted by subtracting a
mminfra offset.
This information should be handled inside the CMDQ driver, allowing
CMDQ users to call CMDQ APIs as usual.
Therefore, CMDQ driver needs to use th
To support hardware without subsys IDs on new SoCs, add a programming
flow that checks whether the subsys ID is valid. If the subsys ID is
invalid, the flow will call 2 alternative CMDQ APIs:
cmdq_pkt_assign() and cmdq_pkt_write_s_value() to achieve the same
functionality.
Signed-off-by: Jason-JH.
From: Hsiao Chien Sung
Modify rules for both MT8195 and MT8188.
Hardware capabilities include color formats and AFBC are
changed since MT8195, stop using the settings of MT8183.
Acked-by: Rob Herring
Reviewed-by: AngeloGioacchino Del Regno
Reviewed-by: CK Hu
Signed-off-by: Hsiao Chien Sung
The OVL hardware capabilities have changed starting from MT8195,
making the MT8183 compatible no longer applicable.
Therefore, it is necessary to remove the MT8183 compatible for OVL.
Signed-off-by: Jason-JH.Lin
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 2 +-
1 file changed, 1 insertion(+),
This patch series updates the compatible strings for the MediaTek OVL
in the MT8188 dts and the corresponding dt-binding.
The changes ensure that the MT8188 OVL device is correctly identified
and managed by the appropriate drivers.
The 1st patch is resending the reviewed and acked patch from:
-
h
The OVL hardware capabilities have changed starting from MT8195,
making the MT8183 compatible no longer applicable.
Therefore, it is necessary to update the OVL compatible from MT8183 to
MT8195.
Signed-off-by: Jason-JH.Lin
---
arch/arm64/boot/dts/mediatek/mt8188.dtsi | 2 +-
1 file changed, 1 in
From: Hsiao Chien Sung
Modify rules for both MT8195 and MT8188.
Hardware capabilities include color formats and AFBC are
changed since MT8195, stop using the settings of MT8183.
Acked-by: Rob Herring
Reviewed-by: AngeloGioacchino Del Regno
Signed-off-by: Hsiao Chien Sung
Signed-off-by: Jason
This patch series updates the compatible strings for the MediaTek OVL
in the MT8188 dts and the corresponding dt-binding.
The changes ensure that the MT8188 OVL device is correctly identified
and managed by the appropriate drivers.
The first patch is resending the reviewed and acked patch from:
-
The OVL hardware capabilities have changed starting from MT8195,
making the MT8183 compatible no longer applicable.
Therefore, it is necessary to update the OVL compatible from MT8183 to
MT8195.
Signed-off-by: Jason-JH.Lin
---
arch/arm64/boot/dts/mediatek/mt8188.dtsi | 2 +-
1 file changed, 1 in
To support hardware without subsys IDs on new SoCs, add a programming
flow that checks whether the subsys ID is valid. If the subsys ID is
invalid, the flow will call 2 alternative CMDQ APIs:
cmdq_pkt_assign() and cmdq_pkt_write_s_value() to achieve the same
functionality.
Signed-off-by: Jason-JH.
mtk_crtc_finish_page_flip() is used to notify userspace that a
page flip has been completed, allowing userspace to free the frame
buffer of the last frame and commit the next frame.
In MediaTek's hardware design for configuring display hardware by using
GCE, `DRM_EVENT_FLIP_COMPLETE` should be not
When GCE executes instructions, the corresponding hardware register
can be found through the subsys ID. For hardware that does not support
subsys IDs, the physical address needs to be used to generate GCE
instructions.
This commit adds a pa_base parsing flow to the cmdq_client_reg structure
for th
To support hardware without subsys IDs on new SoCs, add a programming
flow that checks whether the subsys ID is valid. If the subsys ID is
invalid, the flow will call 2 alternative CMDQ APIs:
cmdq_pkt_assign() and cmdq_pkt_write_s_mask_value() to achieve the
same functionality.
Signed-off-by: Jaso
To support hardware without subsys IDs on new SoCs, add a programming
flow that checks whether the subsys ID is valid. If the subsys ID is
invalid, the flow will call 2 alternative CMDQ APIs:
cmdq_pkt_assign() and cmdq_pkt_write_s_value() to achieve the same
functionality.
Signed-off-by: Jason-JH.
MT8196 has 4 hardware changes compared with the previous SoC,
which correspond to the 4 new driver data:
1. mminfra_offset: For GCE data plane control
Since GCE has been moved into mminfra, GCE needs to append the
mminfra offset to the DRAM address when accessing the DRAM.
2. gce_vm: For GC
Since GCE has been moved to mminfra in MT8196, all transactions from
mminfra to DRAM will have their addresses adjusted by subtracting a
mminfra offset.
This information should be handled inside the CMDQ driver, allowing
CMDQ users to call CMDQ APIs as usual.
Therefore, CMDQ driver needs to use th
Add the Global Command Engine (GCE) header file to define the GCE
thread priority, GCE subsys ID and GCE events for MT8196.
Signed-off-by: Jason-JH.Lin
---
.../dt-bindings/mailbox/mediatek,mt8196-gce.h | 1439 +
1 file changed, 1439 insertions(+)
create mode 100644 include/dt-bi
From: Jason-jh Lin
This patch series adds support for the MediaTek MT8196 SoC in the CMDQ
driver and related subsystems. The changes include adding compatible
names and properties, updating driver data to accommodate hardware
changes, and modifying the usage of CMDQ API to support non-subsys ID
Add compatible name and iommus property for MT8196.
Signed-off-by: Jason-JH.Lin
---
.../devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml | 4
1 file changed, 4 insertions(+)
diff --git
a/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml
b/Documentation/devicetr
mtk_crtc_finish_page_flip() is used to notify userspace that a
page flip has been completed, allowing userspace to free the frame
buffer of the last frame and commit the next frame.
In MediaTek's hardware design for configuring display hardware by using
GCE, `DRM_EVENT_FLIP_COMPLETE` should be not
MT8196 has 4 hardware changes compared with the previous SoC,
which correspond to the 4 new driver data:
1. mminfra_offset: For GCE data plane control
Since GCE has been moved into mminfra, GCE needs to append the
mminfra offset to the DRAM address when accessing the DRAM.
2. gce_vm: For GC
Add the Global Command Engine (GCE) header file to define the GCE
thread priority, GCE subsys ID, GCE events, and various constants
for MT8196.
Signed-off-by: Jason-JH.Lin
---
.../dt-bindings/mailbox/mediatek,mt8196-gce.h | 1449 +
1 file changed, 1449 insertions(+)
create mode
To support non-subsys ID hardware on new SoCs, the CMDQ API has been
changed to include the pa_base parameter. This change accommodates
the new interface requirements.
Signed-off-by: Jason-JH.Lin
---
drivers/soc/mediatek/mtk-mmsys.c | 1 +
drivers/soc/mediatek/mtk-mutex.c | 2 +-
2 files changed
Add compatible name and iommus property for MT8196.
Signed-off-by: Jason-JH.Lin
---
.../devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml | 4
1 file changed, 4 insertions(+)
diff --git
a/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml
b/Documentation/devicetr
Since GCE has been moved to mminfra in MT8196, all transactions from
mminfra to DRAM will have their addresses adjusted by subtracting a
mminfra offset.
This information should be handled inside the CMDQ driver, allowing
CMDQ users to call CMDQ APIs as usual.
Therefore, CMDQ driver needs to use th
When GCE executes instructions, the corresponding hardware register
can be found through the subsys ID.
For unsupported subsys ID hardware, the physical address need to be used
to generate GCE instructions.
Add the pa_base interface to the instruction programming flow for these
unsupported subsys
This patch series adds support for the MediaTek MT8196 SoC in the CMDQ
driver and related subsystems. The changes include adding compatible
names and properties, updating driver data to accommodate hardware
changes, and modifying the CMDQ API to support non-subsys ID hardware.
Jason-JH.Lin (8):
To support non-subsys ID hardware on new SoCs, the CMDQ API has been
changed to include the pa_base parameter. This change accommodates
the new interface requirements.
Signed-off-by: Jason-JH.Lin
---
drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions
To support non-subsys ID hardware on new SoCs, the CMDQ API has been
changed to include the pa_base parameter. This change accommodates
the new interface requirements.
Signed-off-by: Jason-JH.Lin
---
drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c | 4 ++--
drivers/media/platform/mediatek/m
mtk_crtc_finish_page_flip() is used to notify userspace that a
page flip has been completed, allowing userspace to free the frame
buffer of the last frame and commit the next frame.
In MediaTek's hardware design for configuring display hardware by using
GCE, `DRM_EVENT_FLIP_COMPLETE` should be not
mtk_crtc_finish_page_flip() is used to notify the page flip that has
been completed to the userspace, so userspace can free the frame buffer
of the last frame and commit the next frame.
However, mtk_crtc_finish_page_flip() cannot guarantee the GCE has
configured all the display hardware settings o
mediatek-drm driver reported the capability of 180-degree rotation by
adding `DRM_MODE_ROTATE_180` to the plane property, as flip-x combined
with flip-y equals a 180-degree rotation. However, we did not handle
the rotation property in the driver and lead to rotation issues.
Fixes: 74608d8feefd ("d
Some SoCs do not support the ignore_pixl_alpha flag, which breaks the
XRGB format. Some SoCs do not support pre-multiplied pixel formats
and extending configuration of OVL pre-multiplied color formats,
such as MT8173.
Fix the SoC degradation problem by this series.
Tested-by: Chen-Yu Tsai
--
Refine the comment for ignore_pixel_alpha flag and move it to
if(state->fb) statement to make it less conditional.
Signed-off-by: Jason-JH.Lin
Reviewed-by: AngeloGioacchino Del Regno
Reviewed-by: CK Hu
---
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 +-
1 file changed, 9 inse
Since some SoCs support premultiplied pixel formats but some do not,
the blend_modes parameter is added to mtk_plane_init(), which is
obtained from the mtk_ddp_comp_get_blend_modes function implemented
in different blending supported components.
The blending supported components can use driver dat
OVL_CON_CLRFMT_MAN is a configuration for extending color format
settings of DISP_REG_OVL_CON(n).
It will change some of the original color format settings.
Take the settings of (3 << 12) for example.
- If OVL_CON_CLRFMT_MAN = 0 means OVL_CON_CLRFMT_RGBA.
- If OVL_CON_CLRFMT_MAN = 1 means OVL_
Since we changed MACROs to be consistent with DRM input color format
naming, the comment for ovl_fmt_conver() is no longer needed.
Fixes: 9f428b95ac89 ("drm/mediatek: Add new color format MACROs in OVL")
Signed-off-by: Jason-JH.Lin
Reviewed-by: CK Hu
---
drivers/gpu/drm/mediatek/mtk_disp_ovl.c
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