://devicetree.org/schemas/npu/rockchip,rk3588-rknn-core.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Neural Processing Unit IP from Rockchip
+
+maintainers:
+ - Tomeu Vizoso
+
+description:
+ Rockchip IP for accelerating inference of neural networks, based on NVIDIA's
+ open s
Hugo
Signed-off-by: Tomeu Vizoso
---
drivers/accel/rocket/Makefile| 3 +-
drivers/accel/rocket/rocket_device.c | 4 ++
drivers/accel/rocket/rocket_device.h | 2 +
drivers/accel/rocket/rocket_drv.c| 7 +-
drivers/accel/rocket/rocket_gem.c| 131
same IOCTLs from the Etnaviv driver.
v2:
- Don't break UABI by reordering the IOCTL IDs (Jeff Hugo)
v3:
- Check that padding fields in IOCTLs are zero (Jeff Hugo)
Signed-off-by: Tomeu Vizoso
---
drivers/accel/rocket/rocket_drv.c | 2 +
drivers/accel/rocket/rocket_
Enable the nodes added in a previous commit to the rk3588s device tree.
v2:
- Split nodes (Sebastian Reichel)
- Sort nodes (Sebastian Reichel)
- Add board regulators (Sebastian Reichel)
Signed-off-by: Tomeu Vizoso
---
.../arm64/boot/dts/rockchip/rk3588-quartzpro64.dts | 30
/mesa/mesa/-/merge_requests/29698
Signed-off-by: Tomeu Vizoso
---
Changes in v5:
- Use bulk clk API
- Rename bindings file
- Syntax improvement to bindings
- Link to v4:
https://lore.kernel.org/r/20250519-6-10-rocket-v4-0-d6dff6b4c...@tomeuvizoso.net
Changes in v4:
- Several fixes to DT bindings
From: Nicolas Frattaroli
The NPU on the ROCK5B uses the same regulator for both the sram-supply
and the npu's supply. Add this regulator, and enable all the NPU bits.
Also add the regulator as a domain-supply to the pd_npu power domain.
Signed-off-by: Nicolas Frattaroli
Signed-off-by:
be on, add a label to
the NPU power domain node so board files can reference it.
Signed-off-by: Nicolas Frattaroli
Signed-off-by: Tomeu Vizoso
---
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/r
macros (Thomas Zimmermann)
- Add padding to ioctls and check for zero (Jeff Hugo)
- Improve error handling (Nicolas Frattaroli)
Signed-off-by: Tomeu Vizoso
---
drivers/accel/rocket/Makefile| 3 +-
drivers/accel/rocket/rocket_core.c | 14 +-
drivers/accel/rocket/rocket_core.h | 14
anups (Thomas Zimmermann and Jeff Hugo)
- Make use of GPL-2.0-only for the copyright notice (Jeff Hugo)
- PM improvements (Nicolas Frattaroli)
v4:
- Use bulk clk API (Krzysztof Kozlowski)
Signed-off-by: Tomeu Vizoso
---
Documentation/accel/index.rst| 1 +
Documentation/accel/rocket/inde
rockchip,iommu compatible to IOMMU nodes (Sebastian Reichel)
v3:
- Adapt to a split of the register block in the DT bindings (Nicolas
Frattaroli)
v4:
- Adapt to changes in bindings
Signed-off-by: Tomeu Vizoso
---
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 85 +++
1 f
/mesa/mesa/-/merge_requests/29698
Signed-off-by: Tomeu Vizoso
---
Changes in v4:
- Several fixes to DT bindings.
- Link to v3:
https://lore.kernel.org/r/20250516-6-10-rocket-v3-0-7051ac922...@tomeuvizoso.net
Changes in v3:
- Reference in the device tree only the register blocks that are
same IOCTLs from the Etnaviv driver.
v2:
- Don't break UABI by reordering the IOCTL IDs (Jeff Hugo)
v3:
- Check that padding fields in IOCTLs are zero (Jeff Hugo)
Signed-off-by: Tomeu Vizoso
---
drivers/accel/rocket/rocket_drv.c | 2 +
drivers/accel/rocket/rocket_
Kozlowski)
- Add reg-names to list of required properties (Krzysztof Kozlowski)
- Fix example (Krzysztof Kozlowski)
Signed-off-by: Tomeu Vizoso
Signed-off-by: Sebastian Reichel
---
.../bindings/npu/rockchip,rknn-core.yaml | 149 +
1 file changed, 149 insertions
macros (Thomas Zimmermann)
- Add padding to ioctls and check for zero (Jeff Hugo)
- Improve error handling (Nicolas Frattaroli)
Signed-off-by: Tomeu Vizoso
---
drivers/accel/rocket/Makefile| 3 +-
drivers/accel/rocket/rocket_core.c | 14 +-
drivers/accel/rocket/rocket_core.h | 14
be on, add a label to
the NPU power domain node so board files can reference it.
Signed-off-by: Nicolas Frattaroli
Signed-off-by: Tomeu Vizoso
---
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/r
rockchip,iommu compatible to IOMMU nodes (Sebastian Reichel)
v3:
- Adapt to a split of the register block in the DT bindings (Nicolas
Frattaroli)
v4:
- Adapt to changes in bindings
Signed-off-by: Tomeu Vizoso
---
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 85 +++
1 f
Enable the nodes added in a previous commit to the rk3588s device tree.
v2:
- Split nodes (Sebastian Reichel)
- Sort nodes (Sebastian Reichel)
- Add board regulators (Sebastian Reichel)
Signed-off-by: Tomeu Vizoso
---
.../arm64/boot/dts/rockchip/rk3588-quartzpro64.dts | 30
anups (Thomas Zimmermann and Jeff Hugo)
- Make use of GPL-2.0-only for the copyright notice (Jeff Hugo)
- PM improvements (Nicolas Frattaroli)
Signed-off-by: Tomeu Vizoso
---
Documentation/accel/index.rst| 1 +
Documentation/accel/rocket/index.rst | 25 +++
MAINTA
From: Nicolas Frattaroli
The NPU on the ROCK5B uses the same regulator for both the sram-supply
and the npu's supply. Add this regulator, and enable all the NPU bits.
Also add the regulator as a domain-supply to the pd_npu power domain.
Signed-off-by: Nicolas Frattaroli
Signed-off-by:
ivers/accel/rocket/rocket_gem.c
b/drivers/accel/rocket/rocket_gem.c
new file mode 100644
index
..8a8a7185daac4740081293aae6945c9b2bbeb2dd
--- /dev/null
+++ b/drivers/accel/rocket/rocket_gem.c
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copy
On Mon, May 19, 2025 at 10:47 AM Krzysztof Kozlowski wrote:
>
> On 19/05/2025 10:27, Tomeu Vizoso wrote:
> > On Mon, May 19, 2025 at 8:08 AM Krzysztof Kozlowski wrote:
> >>
> >> On 16/05/2025 18:53, Tomeu Vizoso wrote:
> >>> See Chapter 36 "RKNN&quo
On Mon, May 19, 2025 at 8:08 AM Krzysztof Kozlowski wrote:
>
> On 16/05/2025 18:53, Tomeu Vizoso wrote:
> > See Chapter 36 "RKNN" from the RK3588 TRM (Part 1).
> >
> > This is a derivative of NVIDIA's NVDLA, but with its own front-end
> > proces
macros (Thomas Zimmermann)
- Add padding to ioctls and check for zero (Jeff Hugo)
- Improve error handling (Nicolas Frattaroli)
Signed-off-by: Tomeu Vizoso
---
drivers/accel/rocket/Makefile| 3 +-
drivers/accel/rocket/rocket_core.c | 14 +-
drivers/accel/rocket/rocket_core.h | 14
be on, add a label to
the NPU power domain node so board files can reference it.
Signed-off-by: Nicolas Frattaroli
Signed-off-by: Tomeu Vizoso
---
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/r
From: Nicolas Frattaroli
The NPU on the ROCK5B uses the same regulator for both the sram-supply
and the npu's supply. Add this regulator, and enable all the NPU bits.
Also add the regulator as a domain-supply to the pd_npu power domain.
Signed-off-by: Nicolas Frattaroli
Signed-off-by:
Enable the nodes added in a previous commit to the rk3588s device tree.
v2:
- Split nodes (Sebastian Reichel)
- Sort nodes (Sebastian Reichel)
- Add board regulators (Sebastian Reichel)
Signed-off-by: Tomeu Vizoso
---
.../arm64/boot/dts/rockchip/rk3588-quartzpro64.dts | 30
same IOCTLs from the Etnaviv driver.
v2:
- Don't break UABI by reordering the IOCTL IDs (Jeff Hugo)
v3:
- Check that padding fields in IOCTLs are zero (Jeff Hugo)
Signed-off-by: Tomeu Vizoso
---
drivers/accel/rocket/rocket_drv.c | 2 +
drivers/accel/rocket/rocket_
ivers/accel/rocket/rocket_gem.c
b/drivers/accel/rocket/rocket_gem.c
new file mode 100644
index
..8a8a7185daac4740081293aae6945c9b2bbeb2dd
--- /dev/null
+++ b/drivers/accel/rocket/rocket_gem.c
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copy
anups (Thomas Zimmermann and Jeff Hugo)
- Make use of GPL-2.0-only for the copyright notice (Jeff Hugo)
- PM improvements (Nicolas Frattaroli)
Signed-off-by: Tomeu Vizoso
---
Documentation/accel/index.rst| 1 +
Documentation/accel/rocket/index.rst | 25 +++
MAINTA
rockchip,iommu compatible to IOMMU nodes (Sebastian Reichel)
v3:
- Adapt to a split of the register block in the DT bindings (Nicolas
Frattaroli)
Signed-off-by: Tomeu Vizoso
---
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 85 +++
1 file changed, 85 insertions(+)
diff --g
/mesa/mesa/-/merge_requests/29698
Signed-off-by: Tomeu Vizoso
---
Changes in v3:
- Reference in the device tree only the register blocks that are
actually used.
- Several style and robustness fixes suggested in the mailing list.
- Added patches from Nicolas Frattaroli that add support to the NPU
would ever use (Nicolas Frattaroli)
- Group supplies (Rob Herring)
- Explain the way in which the top core is special (Rob Herring)
Signed-off-by: Tomeu Vizoso
Signed-off-by: Sebastian Reichel
---
.../bindings/npu/rockchip,rknn-core.yaml | 162 +
1 file changed, 162
On Fri, May 16, 2025 at 12:25 PM Nicolas Frattaroli
wrote:
>
> On Thursday, 15 May 2025 10:30:14 Central European Summer Time Tomeu Vizoso
> wrote:
> > On Wed, May 14, 2025 at 7:50 PM Nicolas Frattaroli
> > wrote:
> > >
> > > On Wednesday, 14 May 2025 17:1
On Fri, Apr 25, 2025 at 8:22 PM Nicolas Frattaroli
wrote:
>
> On Tuesday, 25 February 2025 08:55:50 Central European Summer Time Tomeu
> Vizoso wrote:
> > This initial version supports the NPU as shipped in the RK3588 SoC and
> > described in the first part of i
On Wed, May 14, 2025 at 7:50 PM Nicolas Frattaroli
wrote:
>
> On Wednesday, 14 May 2025 17:18:22 Central European Summer Time Tomeu Vizoso
> wrote:
> > Hi Nicolas,
> >
> > Thanks for looking at this. Some thoughts below:
> >
> > On Fri, Apr 25, 2025 a
Hi Rob,
On Tue, Feb 25, 2025 at 5:02 PM Rob Herring wrote:
>
> On Tue, Feb 25, 2025 at 08:55:47AM +0100, Tomeu Vizoso wrote:
> > Add the bindings for the Neural Processing Unit IP from Rockchip.
> >
> > v2:
> > - Adapt to new node structure (one node per core,
Hi Nicolas,
Thanks for looking at this. Some thoughts below:
On Fri, Apr 25, 2025 at 8:50 PM Nicolas Frattaroli
wrote:
>
> On Tuesday, 25 February 2025 08:55:47 Central European Summer Time Tomeu
> Vizoso wrote:
> > Add the bindings for the Neural Processing Unit IP from Rockc
On Thu, May 8, 2025 at 7:08 PM Lucas Stach wrote:
>
> Am Donnerstag, dem 08.05.2025 um 16:56 +0200 schrieb Tomeu Vizoso:
> > We should be comparing the last submitted sequence number with that of
> > the address space we may be switching to.
> >
> This isn't the re
We should be comparing the last submitted sequence number with that of
the address space we may be switching to.
Fixes: 27b67278e007 ("drm/etnaviv: rework MMU handling")
Signed-off-by: Tomeu Vizoso
---
drivers/gpu/drm/etnaviv/etnaviv_buffer.c | 2 +-
1 file changed, 1 insertion(+),
We should be comparing the last submitted sequence number with that of
the address space we may be switching to.
And we should be using the latter as the last submitted sequence number
afterwards.
Signed-off-by: Tomeu Vizoso
---
drivers/gpu/drm/etnaviv/etnaviv_buffer.c | 3 ++-
1 file changed
of cores
- Misc. style fixes (Jeffrey Hugo)
- Repack IOCTL struct (Jeffrey Hugo)
Signed-off-by: Tomeu Vizoso
---
drivers/accel/rocket/Makefile| 3 +-
drivers/accel/rocket/rocket_core.c | 6 +
drivers/accel/rocket/rocket_core.h | 14 +
drivers/accel/rocket/rocket_device.c | 2
Enable the nodes added in a previous commit to the rk3588s device tree.
v2:
- Split nodes (Sebastian Reichel)
- Sort nodes (Sebastian Reichel)
- Add board regulators (Sebastian Reichel)
Signed-off-by: Tomeu Vizoso
---
.../arm64/boot/dts/rockchip/rk3588-quartzpro64.dts | 30
same IOCTLs from the Etnaviv driver.
v2:
- Don't break UABI by reordering the IOCTL IDs (Jeffrey Hugo)
Signed-off-by: Tomeu Vizoso
---
drivers/accel/rocket/rocket_drv.c | 2 ++
drivers/accel/rocket/rocket_gem.c | 75 +++
drivers/accel/rocket/rocket_
This uses the SHMEM DRM helpers and we map right away to the CPU and NPU
sides, as all buffers are expected to be accessed from both.
v2:
- Sync the IOMMUs for the other cores when mapping and unmapping.
Signed-off-by: Tomeu Vizoso
---
drivers/accel/rocket/Makefile| 3 +-
drivers
rockchip,iommu compatible to IOMMU nodes (Sebastian Reichel)
Signed-off-by: Tomeu Vizoso
---
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 76 +++
1 file changed, 76 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
b/arch/arm64/boot/dts/rockchip/r
Add the bindings for the Neural Processing Unit IP from Rockchip.
v2:
- Adapt to new node structure (one node per core, each with its own
IOMMU)
- Several misc. fixes from Sebastian Reichel
Signed-off-by: Tomeu Vizoso
Signed-off-by: Sebastian Reichel
---
.../bindings/npu/rockchip,rknn
/mesa/mesa/-/merge_requests/29698
Signed-off-by: Tomeu Vizoso
---
Changes in v2:
- Drop patch adding the rk3588 compatible to rockchip-iommu (Sebastian Reichel)
- Drop patch adding support for multiple power domains to rockchip-iommu
(Sebastian Reichel)
- Link to v1:
https://lore.kernel.org/r
On Fri, Jun 14, 2024 at 2:07 PM Robin Murphy wrote:
>
> On 2024-06-13 10:38 pm, Sebastian Reichel wrote:
> > Hi,
> >
> > On Thu, Jun 13, 2024 at 11:34:02AM GMT, Tomeu Vizoso wrote:
> >> On Thu, Jun 13, 2024 at 11:24 AM Tomeu Vizoso
> >> wrote:
>
On Thu, Jun 13, 2024 at 11:38 PM Sebastian Reichel
wrote:
>
> Hi,
>
> On Thu, Jun 13, 2024 at 11:34:02AM GMT, Tomeu Vizoso wrote:
> > On Thu, Jun 13, 2024 at 11:24 AM Tomeu Vizoso wrote:
> > > On Thu, Jun 13, 2024 at 2:05 AM Sebastian Reichel
> > > wrote:
&
On Wed, Jun 26, 2024 at 9:26 PM Daniel Stone wrote:
>
> On Wed, 26 Jun 2024 at 18:52, Daniel Vetter wrote:
> > On Wed, Jun 26, 2024 at 11:39:01AM +0100, Daniel Stone wrote:
> > > On Wed, 26 Jun 2024 at 09:28, Lucas Stach wrote:
> > > > So we are kind of stuck here between breaking one or the oth
Hi Lucas,
Do you have any idea on how not to break userspace if we expose a render node?
Cheers,
Tomeu
On Wed, Jun 12, 2024 at 4:26 PM Tomeu Vizoso wrote:
>
> On Mon, May 20, 2024 at 1:19 PM Daniel Stone wrote:
> >
> > Hi,
> >
> > On Mon, 20 May 2024 at 08:39,
On Thu, Jun 13, 2024 at 11:24 AM Tomeu Vizoso wrote:
>
> On Thu, Jun 13, 2024 at 2:05 AM Sebastian Reichel
> wrote:
> >
> > Hi,
> >
> > On Wed, Jun 12, 2024 at 03:52:55PM GMT, Tomeu Vizoso wrote:
> > > IOMMUs with multiple base addresses
On Thu, Jun 13, 2024 at 2:05 AM Sebastian Reichel
wrote:
>
> Hi,
>
> On Wed, Jun 12, 2024 at 03:52:55PM GMT, Tomeu Vizoso wrote:
> > IOMMUs with multiple base addresses can also have multiple power
> > domains.
> >
> > The base framework only takes ca
On Mon, May 20, 2024 at 1:19 PM Daniel Stone wrote:
>
> Hi,
>
> On Mon, 20 May 2024 at 08:39, Tomeu Vizoso wrote:
> > On Fri, May 10, 2024 at 10:34 AM Lucas Stach wrote:
> > > Am Mittwoch, dem 24.04.2024 um 08:37 +0200 schrieb Tomeu Vizoso:
> > > > If w
same IOCTLs from the Etnaviv driver.
Signed-off-by: Tomeu Vizoso
---
drivers/accel/rocket/rocket_drv.c | 2 ++
drivers/accel/rocket/rocket_gem.c | 68 +++
drivers/accel/rocket/rocket_gem.h | 7 +++-
include/uapi/drm/rocket_accel.h | 20 +++-
4
Using the DRM GPU scheduler infrastructure, with a scheduler for each
core.
Userspace can decide for a series of tasks to be executed sequentially
in the same core, so SRAM locality can be taken advantage of.
The job submission code was intially based on Panfrost.
Signed-off-by: Tomeu Vizoso
This uses the SHMEM DRM helpers and we map right away to the CPU and NPU
sides, as all buffers are expected to be accessed from both.
Signed-off-by: Tomeu Vizoso
---
drivers/accel/rocket/Makefile | 3 +-
drivers/accel/rocket/rocket_drv.c | 7 +++-
drivers/accel/rocket/rocket_gem.c | 68
See Chapter 36 "RKNN" from the RK3588 TRM (Part 1).
This is a derivative of NVIDIA's NVDLA, but with its own front-end
processor.
Mostly taken from downstream.
Signed-off-by: Tomeu Vizoso
---
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 53 +++
1 f
Enable the nodes added in a previous commit to the rk3588s device tree.
Signed-off-by: Tomeu Vizoso
---
arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts
b/arch/arm64/boot/dts
Add the bindings for the Neural Processing Unit IP from Rockchip.
Signed-off-by: Tomeu Vizoso
---
.../devicetree/bindings/npu/rockchip,rknn.yaml | 123 +
1 file changed, 123 insertions(+)
diff --git a/Documentation/devicetree/bindings/npu/rockchip,rknn.yaml
b
the DT.
This is needed by the IOMMU used by the NPU in the RK3588.
Signed-off-by: Tomeu Vizoso
---
drivers/iommu/rockchip-iommu.c | 36
1 file changed, 36 insertions(+)
diff --git a/drivers/iommu/rockchip-iommu.c b/drivers/iommu/rockchip-iommu.c
index
So far, seems to be fully compatible with the one in the RK3568.
The bindings already had this compatible, but the driver didn't
advertise it.
Signed-off-by: Tomeu Vizoso
---
drivers/iommu/rockchip-iommu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/iommu/rockchip-iomm
/mesa/mesa/-/merge_requests/29698
Signed-off-by: Tomeu Vizoso
---
Tomeu Vizoso (9):
iommu/rockchip: Add compatible for rockchip,rk3588-iommu
iommu/rockchip: Attach multiple power domains
dt-bindings: mailbox: rockchip,rknn: Add bindings
arm64: dts: rockchip: Add nodes for
On Tue, May 21, 2024 at 2:12 PM Daniel Vetter wrote:
>
> On Sat, May 18, 2024 at 10:46:01AM +0200, Tomeu Vizoso wrote:
> > Hi,
> >
> > I would like to use the chance at the next Plumbers to discuss the
> > present challenges related to ML accelerators in mainline.
&g
On Thu, May 23, 2024 at 8:35 AM Jacek Lawrynowicz
wrote:
>
> Hi,
>
> On 21.05.2024 17:10, Jeffrey Hugo wrote:
> > On 5/21/2024 8:41 AM, Tomeu Vizoso wrote:
> >> On Tue, May 21, 2024 at 2:12 PM Daniel Vetter wrote:
> >>>
> >>> On Sat, M
On Tue, May 21, 2024 at 2:12 PM Daniel Vetter wrote:
>
> On Sat, May 18, 2024 at 10:46:01AM +0200, Tomeu Vizoso wrote:
> > Hi,
> >
> > I would like to use the chance at the next Plumbers to discuss the
> > present challenges related to ML accelerators in mainline.
&g
On Fri, May 10, 2024 at 10:34 AM Lucas Stach wrote:
>
> Hi Tomeu,
>
> Am Mittwoch, dem 24.04.2024 um 08:37 +0200 schrieb Tomeu Vizoso:
> > If we expose a render node for NPUs without rendering capabilities, the
> > userspace stack will offer it to compositors and applic
Hi Lucas,
On Fri, May 10, 2024 at 10:34 AM Lucas Stach wrote:
>
> Hi Tomeu,
>
> Am Mittwoch, dem 24.04.2024 um 08:37 +0200 schrieb Tomeu Vizoso:
> > If we expose a render node for NPUs without rendering capabilities, the
> > userspace stack will offer it to composit
Hi,
I would like to use the chance at the next Plumbers to discuss the
present challenges related to ML accelerators in mainline.
I'm myself more oriented towards edge-oriented deployments, and don't
know enough about how these accelerators are being used in the cloud
(and maybe desktop?) to tell
Oded, Dave,
Do you have an opinion on this?
Thanks,
Tomeu
On Fri, Apr 26, 2024 at 8:10 AM Tomeu Vizoso wrote:
>
> On Thu, Apr 25, 2024 at 8:59 PM Jeffrey Hugo wrote:
> >
> > On 4/24/2024 12:37 AM, Tomeu Vizoso wrote:
> > > If we expose a render node for NPUs wit
On Thu, Apr 25, 2024 at 8:59 PM Jeffrey Hugo wrote:
>
> On 4/24/2024 12:37 AM, Tomeu Vizoso wrote:
> > If we expose a render node for NPUs without rendering capabilities, the
> > userspace stack will offer it to compositors and applications for
> > rendering, wh
away from a render node. What needs to be
> done
> on the userspace side?
Doesn't seem that bad, here is a proof of concept:
https://gitlab.freedesktop.org/tomeu/mesa/-/tree/teflon-accel
Thanks for taking a look.
Tomeu
> > Signed-off-by: Tomeu Vizoso
> > Cc: Oded Gabbay
&
and retry with an accel node.
Signed-off-by: Tomeu Vizoso
Cc: Oded Gabbay
---
drivers/gpu/drm/etnaviv/etnaviv_drv.c | 46 ++-
1 file changed, 38 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_drv.c
b/drivers/gpu/drm/etnaviv/etnaviv_d
Agreed, thanks for doing this, Christian.
Reviewed-by: Tomeu Vizoso
Cheers,
Tomeu
On Sat, Apr 20, 2024 at 3:41 PM Christian Gmeiner
wrote:
>
> From: Christian Gmeiner
>
> This reverts commit 1dccdba084897443d116508a8ed71e0ac8a031a4.
>
> In userspace a different approach
d increment the minor version too.
>
> Fixes: 4078a1186dd3 ("drm/etnaviv: update hwdb selection logic")
> Cc: sta...@vger.kernel.org
Oops.
Reviewed-by: Tomeu Vizoso
Cheers,
Tomeu
> Signed-off-by: Christian Gmeiner
> ---
> drivers/gpu/drm/etnaviv/etnaviv_drv.c |
These ones will be needed to make use fo the NN and TP units in the NPUs
based on Vivante IP.
Signed-off-by: Tomeu Vizoso
Acked-by: Christian Gmeiner
---
drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 20
drivers/gpu/drm/etnaviv/etnaviv_gpu.h | 12
drivers/gpu/drm
These ones will be needed to make use fo the NN and TP units in the NPUs
based on Vivante IP.
Also fix the number of NN cores in the VIPNano-qi.
Signed-off-by: Tomeu Vizoso
---
v2: Update a few chipspecs that I had missed before. (Christian)
---
drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 20
These ones will be needed to make use fo the NN and TP units in the NPUs
based on Vivante IP.
Also fix the number of NN cores in the VIPNano-qi.
Signed-off-by: Tomeu Vizoso
---
drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 20
drivers/gpu/drm/etnaviv/etnaviv_gpu.h | 12
intf(m, "\t pixel_pipes: %d\n",
gpu->identity.pixel_pipes);
seq_printf(m, "\t vertex_output_buffer_size: %d\n",
Hi Lucas,
That looks good to me.
Reviewed-by: Tomeu Vizoso
Cheers,
Tomeu
On 2/1/23 14:26, Lucas Stach wrote:
Hi Tomeu,
Am Donnerstag, dem 01.12.2022 um 11:30 +0100 schrieb Tomeu Vizoso:
This is a compute-only module marketed towards AI and vision
acceleration. This particular version can be found on the Amlogic A311D
SoC.
The feature bits are taken from the Khadas
This is a compute-only module marketed towards AI and vision
acceleration. This particular version can be found on the Amlogic A311D
SoC.
The feature bits are taken from the Khadas downstream kernel driver
6.4.4.3.310723AAA.
Signed-off-by: Tomeu Vizoso
---
drivers/gpu/drm/etnaviv
Userspace is still not making full use of the hardware, so we don't know
yet if changes to the UAPI won't be needed. Warn about it.
Signed-off-by: Tomeu Vizoso
---
drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/etnaviv/etn
We will use these for differentiating between GPUs and NPUs, as the
downstream driver does.
Signed-off-by: Tomeu Vizoso
---
drivers/gpu/drm/etnaviv/etnaviv_gpu.h | 3 +++
drivers/gpu/drm/etnaviv/etnaviv_hwdb.c | 4
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/etnaviv
)
Regards,
Tomeu
Tomeu Vizoso (8):
dt-bindings: reset: meson-g12a: Add missing NNA reset
dt-bindings: power: Add G12A NNA power domain
soc: amlogic: meson-pwrc: Add NNA power domain for A311D
arm64: dts: Add DT node for the VIPNano-QI on the A311D
drm/etnaviv: Add nn_core_count to chip feature
This is a compute-only module marketed towards AI and vision
acceleration. This particular version can be found on the Amlogic A311D
SoC.
The feature bits are taken from the Khadas downstream kernel driver
6.4.4.3.310723AAA.
Signed-off-by: Tomeu Vizoso
---
drivers/gpu/drm/etnaviv
Userspace is still not making full use of the hardware, so we don't know
yet if changes to the UAPI won't be needed. Warn about it.
Signed-off-by: Tomeu Vizoso
---
drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/etnaviv/etn
We will use these for differentiating between GPUs and NPUs, as the
downstream driver does.
Signed-off-by: Tomeu Vizoso
---
drivers/gpu/drm/etnaviv/etnaviv_gpu.h | 3 +++
drivers/gpu/drm/etnaviv/etnaviv_hwdb.c | 4
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/etnaviv
://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18986
v2: Move reference to RESET_NNA to npu node (Neil)
v3: Fix indentation mistake (Neil)
v4: Add warning when etnaviv probes on a NPU (Lucas)
v5: Reorder HWDB commit to be the last (Lucas)
Regards,
Tomeu
Tomeu Vizoso (7):
dt-bindings: reset: meson-g12a: Add
We will use these for differentiating between GPUs and NPUs, as the
downstream driver does.
Signed-off-by: Tomeu Vizoso
---
drivers/gpu/drm/etnaviv/etnaviv_gpu.h | 3 +++
drivers/gpu/drm/etnaviv/etnaviv_hwdb.c | 5 +
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/etnaviv
Userspace is still not making full use of the hardware, so we don't know
yet if changes to the UAPI won't be needed. Warn about it.
Signed-off-by: Tomeu Vizoso
---
drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/etnaviv/etn
This is a compute-only module marketed towards AI and vision
acceleration. This particular version can be found on the Amlogic A311D
SoC.
The feature bits are taken from the Khadas downstream kernel driver
6.4.4.3.310723AAA.
Signed-off-by: Tomeu Vizoso
---
drivers/gpu/drm/etnaviv
://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18986
v2: Move reference to RESET_NNA to npu node (Neil)
v3: Fix indentation mistake (Neil)
v4: Add warning when etnaviv probes on a NPU
Regards,
Tomeu
Tomeu Vizoso (7):
dt-bindings: reset: meson-g12a: Add missing NNA reset
dt-bindings: power: Add G12A NNA power
This is a compute-only module marketed towards AI and vision
acceleration. This particular version can be found on the Amlogic A311D
SoC.
The feature bits are taken from the Khadas downstream kernel driver
6.4.4.3.310723AAA.
Signed-off-by: Tomeu Vizoso
---
drivers/gpu/drm/etnaviv
://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18986
v2: Move reference to RESET_NNA to npu node (Neil)
v3: Fix indentation mistake (Neil)
Regards,
Tomeu
Tomeu Vizoso (5):
dt-bindings: reset: meson-g12a: Add missing NNA reset
dt-bindings: power: Add G12A NNA power domain
soc: amlogic: meson-pwrc: Add NNA
This is a compute-only module marketed towards AI and vision
acceleration. This particular version can be found on the Amlogic A311D
SoC.
The feature bits are taken from the Khadas downstream kernel driver
6.4.4.3.310723AAA.
Signed-off-by: Tomeu Vizoso
---
drivers/gpu/drm/etnaviv
://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18986
Regards,
Tomeu
Tomeu Vizoso (5):
dt-bindings: reset: meson-g12a: Add missing NNA reset
dt-bindings: power: Add NNA power domain
soc: amlogic: meson-pwrc: Add NNA power domain for A311D
arm64: dts: Add DT node for the VIPNano-QI on the A311D
drm
This is a compute-only module marketed towards AI and vision
acceleration. This particular version can be found on the Amlogic A311D
SoC.
The feature bits are taken from the Khadas downstream kernel driver
6.4.4.3.310723AAA.
Signed-off-by: Tomeu Vizoso
---
drivers/gpu/drm/etnaviv
Hi,
This series adds support for the Verisilicon VIPNano-QI NPU in the A311D
as in the VIM3 board.
The IP is very closeley based on previous Vivante GPUs, so the etnaviv
driver works basically unchanged.
Regards,
Tomeu
Tomeu Vizoso (6):
dt-bindings: reset: meson-g12a: Add missing NNA reset
ebase on top of latest drm-next
- Lower priority of LAVA jobs to not impact Mesa CI as much
- Update docs
v7:
- Rebase on top of latest drm-next
Signed-off-by: Tomeu Vizoso
Reviewed-by: Neil Armstrong
Reviewed-by: Rob Clark
---
Documentation/gpu/automated_testing.rst
ebase on top of latest drm-next
- Lower priority of LAVA jobs to not impact Mesa CI as much
- Update docs
Signed-off-by: Tomeu Vizoso
Reviewed-by: Neil Armstrong
Reviewed-by: Rob Clark
---
Documentation/gpu/automated_testing.rst | 86 +++
drivers/gpu/drm/ci/amdgpu-s
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