On Tue, Jun 24, 2025 at 3:27 PM Robin Murphy <robin.mur...@arm.com> wrote:
>
> On 2025-06-06 7:28 am, Tomeu Vizoso wrote:
> > Add the bindings for the Neural Processing Unit IP from Rockchip.
> >
> > v2:
> > - Adapt to new node structure (one node per core, each with its own
> > IOMMU)
> > - Several misc. fixes from Sebastian Reichel
> >
> > v3:
> > - Split register block in its constituent subblocks, and only require
> > the ones that the kernel would ever use (Nicolas Frattaroli)
> > - Group supplies (Rob Herring)
> > - Explain the way in which the top core is special (Rob Herring)
> >
> > v4:
> > - Change required node name to npu@ (Rob Herring and Krzysztof Kozlowski)
> > - Remove unneeded items: (Krzysztof Kozlowski)
> > - Fix use of minItems/maxItems (Krzysztof Kozlowski)
> > - Add reg-names to list of required properties (Krzysztof Kozlowski)
> > - Fix example (Krzysztof Kozlowski)
> >
> > v5:
> > - Rename file to rockchip,rk3588-rknn-core.yaml (Krzysztof Kozlowski)
> > - Streamline compatible property (Krzysztof Kozlowski)
> >
> > v6:
> > - Remove mention to NVDLA, as the hardware is only incidentally related
> > (Kever Yang)
> > - Mark pclk and npu clocks as required by all clocks (Rob Herring)
> >
> > v7:
> > - Remove allOf section, not needed now that all nodes require 4 clocks
> > (Heiko Stübner)
> >
> > Signed-off-by: Sebastian Reichel <sebastian.reic...@collabora.com>
> > Signed-off-by: Tomeu Vizoso <to...@tomeuvizoso.net>
> > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlow...@linaro.org>
> > ---
> > .../bindings/npu/rockchip,rk3588-rknn-core.yaml | 118
> > +++++++++++++++++++++
> > 1 file changed, 118 insertions(+)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml
> > b/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml
> > new file mode 100644
> > index
> > 0000000000000000000000000000000000000000..0588c085a723a34f4fa30a9680ea948d960b092f
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml
> > @@ -0,0 +1,118 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/npu/rockchip,rk3588-rknn-core.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Neural Processing Unit IP from Rockchip
> > +
> > +maintainers:
> > + - Tomeu Vizoso <to...@tomeuvizoso.net>
> > +
> > +description:
> > + Rockchip IP for accelerating inference of neural networks.
> > +
> > + There is to be a node per each core in the NPU. In Rockchip's design
> > there
> > + will be one core that is special because it is able to redistribute work
> > to
> > + the other cores by forwarding register writes and sharing data. This
> > special
> > + core is called the top core and should have the compatible string that
> > + corresponds to top cores.
>
> Say a future SoC, for scaling reasons, puts down two or more whole NPUs
> rather than just increasing the number of sub-cores in one? How is a DT
> consumer then going to know which "cores" are associated with which "top
> cores"? I think at the very least they want phandles in one direction or
> the other, but if there is a real functional hierarchy then I'd be
> strongly tempted to have the "core" nodes as children of their "top
> core", particularly since "forwarding register writes" sounds absolutely
> like something which could justify being represented as a "bus" in the
> DT sense.
Actually, I experimented with having the three cores as completely
independent units and things just work with how resources are
referenced in the DT nodes.
So I'm just having a top-level node per core with the same compatible.
Thanks,
Tomeu
> Thanks,
> Robin.
>
> > +
> > +properties:
> > + $nodename:
> > + pattern: '^npu@[a-f0-9]+$'
> > +
> > + compatible:
> > + enum:
> > + - rockchip,rk3588-rknn-core-top
> > + - rockchip,rk3588-rknn-core
> > +
> > + reg:
> > + maxItems: 3
> > +
> > + reg-names:
> > + items:
> > + - const: pc
> > + - const: cna
> > + - const: core
> > +
> > + clocks:
> > + maxItems: 4
> > +
> > + clock-names:
> > + items:
> > + - const: aclk
> > + - const: hclk
> > + - const: npu
> > + - const: pclk
> > +
> > + interrupts:
> > + maxItems: 1
> > +
> > + iommus:
> > + maxItems: 1
> > +
> > + npu-supply: true
> > +
> > + power-domains:
> > + maxItems: 1
> > +
> > + resets:
> > + maxItems: 2
> > +
> > + reset-names:
> > + items:
> > + - const: srst_a
> > + - const: srst_h
> > +
> > + sram-supply: true
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - reg-names
> > + - clocks
> > + - clock-names
> > + - interrupts
> > + - iommus
> > + - power-domains
> > + - resets
> > + - reset-names
> > + - npu-supply
> > + - sram-supply
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/rockchip,rk3588-cru.h>
> > + #include <dt-bindings/interrupt-controller/irq.h>
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > + #include <dt-bindings/power/rk3588-power.h>
> > + #include <dt-bindings/reset/rockchip,rk3588-cru.h>
> > +
> > + bus {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + npu@fdab0000 {
> > + compatible = "rockchip,rk3588-rknn-core-top";
> > + reg = <0x0 0xfdab0000 0x0 0x1000>,
> > + <0x0 0xfdab1000 0x0 0x1000>,
> > + <0x0 0xfdab3000 0x0 0x1000>;
> > + reg-names = "pc", "cna", "core";
> > + assigned-clocks = <&scmi_clk SCMI_CLK_NPU>;
> > + assigned-clock-rates = <200000000>;
> > + clocks = <&cru ACLK_NPU0>, <&cru HCLK_NPU0>,
> > + <&scmi_clk SCMI_CLK_NPU>, <&cru PCLK_NPU_ROOT>;
> > + clock-names = "aclk", "hclk", "npu", "pclk";
> > + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
> > + iommus = <&rknn_mmu_top>;
> > + npu-supply = <&vdd_npu_s0>;
> > + power-domains = <&power RK3588_PD_NPUTOP>;
> > + resets = <&cru SRST_A_RKNN0>, <&cru SRST_H_RKNN0>;
> > + reset-names = "srst_a", "srst_h";
> > + sram-supply = <&vdd_npu_mem_s0>;
> > + };
> > + };
> > +...
> >
>
