Hi,
Am Mittwoch, 28. Mai 2025, 09:17:13 Mitteleuropäische Sommerzeit schrieb Damon
Ding:
> On 2025/5/28 11:42, Stephen Rothwell wrote:
> > Hi all,
> >
> > After merging the drm-misc tree, today's linux-next build (arm
> > multi_v7_defconfig) failed like this:
> >
> > drivers/gpu/drm/bridge/anal
[resending to update to Dmitry's new address]
Am Sonntag, 2. März 2025, 09:30:43 Mitteleuropäische Sommerzeit schrieb Damon
Ding:
> With the commit f37952339cc2 ("drm/bridge: analogix_dp: handle clock via
> runtime PM"), the PM operations can help enable/disable the clock. The
> err_disable_clk l
Am Sonntag, 2. März 2025, 09:30:43 Mitteleuropäische Sommerzeit schrieb Damon
Ding:
> With the commit f37952339cc2 ("drm/bridge: analogix_dp: handle clock via
> runtime PM"), the PM operations can help enable/disable the clock. The
> err_disable_clk label and clk_disable_unprepare() operations are
Am Donnerstag, 15. Mai 2025, 17:54:20 Mitteleuropäische Sommerzeit schrieb
Krzysztof Kozlowski:
> On 15/05/2025 14:35, long.yunj...@zte.com.cn wrote:
> > From: Yumeng Fang
> >
> > In the probe path, dev_err() can be replaced with dev_err_probe()
>
> That's not probe path. I am not sure if you r
Hi,
Am Dienstag, 13. Mai 2025, 03:19:04 Mitteleuropäische Sommerzeit schrieb Chaoyi
Chen:
> From: Chaoyi Chen
> + ports:
> +$ref: /schemas/graph.yaml#/properties/ports
> +
> +properties:
> + port@0:
> +$ref: /schemas/graph.yaml#/properties/port
> +description: Input
Am Freitag, 9. Mai 2025, 09:34:47 Mitteleuropäische Sommerzeit schrieb Chaoyi
Chen:
> Hi Krzysztof,
>
> On 2025/5/9 15:11, Krzysztof Kozlowski wrote:
> > On 09/05/2025 09:02, Chaoyi Chen wrote:
> >> +
> >> + clock-names:
> >> +items:
> >> + - const: core-clk
> >> + - const: pclk
>
Am Donnerstag, 10. April 2025, 14:36:45 Mitteleuropäische Sommerzeit schrieb
Arnd Bergmann:
> On Wed, Apr 9, 2025, at 09:07, Arnd Bergmann wrote:
> > On Tue, Apr 8, 2025, at 19:51, Arnd Bergmann wrote:
> >> From: Arnd Bergmann
> >>
> >> clang-16 and earlier complain about what it thinks might be
Am Montag, 28. April 2025, 12:23:07 Mitteleuropäische Sommerzeit schrieb Andy
Yan:
> From: Andy Yan
>
> Convert it to drm bridge driver, it will be convenient for us to
> migrate the connector part to the display driver later.
>
> Note: I don't have the hardware to test this driver, so for now
Am Dienstag, 22. April 2025, 09:04:39 Mitteleuropäische Sommerzeit schrieb Andy
Yan:
> From: Andy Yan
>
> When preparing to convert the current inno hdmi driver into a
> bridge driver, I found that there are several issues currently
> existing with it:
>
> 1. When the system starts up, the firs
Hi Alex,
Am Dienstag, 22. April 2025, 09:04:39 Mitteleuropäische Sommerzeit schrieb Andy
Yan:
> From: Andy Yan
>
> When preparing to convert the current inno hdmi driver into a
> bridge driver, I found that there are several issues currently
> existing with it:
>
> 1. When the system starts up
Hi Andy,
Am Freitag, 14. März 2025, 08:57:47 Mitteleuropäische Sommerzeit schrieb Andy
Yan:
> From: Andy Yan
>
> It is not recommended for drivers to include UAPI header
> directly.
>
> Signed-off-by: Andy Yan
Reviewed-by: Heiko Stuebner
But looking at
scripts/get_maintainer.pl -
Hi Dan,
Am Mittwoch, 9. April 2025, 12:59:39 Mitteleuropäische Sommerzeit schrieb Dan
Carpenter:
> Commit e09be2a6ab1a ("HACK: drm/panel: ltk050h3146w: read panel-id")
that commit was accientially merged into my for-next branch but never
applied to any actual kernel branch (and is already gone a
Am Dienstag, 4. März 2025, 21:30:22 MEZ schrieb Dragan Simic:
> Hello Heiko,
>
> On 2025-03-04 13:44, Heiko Stuebner wrote:
> > diff --git a/drivers/gpu/drm/rockchip/rockchip_lvds.c
> > b/drivers/gpu/drm/rockchip/rockchip_lvds.c
> > index 385cf6881504..ecfae8d5da89 100644
> > --- a/drivers/gpu/drm
Am Dienstag, 4. März 2025, 12:46:59 MEZ schrieb Quentin Schulz:
> > @@ -465,14 +464,14 @@ static int rk3288_lvds_probe(struct platform_device
> > *pdev,
> >
> > lvds->pins->p = devm_pinctrl_get(lvds->dev);
> > if (IS_ERR(lvds->pins->p)) {
> > - DRM_DEV_ERROR(lvds->dev, "no pin
Hi Andy,
Am Dienstag, 18. Februar 2025, 12:28:58 MEZ schrieb Andy Yan:
> From: Andy Yan
>
> VOP2 on rk3576:
> Three video ports:
> VP0 Max 4096x2160
> VP1 Max 2560x1600
> VP2 Max 1920x1080
>
> 2 4K Cluster windows with AFBC/RFBC, line RGB and YUV
> 4 Esmart windows with line RGB/YUV support:
>
Hi Andy,
Am Dienstag, 18. Februar 2025, 12:27:34 MEZ schrieb Andy Yan:
> From: Andy Yan
>
> In the upcoming VOP of rk3576, a Window cannot attach to all Video Ports,
> so make sure all VP find it's suitable primary plane, then register the
> remain windows as overlay plane will make code easier.
Am Samstag, 1. März 2025, 10:11:54 MEZ schrieb Piotr Oniszczuk:
>
> > Wiadomość napisana przez Detlev Casanova w
> > dniu 25 lut 2025, o godz. 15:58:
> >
> > From what I see, the error is not present anymore on linux 6.14-rc4. I
> > tried
> > reverting your patch "ASoC: simple-card-utils.c: a
Am Freitag, 28. Februar 2025, 18:42:32 MEZ schrieb Quentin Schulz:
> Hi Heiko,
>
> On 2/28/25 5:57 PM, Heiko Stuebner wrote:
> > From: Heiko Stuebner
> >
> > Commit 52d11c863ac9 ("drm/rockchip: lvds: do not print scary message when
> > probing defer") already started hiding scary messages that a
Hi Greg,
Am Freitag, 21. Februar 2025, 07:14:07 MEZ schrieb Greg KH:
> On Fri, Feb 21, 2025 at 12:41:40AM +0100, Heiko Stuebner wrote:
> > The component helpers already expose the bound status in debugfs, but at
> > times it might be necessary to also check that state in the kernel and
> > act dif
Am Dienstag, 18. Februar 2025, 15:13:07 MEZ schrieb Sebastian Reichel:
> Hi,
>
> On Tue, Feb 18, 2025 at 08:17:46PM +0800, Jianfeng Liu wrote:
> > On Tue, 18 Feb 2025 11:00:57 +0100, Heiko Stübnerwrote:
> > >So I guess step1, check what error is actually returned.
> >
> > I have checked that the
Am Dienstag, 18. Februar 2025, 10:52:16 MEZ schrieb Jianfeng Liu:
> Hi Cristian,
>
> No matter one or two hdmi ports the rk3588 boards have, most of
> devicetrees in mainline kernel only have hdmi0 supported. After applying
> this patch their hdmi0 support is broken.
>
> So I recommend moving the
Am Montag, 17. Februar 2025, 03:44:37 MEZ schrieb Jianfeng Liu:
> Hi Cristian,
>
> On Sat, 15 Feb 2025 02:55:39 +0200, Cristian Ciocaltea wrote:
> >The HDMI1 PHY PLL clock source cannot be added directly to vop node in
> >rk3588-base.dtsi, along with the HDMI0 related one, because HDMI1 is an
> >o
Am Mittwoch, 12. Februar 2025, 10:34:59 MEZ schrieb Andy Yan:
> From: Andy Yan
>
> Now these two function share the same logic, the can
> be merged as one.
>
> Signed-off-by: Andy Yan
> ---
>
> (no changes since v1)
>
> drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 42 +---
>
Hi Andy,
Am Mittwoch, 12. Februar 2025, 10:34:57 MEZ schrieb Andy Yan:
> From: Andy Yan
>
> This help avoid "exceeds 100 columns" warning from checkpatch
>
> Signed-off-by: Andy Yan
I'm not much of a fan of "randomly" renaming individual constants
(especially when one is now named OFFS, while
Hi Detlev,
Am Donnerstag, 6. Februar 2025, 18:17:51 MEZ schrieb Detlev Casanova:
> On Tuesday, 4 February 2025 05:14:37 EST Quentin Schulz wrote:
> > This is an address/bus-less device, so I believe it needs to be put
> > among other address/bus-less devices, which for Rockchip SoCs is at the
> >
Hi Damon,
Am Donnerstag, 23. Januar 2025, 11:07:41 MEZ schrieb Damon Ding:
> Move drm_of_find_panel_or_bridge() a little later and combine it with
> component_add() into a new function rockchip_dp_link_panel(). The function
> will serve as done_probing() callback of devm_of_dp_aux_populate_bus(),
Hi Chris,
Am Montag, 30. Dezember 2024, 03:20:55 CET schrieb Chris Hofstaedtler:
> On Tue, Dec 10, 2024 at 12:10:19AM +0100, Heiko Stuebner wrote:
> > From: Heiko Stuebner
> >
> > Add a Synopsys Designware MIPI DSI host DRM bridge driver for their
> > DSI2 host controller, based on the Rockchip
Am Donnerstag, 9. Januar 2025, 15:57:13 CET schrieb Thomas Zimmermann:
> Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
> buffer size. Align the pitch to a multiple of 64.
>
> Signed-off-by: Thomas Zimmermann
> Cc: Sandy Huang
> Cc: "Heiko Stübner&
Am Montag, 6. Januar 2025, 09:35:26 CET schrieb Andy Yan:
>
> Hi Heiko,
>
> At 2025-01-02 19:51:58, "Heiko Stübner" wrote:
> >Hi Andy,
> >
> >Am Mittwoch, 25. Dezember 2024, 11:37:29 CET schrieb Andy Yan:
> >> From: Andy Yan
> >>
>
Hi Andy,
Am Dienstag, 31. Dezember 2024, 10:07:45 CET schrieb Andy Yan:
> From: Andy Yan
>
> The VOP interface mux, overlay, background delay cycle configuration
> of different SOC are much different. Add platform specific callback
> ops to let the core driver look cleaner and more refined.
>
>
Am Mittwoch, 25. Dezember 2024, 11:37:31 CET schrieb Andy Yan:
> From: Andy Yan
>
> The HDMI on RK3576 shares the same IP block (PHY and Controller)
> with rk3588.
> However, there are some control bits scattered in different GRF.
>
> Signed-off-by: Andy Yan
> Signed-off-by: Detlev Casanova
>
Hi Andy,
Am Mittwoch, 25. Dezember 2024, 11:37:29 CET schrieb Andy Yan:
> From: Andy Yan
>
> There are some control bits for IO and interrupts status scattered
> across different GRF on differt SOC.
> Add platform callback for this IO setting and interrupts status
> handling.
>
> Signed-off-by:
Hi Andy,
Am Sonntag, 29. Dezember 2024, 07:48:36 CET schrieb Andy Yan:
>
> Hi Heiko,
>
> At 2024-12-29 02:36:36, "Heiko Stübner" wrote:
> >Hi Andy,
> >
> >Am Samstag, 28. Dezember 2024, 13:21:43 CET schrieb Andy Yan:
> >> From: Andy Yan
>
Hi Andy,
Am Samstag, 28. Dezember 2024, 13:21:43 CET schrieb Andy Yan:
> From: Andy Yan
>
>
> As the VOP[0] and HDMI[1] driver have already been submitted for review.
> This series send all display related device tree part together.
> [0]
> https://lore.kernel.org/linux-rockchip/20241219073931
Hi Damon,
Am Montag, 16. Dezember 2024, 04:12:25 CET schrieb Damon Ding:
> The related nodes are hdptxphy1_grf, hdptxphy1 and edp1. And the
> aliases edp0 and edp1 are added to separate two independent eDP
> devices.
>
> Signed-off-by: Damon Ding
> ---
> .../arm64/boot/dts/rockchip/rk3588-extra
Hi Damon,
Am Montag, 16. Dezember 2024, 04:12:18 CET schrieb Damon Ding:
> Add basic support for RBR/HBR/HBR2 link rates, and the voltage swing and
> pre-emphasis configurations of each link rate have been verified according
> to the eDP 1.3 requirements.
>
> Signed-off-by: Damon Ding
>
> ---
>
Am Montag, 16. Dezember 2024, 09:57:41 CET schrieb Dmitry Baryshkov:
> On Mon, Dec 16, 2024 at 11:12:17AM +0800, Damon Ding wrote:
> > RK3588 integrates the analogix eDP 1.3 TX controller IP and the HDMI/eDP
> > TX Combo PHY based on a Samsung IP block, and there are also two
> > independent eDP di
Am Mittwoch, 11. Dezember 2024, 18:47:44 CET schrieb Maxime Ripard:
> On Wed, Dec 11, 2024 at 06:23:03PM +0100, Heiko Stübner wrote:
> > Am Mittwoch, 11. Dezember 2024, 18:07:57 CET schrieb Maxime Ripard:
> > > On Wed, Dec 11, 2024 at 12:15:07PM +0200, Cristian Ciocaltea wrote:
Am Mittwoch, 11. Dezember 2024, 18:07:57 CET schrieb Maxime Ripard:
> On Wed, Dec 11, 2024 at 12:15:07PM +0200, Cristian Ciocaltea wrote:
> > The RK3588 specific implementation is currently quite limited in terms
> > of handling the full range of display modes supported by the connected
> > screens
Hi Andy,
Am Mittwoch, 11. Dezember 2024, 08:07:21 CET schrieb Andy Yan:
> At 2024-12-10 19:57:44, "Heiko Stübner" wrote:
> >Am Montag, 9. Dezember 2024, 13:29:13 CET schrieb Andy Yan:
> >> From: Andy Yan
> >>
> >> /sys/kernel/debug/dri/vop2/sum
Hi Cristian,
Am Mittwoch, 11. Dezember 2024, 00:06:13 CET schrieb Cristian Ciocaltea:
> The patches provide the basic support to handle the second HDMI output
> port found on Rockchip RK3588 SoC.
>
> For now I enabled it on Radxa ROCK 5B only, the board I've been using to
> validate this.
>
> **
Am Montag, 9. Dezember 2024, 13:33:29 CET schrieb Andy Yan:
> From: Andy Yan
>
> There is a version number hardcoded in the VOP VERSION_INFO
> register, and the version number increments sequentially based
> on the production order of the SOC.
>
> So using this version number to distinguish diff
, 10 Dec 2024 at 03:22, Andy Yan wrote:
> >> >> 在 2024-12-10 09:01:38,"Dmitry Baryshkov"
> >> >> 写道:
> >> >> >On Tue, Dec 10, 2024 at 08:50:51AM +0800, Andy Yan wrote:
> >> >> >> At 2024-12-10 07:12:26, "Heiko Stübne
Hi Andy,
Am Montag, 9. Dezember 2024, 13:29:13 CET schrieb Andy Yan:
> From: Andy Yan
>
> /sys/kernel/debug/dri/vop2/summary: dump vop display state
> /sys/kernel/debug/dri/vop2/regs: dump whole vop registers
> /sys/kernel/debug/dri/vop2/active_regs: only dump the registers of
> activated modul
2-10 09:01:38,"Dmitry Baryshkov" 写道:
> >> >On Tue, Dec 10, 2024 at 08:50:51AM +0800, Andy Yan wrote:
> >> >>
> >> >>
> >> >> Hi,
> >> >>
> >> >> At 2024-12-10 07:12:26, "Heiko Stübner"
Am Montag, 9. Dezember 2024, 17:11:03 CET schrieb Diederik de Haas:
> Hi,
>
> On Mon Dec 9, 2024 at 4:06 PM CET, Daniel Semkowicz wrote:
> > On 03.12.24 21:54, Heiko Stuebner wrote:
> > > This series adds a bridge and glue driver for the DSI2 controller found
> > > in the rk3588 soc from Rockchip,
Hi Daemon,
Am Mittwoch, 27. November 2024, 08:51:47 CET schrieb Damon Ding:
> These patchs have been tested with a 1536x2048p60 eDP panel on
> RK3588S EVB1 board, and HDMI 1080P/4K display also has been verified
> on RK3588 EVB1 board.
>
> Patch 1~3 are the RK3588 eDP support of Rockchip analogix
Hi Piotr,
Am Mittwoch, 4. Dezember 2024, 16:45:21 CET schrieb Piotr Zalewski:
> I just noticed that after coming out of suspend gamma LUT is lost and must
> be rewritten by userspace.
>
> So I guess it will be needed to save LUT to a buffer and rewrite it after
> going out of suspend during modes
Hi Damon,
Am Freitag, 29. November 2024, 03:43:57 CET schrieb Damon Ding:
> On 2024/11/27 19:04, Heiko Stübner wrote:
> > Am Mittwoch, 27. November 2024, 12:00:10 CET schrieb Damon Ding:
> >> On 2024/11/27 17:29, Heiko Stübner wrote:
> >>> Am Mittwoch, 27. Novem
Hi Damon,
Am Mittwoch, 27. November 2024, 12:00:10 CET schrieb Damon Ding:
> Hi Heiko:
>
> On 2024/11/27 17:29, Heiko Stübner wrote:
> > Hi Damon,
> >
> > Am Mittwoch, 27. November 2024, 08:51:51 CET schrieb Damon Ding:
> >> Add basic support for RBR/HBR/HB
Hi Damon,
Am Mittwoch, 27. November 2024, 08:51:51 CET schrieb Damon Ding:
> Add basic support for RBR/HBR/HBR2 link rates, and the voltage swing and
> pre-emphasis configurations of each link rate have been verified according
> to the eDP 1.3 requirements.
>
> Signed-off-by: Damon Ding
> ---
[
Hi Damon,
Am Mittwoch, 27. November 2024, 08:51:57 CET schrieb Damon Ding:
> Add the necessary DT changes to enable eDP0 on RK3588S EVB1 board.
>
> Signed-off-by: Damon Ding
> ---
> .../boot/dts/rockchip/rk3588s-evb1-v10.dts| 84 +++
> 1 file changed, 84 insertions(+)
>
> d
Hi,
Am Mittwoch, 6. November 2024, 14:54:39 CET schrieb neil.armstr...@linaro.org:
> > +#define UPDATE(v, h, l)(((v) << (l)) & GENMASK((h),
> > (l)))
>
> I'm not super fan of this macro, overall I thinkg you should switch to
> regmap and make use of regmap_update_bits and dro
Hi,
Am Mittwoch, 6. November 2024, 14:33:25 CET schrieb Diederik de Haas:
> > +#define IPI_DEPTH_5_6_5_BITS 0x02
> > +#define IPI_DEPTH_6_BITS 0x03
> > +#define IPI_DEPTH_8_BITS 0x05
> > +#define IPI_DEPTH_10_BITS 0x06
>
> Possibly dumb remark (sorry):
>
Hi Detlev,
Am Freitag, 8. November 2024, 19:50:39 CET schrieb Detlev Casanova:
> At the end of initialization, each VP clock needs to be reset before
> they can be used.
>
> Failing to do so can put the VOP in an undefined state where the
> generated HDMI signal is either lost or not matching the
Hi Detlev,
Am Freitag, 8. November 2024, 19:50:38 CET schrieb Detlev Casanova:
> Detlev Casanova (3):
> vop2: Add clock resets support
> arm64: dts: rockchip: Add VOP clock resets for rk3588s
> dt-bindings: display: vop2: Add VP clock resets
while it isn't that important for this short seri
Am Freitag, 8. November 2024, 16:21:24 CET schrieb Diederik de Haas:
> On Fri Nov 8, 2024 at 3:44 PM CET, Heiko Stuebner wrote:
> > From: Heiko Stuebner
> >
> > DRM_DEV_ERROR is deprecated and using dev_err_probe saves quite a number
> > of lines too, so convert the error prints for the dsi-driver
Am Freitag, 8. November 2024, 15:13:33 CET schrieb Dragan Simic:
> On 2024-11-08 15:09, Heiko Stübner wrote:
> > Am Freitag, 8. November 2024, 15:05:02 CET schrieb Dragan Simic:
> >> On 2024-11-08 14:56, Heiko Stübner wrote:
> >> > Am Freitag, 8. November 2024, 14:
Am Freitag, 8. November 2024, 15:05:02 CET schrieb Dragan Simic:
> Hello Heiko,
>
> On 2024-11-08 14:56, Heiko Stübner wrote:
> > Am Freitag, 8. November 2024, 14:53:57 CET schrieb Dragan Simic:
> >> Perform a few trivial code cleanups, to make one logged message a bit
&
Hey Dragan,
Am Freitag, 8. November 2024, 14:53:57 CET schrieb Dragan Simic:
> Perform a few trivial code cleanups, to make one logged message a bit more
> consistent with the other logged messages by capitalizing its first word, and
> to avoid line wrapping by using the 100-column width better.
>
Am Freitag, 20. September 2024, 12:28:02 CEST schrieb Liviu Dudau:
> Since 641bb4394f40 ("fs: move FMODE_UNSIGNED_OFFSET to fop_flags")
> the FMODE_UNSIGNED_OFFSET flag has been moved to fop_flags and renamed,
> but the patch failed to make the changes for the panthor driver.
> When user space open
Am Dienstag, 10. September 2024, 18:39:54 CEST schrieb Heiko Stübner:
> Am Dienstag, 10. September 2024, 17:41:42 CEST schrieb Cristian Ciocaltea:
> > On 9/10/24 6:21 PM, Heiko Stübner wrote:
> > > Am Dienstag, 10. September 2024, 17:07:57 CEST schrieb Heiko Stübner:
&g
Am Freitag, 6. September 2024, 03:17:42 CEST schrieb Cristian Ciocaltea:
> The RK3588 SoC family integrates the newer Synopsys DesignWare HDMI 2.1
> Quad-Pixel (QP) TX controller IP and a HDMI/eDP TX Combo PHY based on a
> Samsung IP block.
>
> Add just the basic support for now, i.e. RGB output u
Am Dienstag, 10. September 2024, 17:41:42 CEST schrieb Cristian Ciocaltea:
> On 9/10/24 6:21 PM, Heiko Stübner wrote:
> > Am Dienstag, 10. September 2024, 17:07:57 CEST schrieb Heiko Stübner:
> >> Am Freitag, 6. September 2024, 03:17:42 CEST schrieb Cristian Ciocaltea:
> >
Am Dienstag, 10. September 2024, 17:07:57 CEST schrieb Heiko Stübner:
> Am Freitag, 6. September 2024, 03:17:42 CEST schrieb Cristian Ciocaltea:
> > The RK3588 SoC family integrates the newer Synopsys DesignWare HDMI 2.1
> > Quad-Pixel (QP) TX controller IP and a HDMI/eDP TX Combo
Am Freitag, 6. September 2024, 03:17:42 CEST schrieb Cristian Ciocaltea:
> The RK3588 SoC family integrates the newer Synopsys DesignWare HDMI 2.1
> Quad-Pixel (QP) TX controller IP and a HDMI/eDP TX Combo PHY based on a
> Samsung IP block.
>
> Add just the basic support for now, i.e. RGB output u
Am Freitag, 6. September 2024, 03:17:42 CEST schrieb Cristian Ciocaltea:
> The RK3588 SoC family integrates the newer Synopsys DesignWare HDMI 2.1
> Quad-Pixel (QP) TX controller IP and a HDMI/eDP TX Combo PHY based on a
> Samsung IP block.
>
> Add just the basic support for now, i.e. RGB output u
Hi Andi,
Am Dienstag, 3. September 2024, 17:46:00 CEST schrieb Andi Shyti:
> On Tue, Sep 03, 2024 at 11:22:33AM GMT, Detlev Casanova wrote:
> > Just like RK356x and RK3588, RK3576 is compatible to the existing
> > rk3399 binding.
> >
> > Signed-off-by: Detlev Casanova
> > Acked-by: Krzysztof Koz
Am Dienstag, 3. September 2024, 18:47:17 CEST schrieb Andi Shyti:
> On Tue, Sep 03, 2024 at 11:59:34AM GMT, Detlev Casanova wrote:
> > On Tuesday, 3 September 2024 11:46:00 EDT Andi Shyti wrote:
> > > Hi,
> > >
> > > On Tue, Sep 03, 2024 at 11:22:33AM GMT, Detlev Casanova wrote:
> > > > Just like
Hi,
Am Samstag, 31. August 2024, 08:16:26 CEST schrieb Krzysztof Kozlowski:
> On Sat, Aug 31, 2024 at 12:55:29AM +0300, Cristian Ciocaltea wrote:
> > + clocks:
> > +minItems: 4
> > +maxItems: 6
> > +items:
> > + - description: Peripheral/APB bus clock
> > + - description: E
Hi Guenter,
Am Dienstag, 27. August 2024, 21:38:35 CEST schrieb Guenter Roeck:
> On 8/27/24 00:20, Heiko Stübner wrote:
> > Am Samstag, 24. August 2024, 18:44:29 CEST schrieb Guenter Roeck:
> >> On Fri, Aug 23, 2024 at 10:52:36AM -0400, Detlev Casanova wrote:
> >>> I
Hi Guenter,
Am Samstag, 24. August 2024, 18:44:29 CEST schrieb Guenter Roeck:
> On Fri, Aug 23, 2024 at 10:52:36AM -0400, Detlev Casanova wrote:
> > It is compatible with the other rockchip SoCs.
> >
> > Signed-off-by: Detlev Casanova
>
> Acked-by: Guenter Roeck
For my understanding, does thi
Am Donnerstag, 22. August 2024, 10:41:10 CEST schrieb Conor Dooley:
> On Thu, Aug 22, 2024 at 09:01:34AM +0200, Heiko Stübner wrote:
> > @Conor: just for me, did some shift happen in our understanding of dt-
> > best-practices in terms of syscon via phandle vs. syscon
Am Freitag, 23. August 2024, 11:20:49 CEST schrieb Jinjie Ruan:
> Avoids the need for manual cleanup of_node_put() in early exits
> from the loop.
>
> Signed-off-by: Jinjie Ruan
Not sure if this should go in in one part or individually, but anyway
Reviewed-by: Heiko Stuebner
> drivers/gpu/dr
Am Donnerstag, 22. August 2024, 01:22:16 CEST schrieb Cristian Ciocaltea:
> On 8/22/24 12:38 AM, Heiko Stuebner wrote:
> >
> >
> > Am 21. August 2024 23:28:55 MESZ schrieb Conor Dooley :
> >> Cristian, Heiko,
> >>
> >> On Wed, Aug 21, 2024 at 11:38:01PM +0300, Cristian Ciocaltea wrote:
> >>> On 8
Am Montag, 19. August 2024, 10:02:23 CEST schrieb Mary Guillemard:
> Extend the uAPI with a new job requirement flag for cycle
> counters. This requirement is used by userland to indicate that a job
> requires cycle counters or system timestamp to be propagated. (for use
> with write value timestam
Am Montag, 19. August 2024, 10:02:22 CEST schrieb Mary Guillemard:
> Expose system timestamp and frequency supported by the GPU.
>
> Mali uses an external timer as GPU system time. On ARM, this is wired to
> the generic arch timer so we wire cntfrq_el0 as device frequency.
>
> This new uAPI will
Am Montag, 19. August 2024, 13:25:08 CEST schrieb Mary Guillemard:
> Expose timestamp information supported by the GPU with a new device
> query.
>
> Mali uses an external timer as GPU system time. On ARM, this is wired to
> the generic arch timer so we wire cntfrq_el0 as device frequency.
>
> Th
mermann
> Cc: Sandy Huang
> Cc: "Heiko Stübner"
> Cc: Andy Yan
I've looked up the whole patchseries and while I can't say overly much
about the core changes, at least for the Rockchip driver, things look
like they'll stay the same even after t
Am Donnerstag, 15. August 2024, 19:26:54 CEST schrieb Cristian Ciocaltea:
> On 8/15/24 5:21 PM, Heiko Stübner wrote:
> > Am Donnerstag, 8. August 2024, 13:58:02 CEST schrieb Cristian Ciocaltea:
> >> Move rockchip_drm_platform_driver unregistration after its sub-drivers,
>
Am Donnerstag, 8. August 2024, 13:58:02 CEST schrieb Cristian Ciocaltea:
> Move rockchip_drm_platform_driver unregistration after its sub-drivers,
> which ensures all drivers are unregistered in the reverse order used
> when they were registered.
are you sure about that?
I.e. currently rockchip_d
Am Mittwoch, 7. August 2024, 13:07:22 CEST schrieb Cristian Ciocaltea:
> The Rockchip RK3588 SoC family integrates the Synopsys DesignWare HDMI
> 2.1 Quad-Pixel (QP) TX controller, which is a new IP block, quite
> different from those used in the previous generations of Rockchip SoCs.
>
> The cont
Hi,
Am Montag, 12. August 2024, 14:28:15 CEST schrieb Mary Guillemard:
> Expose timestamp information supported by the GPU with a new device
> query.
>
> Mali uses an external timer as GPU system time. On ARM, this is wired to
> the generic arch timer so we wire cntfrq_el0 as device frequency.
>
Am Donnerstag, 4. Juli 2024, 11:09:00 CEST schrieb Diederik de Haas:
> On Friday, 22 April 2022 09:28:26 CEST Sascha Hauer wrote:
> > The RK3568 has HDMI_TX_AVDD0V9 and HDMI_TX_AVDD_1V8 supply inputs needed
> > for the HDMI port. add support for these to the driver for boards which
> > have them su
Am Samstag, 15. Juni 2024, 19:03:53 CEST schrieb Jonas Karlman:
> Similar to DCLK_LCDC on RK3328, the DCLK_VOP on RK3228 is typically
> parented by the hdmiphy clk and it is expected that the DCLK_VOP and
> hdmiphy clk rate are kept in sync.
>
> Use CLK_SET_RATE_PARENT and CLK_SET_RATE_NO_REPARENT
Am Freitag, 3. Mai 2024, 17:11:15 CEST schrieb Lucas Stach:
> Currently the AUX channel support in the Analogix DP driver is severely
> limited as the AUX block of the bridge is only initialized when the video
> link is to be enabled. This is okay for the purposes of link training,
> but does not a
Am Freitag, 3. Mai 2024, 17:11:17 CEST schrieb Lucas Stach:
> Hook up the runtime PM suspend/resume paths to make the rockchip
> glue behave more like the exynos one. The same suspend/resume
> functions are used for system sleep via the runtime PM force
> suspend/resume.
>
> Signed-off-by: Lucas S
Am Donnerstag, 6. Juni 2024, 11:53:23 CEST schrieb Cristian Ciocaltea:
> On 6/5/24 5:48 PM, Heiko Stübner wrote:
> > Am Samstag, 1. Juni 2024, 15:12:35 CEST schrieb Cristian Ciocaltea:
> >> The Synopsys DesignWare HDMI 2.1 Quad-Pixel (QP) TX controller supports
> >> th
Am Mittwoch, 5. Juni 2024, 21:58:23 CEST schrieb Luis de Arquer:
> On 6/5/24 16:48, Heiko Stübner wrote:
> > Without this change, connecting to a DVI display does not work, and
> > reading the EDID ends in the "i2c read error" below.
>
> I had a lot of problems init
Am Samstag, 1. Juni 2024, 15:12:35 CEST schrieb Cristian Ciocaltea:
> The Synopsys DesignWare HDMI 2.1 Quad-Pixel (QP) TX controller supports
> the following features, among others:
>
> * Fixed Rate Link (FRL)
> * 4K@120Hz and 8K@60Hz video modes
> * Variable Refresh Rate (VRR) including Quick Med
Am Sonntag, 2. Juni 2024, 17:57:12 CEST schrieb Andy Shevchenko:
> Make two APIs look similar. Hence convert match_string() to be
> a 2-argument macro. In order to avoid unneeded churn, convert
> all users as well. There is no functional change intended.
>
> Signed-off-by: Andy Shevchenko
> ---
>
Am Mittwoch, 29. Mai 2024, 17:55:25 CEST schrieb Diederik de Haas:
> On Thursday, 25 April 2024 17:19:58 CEST Heiko Stuebner wrote:
> > On Mon, 22 Apr 2024 18:19:04 +0800, Andy Yan wrote:
> > > From: Andy Yan
> > >
> > > The port mux bits of VP2 should be defined by
> > > RK3568_OVL_PORT_SET__POR
Hey,
Am Dienstag, 28. Mai 2024, 00:13:59 CEST schrieb Val Packett:
> On Mon, May 27 2024 at 22:43:18 +02:00:00, Heiko Stübner
> wrote:
> > Am Montag, 27. Mai 2024, 09:16:33 CEST schrieb Val Packett:
> >> On the RK3066, there is a bit that must be cleared, otherwise
>
Hi Val,
Am Montag, 27. Mai 2024, 09:16:33 CEST schrieb Val Packett:
> On the RK3066, there is a bit that must be cleared, otherwise
> the picture does not show up on the display (at least for RGB).
>
> Fixes: f4a6de8 ("drm: rockchip: vop: add rk3066 vop definitions")
> Cc: sta...@vger.kernel.org
Hi Alex,
Am Dienstag, 21. Mai 2024, 12:58:07 CEST schrieb keith:
> Verisilicon/DC8200 display controller IP has 2 display pipes and each
> pipe support a primary plane and a cursor plane .
> In addition, there are four overlay planes as two display pipes common
> resources.
>
> The first displ
Am Mittwoch, 15. Mai 2024, 18:19:29 CEST schrieb Conor Dooley:
> On Tue, May 14, 2024 at 11:19:47AM -0400, Detlev Casanova wrote:
> > Add the documentation for VOP2 video ports reset clocks.
> > One reset can be set per video port.
> >
> > Signed-off-by: Detlev Casanova
>
> Are these resets vali
Hi Alex,
Am Donnerstag, 9. Mai 2024, 14:07:08 CEST schrieb Alex Bee:
> This series aims to add support for the DesignWare MIPI DSI controller and
> the Innoslicon D-PHY found in RK3128 SoCs. The code additions are rather
> tiny: It only need some code in the Rockchip dw-mipi-dsi glue layer for
> t
] https://lore.kernel.org/r/20230921192749.1542462-1-diand...@chromium.org
>
> Cc: "Heiko Stübner"
> Signed-off-by: Douglas Anderson
the underlying setup (rockchip-drm with dw-dsi) as well as the
change itself is similar to the ltk050h3146w variant, so I don't
see how this should behave differently ;-)
Reviewed-by: Heiko Stuebner
ed/enabled state. Even if someone was relying on the
> double-check before, that double-check is now in the core and not
> needed in individual drivers.
>
> Cc: "Heiko Stübner"
> Signed-off-by: Douglas Anderson
the underlying setup (rockchip-drm with dw-dsi) as well as t
mium.org
> [2] https://lore.kernel.org/r/20230901234202.566951-1-diand...@chromium.org
> [3] https://lore.kernel.org/r/20230921192749.1542462-1-diand...@chromium.org
>
> Cc: "Heiko Stübner"
> Signed-off-by: Douglas Anderson
the underlying setup (rockchip-drm with dw-dsi) as w
1 - 100 of 453 matches
Mail list logo