Am Sonntag, 13. Juli 2025, 10:38:58 Mitteleuropäische Sommerzeit schrieb Tomeu
Vizoso:
> See Chapter 36 "RKNN" from the RK3588 TRM (Part 1).
>
> The IP is divided in three cores, programmed independently. The first
> core though is special, being able to delegate work to the other cores.
>
> The IOMMU of the first core is also special in that it has two subunits
> (read/write?) that need to be programmed in sync.
>
> v2:
> - Have one device for each NPU core (Sebastian Reichel)
> - Have one device for each IOMMU (Sebastian Reichel)
> - Correctly sort nodes (Diederik de Haas)
> - Add rockchip,iommu compatible to IOMMU nodes (Sebastian Reichel)
>
> v3:
> - Adapt to a split of the register block in the DT bindings (Nicolas
> Frattaroli)
>
> v4:
> - Adapt to changes in bindings
>
> v6:
> - pclk and npu clocks are needed by all clocks (Rob Herring)
>
> v8:
> - Remove notion of top core (Robin Murphy)
>
> Tested-by: Heiko Stuebner <he...@sntech.de>
> Signed-off-by: Tomeu Vizoso <to...@tomeuvizoso.net>
> ---
> arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 91
> +++++++++++++++++++++++++++
> 1 file changed, 91 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
> b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
> index
> 1eddc69fd9c9ed95cdc810ba48d9683e3f82489a..dbd472feaa8b3f8c14597a48a4f5afbe3cb45b6a
> 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
> @@ -1140,6 +1140,97 @@ power-domain@RK3588_PD_SDMMC {
> };
> };
>
> + rknn_core_0: npu@fdab0000 {
> + compatible = "rockchip,rk3588-rknn-core";
> + reg = <0x0 0xfdab0000 0x0 0x1000>,
> + <0x0 0xfdab1000 0x0 0x1000>,
> + <0x0 0xfdab3000 0x0 0x1000>;
> + reg-names = "pc", "cna", "core";
> + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&cru ACLK_NPU0>, <&cru HCLK_NPU0>,
> + <&scmi_clk SCMI_CLK_NPU>, <&cru PCLK_NPU_ROOT>;
> + clock-names = "aclk", "hclk", "npu", "pclk";
> + assigned-clocks = <&scmi_clk SCMI_CLK_NPU>;
> + assigned-clock-rates = <200000000>;
> + resets = <&cru SRST_A_RKNN0>, <&cru SRST_H_RKNN0>;
> + reset-names = "srst_a", "srst_h";
> + power-domains = <&power RK3588_PD_NPUTOP>;
> + iommus = <&rknn_mmu_top>;
> + status = "disabled";
> + };
> +
> + rknn_mmu_top: iommu@fdab9000 {
nit: phandle for the mmu should probably also follow the naming change?
I.e. become rknn_mmu_0 ?
> + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
> + reg = <0x0 0xfdab9000 0x0 0x100>,
> + <0x0 0xfdaba000 0x0 0x100>;
> + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&cru ACLK_NPU0>, <&cru HCLK_NPU0>;
> + clock-names = "aclk", "iface";
> + #iommu-cells = <0>;
> + power-domains = <&power RK3588_PD_NPUTOP>;
> + status = "disabled";
> + };
