Am Freitag, 6. September 2024, 03:17:42 CEST schrieb Cristian Ciocaltea:
> The RK3588 SoC family integrates the newer Synopsys DesignWare HDMI 2.1
> Quad-Pixel (QP) TX controller IP and a HDMI/eDP TX Combo PHY based on a
> Samsung IP block.
>
> Add just the basic support for now, i.e. RGB output up to 4K@60Hz,
> without audio, CEC or any of the HDMI 2.1 specific features.
>
> Co-developed-by: Algea Cao <algea....@rock-chips.com>
> Signed-off-by: Algea Cao <algea....@rock-chips.com>
> Tested-by: Heiko Stuebner <he...@sntech.de>
> Signed-off-by: Cristian Ciocaltea <cristian.ciocal...@collabora.com>
[...]
> diff --git a/drivers/gpu/drm/rockchip/Makefile
> b/drivers/gpu/drm/rockchip/Makefile
> index 3ff7b21c0414..3eab662a5a1d 100644
> --- a/drivers/gpu/drm/rockchip/Makefile
> +++ b/drivers/gpu/drm/rockchip/Makefile
> @@ -11,6 +11,7 @@ rockchipdrm-$(CONFIG_ROCKCHIP_VOP) += rockchip_drm_vop.o
> rockchip_vop_reg.o
> +static int dw_hdmi_qp_rockchip_bind(struct device *dev, struct device
> *master,
> + void *data)
> +{
> + static const char * const clk_names[] = {
> + "pclk", "earc", "aud", "hdp", "hclk_vo1",
> + "ref" /* keep "ref" last */
> + };
[...]
> + for (i = 0; i < ARRAY_SIZE(clk_names); i++) {
> + clk = devm_clk_get_enabled(hdmi->dev, clk_names[i]);
> +
> + if (IS_ERR(clk)) {
> + ret = PTR_ERR(clk);
> + if (ret != -EPROBE_DEFER)
> + drm_err(hdmi, "Failed to get %s clock: %d\n",
> + clk_names[i], ret);
> + return ret;
> + }
> + }
> + hdmi->ref_clk = clk;
How about using devm_clk_bulk_get_all_enable() for everything except the
refclk and a separate call to devm_clk_get_enabled() for that refclk .
That hdmi->ref_clk just accidentially falls out of that loop at the end
looks somewhat strange, so getting and keeping that refclk
separately would make this look cleaner.
