Hi Prabhakar,
> -Original Message-
> From: Prabhakar
> Sent: 30 May 2025 17:59
> Subject: [PATCH v6 02/12] drm: renesas: rz-du: Add support for RZ/V2H(P) SoC
>
> From: Lad Prabhakar
>
> The LCD controller (LCDC) on the RZ/V2H(P) SoC is composed of Frame
> Compression Processor (FCPVD)
On Wed, May 28, 2025 at 08:01:21PM +, Juston Li wrote:
On Wed, 2025-05-28 at 18:34 +, Juston Li wrote:
On Thu, 2025-05-22 at 16:14 +0100, Tvrtko Ursulin wrote:
>
> On 22/05/2025 15:50, Lucas De Marchi wrote:
> > + dri-devel
> >
> > On Wed, May 21, 2025 at 10:42:35PM +, Juston Li wrot
M: David Lechner
S: Maintained
T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
-F: Documentation/devicetree/bindings/display/sitronix,st7586.txt
+F: Documentation/devicetree/bindings/display/sitronix,st7586.yaml
F: drivers/gpu/drm/sitronix/st7586.c
DRM DRIVER FOR SITRON
On Thu, 2025-05-29 at 21:30 +, Timur Tabi wrote:
> On Wed, 2025-05-21 at 15:45 +0900, Alexandre Courbot wrote:
>
> I noticed something interesting in this change to Gpu::new().
>
> > + // Check that the WPR2 region does not already exists - if it
> > does, the GPU needs to be
> > +
On Wed, 2025-05-21 at 15:45 +0900, Alexandre Courbot wrote:
> +// To be removed once that code is used.
> +#[expect(dead_code)]
FWIW - I think most people will understand what the #[expect(dead_code)] bits
are for with or without the comment.
Regardless:
Reviewed-by: Lyude Paul
--
Cheers,
Ly
Some comments down below
On Wed, 2025-05-21 at 15:45 +0900, Alexandre Courbot wrote:
> Add the common Falcon code and HAL for Ampere GPUs, and instantiate the
> GSP and SEC2 Falcons that will be required to boot the GSP.
>
> Signed-off-by: Alexandre Courbot
> ---
> drivers/gpu/nova-core/falcon.
On Wed, 2025-05-21 at 15:45 +0900, Alexandre Courbot wrote:
> Upon reset, the GPU executes the GFW (GPU Firmware) in order to
> initialize its base parameters such as clocks. The driver must ensure
> that this step is completed before using the hardware.
>
> Signed-off-by: Alexandre Courbot
> ---
On Wed, 2025-05-21 at 15:45 +0900, Alexandre Courbot wrote:
> Reserve a page of system memory so sysmembar can perform a read on it if
> a system write occurred since the last flush. Do this early as it can be
> required to e.g. reset the GPU falcons.
>
> Signed-off-by: Alexandre Courbot
> ---
>
Hooray for new types!
Reviewed-by: Lyude Paul
On Wed, 2025-05-21 at 15:45 +0900, Alexandre Courbot wrote:
> Since we will need to allocate lots of distinct memory chunks to be
> shared between GPU and CPU, introduce a type dedicated to that. It is a
> light wrapper around CoherentAllocation.
>
On Wed, 2025-05-21 at 15:45 +0900, Alexandre Courbot wrote:
>
> -const BAR0_SIZE: usize = 8;
> +const BAR0_SIZE: usize = 0x100;
> pub(crate) type Bar0 = pci::Bar;
>
Hm, considering that you just added additional SZ_* constants wouldn't we want
to use one of those here instead of 0x100
Reviewed-by: Lyude Paul
On Wed, 2025-05-21 at 15:45 +0900, Alexandre Courbot wrote:
> Although we want to access registers using the provided methods, it is
> sometimes needed to use their raw offset, for instance when working with
> a register array.
>
> Expose the offset of each register using
Reviewed-by: Lyude Paul
On Wed, 2025-05-21 at 15:45 +0900, Alexandre Courbot wrote:
> This macro is pretty complex, and most rules are just helper, so add a
> delimiter to indicate when users only interested in using it can stop
> reading.
>
> Signed-off-by: Alexandre Courbot
> ---
> drivers/g
Reviewed-by: Lyude Paul
On Wed, 2025-05-21 at 15:45 +0900, Alexandre Courbot wrote:
> Fix the paths that were not absolute to prevent a potential local module
> from being picked up.
>
> Signed-off-by: Alexandre Courbot
> ---
> drivers/gpu/nova-core/regs/macros.rs | 12 ++--
> 1 file c
On Thu, 29 May 2025 10:23:56 -0700, Lucas De Marchi wrote:
> The XE driver can be built with or without VSEC support, but fails to link as
> built-in if vsec is in a loadable module:
>
> x86_64-linux-ld: vmlinux.o: in function `xe_vsec_init':
> (.text+0x1e83e16): undefined reference to `intel_vs
On Sat, May 24, 2025 at 2:14 AM Alexey Nepomnyashih wrote:
>
> A potential NULL pointer dereference may occur when accessing
> tmp_mqd->cp_hqd_pq_control without verifying that tmp_mqd is non-NULL.
> This may happen if mqd_backup[mqd_idx] is unexpectedly NULL.
>
> Although a NULL check for mqd_bac
Applied. Thanks!
Alex
On Fri, May 23, 2025 at 12:34 PM Dan Carpenter wrote:
>
> The "num_syncobj_handles" is a u32 value that comes from the user via the
> ioctl. On 32bit systems the "sizeof(uint32_t) * num_syncobj_handles"
> multiplication can have an integer overflow. Use size_mul() to fix
Applied. Thanks!
On Fri, May 23, 2025 at 12:25 PM Dan Carpenter wrote:
>
> This patch only affects 32bit systems. There are several integer
> overflows bugs here but only the "sizeof(u32) * num_syncobj"
> multiplication is a problem at runtime. (The last lines of this patch).
>
> These variabl
On Thu, May 22, 2025 at 8:39 AM Ozgur Kara wrote:
>
> Durmuş , 22 May 2025 Per, 15:15 tarihinde şunu yazdı:
> >
> > I'm using dual monitors. I disconnected the HDMI to test with a single
> > screen, but the result was the same. I also swapped the HDMI ports,
> > but the issue still persisted.
> >
[AMD Official Use Only - AMD Internal Distribution Only]
Hi Mike,
Thanks for the logs. I've reverted the patch in amd-staging-drm-next and also
sent the patch to the stable list.
If its possible, please also collect the dmcub trace log (cat
/sys/kernel/debug/dri/0/amdgpu_dm_dmub_tracebuffer) a
On Fri, May 30, 2025 at 10:47:27AM -0700, Jessica Zhang wrote:
> From: Abhinav Kumar
>
> On some chipsets such as qcom,sa8775p-dp, qcom,sm8650-dp and some more,
> the display port controller can support more than one pixel stream
> (multi-stream transport).
>
> To support MST on such chipsets, a
On Fri, May 30, 2025 at 10:47:26AM -0700, Jessica Zhang wrote:
> From: Abhinav Kumar
>
> Current documentation of assigned-clock-parents for dp controller does not
> describe its functionality correctly making it harder to extend it for
> adding multiple streams.
>
> Instead of fixing up the doc
On 5/28/2025 11:12 AM, Jacek Lawrynowicz wrote:
Don't WARN if imported buffers are in use in ivpu_gem_bo_free() as they
can be indeed used in the original context/driver.
Fixes: 647371a6609d ("accel/ivpu: Add GEM buffer object management")
Cc: sta...@vger.kernel.org # v6.3
Signed-off-by: Jacek L
From: Lad Prabhakar
Add support for PLLDSI and PLLDSI divider clocks.
Introduce the `renesas-rzv2h-dsi.h` header to centralize and share
PLLDSI-related data structures, limits, and algorithms between the RZ/V2H
CPG and DSI drivers.
The DSI PLL is functionally similar to the CPG's PLLDSI, but ha
From: Baihan Li
When hibmc loaded failed, the driver use hibmc_unload to free the
resource, but the mutexes in mode.config are not init, which will
access an NULL pointer.
Fixes: b3df5e65cc03 ("drm/hibmc: Drop drm_vblank_cleanup")
Reported-by: oushixiong1...@163.com
Signed-off-by: Baihan Li
---
From: Baihan Li
In early OS versions， there is a bug in hibmc-drm driver previously,
so some OS add a VGA parameter in GRUB(video=VGA-1:640x480-32@60me) to
fix the bug, that will config a force VGA mode to drm driver. However, the
HPD problem exists that mentioned in previous patch, so change VGA
…
> +++ b/drivers/accel/rocket/rocket_gem.c
> @@ -0,0 +1,131 @@
…
> +static void rocket_gem_bo_free(struct drm_gem_object *obj)
> +{
…
> + mutex_lock(&rdev->iommu_lock);
> +
> + sgt = drm_gem_shmem_get_pages_sgt(&bo->base);
…
> + drm_gem_shmem_free(&bo->base);
> +
> + mutex_unlock(&
On 5/30/2025 9:05 AM, Dmitry Baryshkov wrote:
On Fri, 30 May 2025 at 02:15, Jessica Zhang
wrote:
HPD state machine in msm dp display driver manages the state transitions
between various HPD events and the expected state of driver to make sure
both match up.
Although originally done with th
On Wed, May 28, 2025 at 10:42 AM Dmitry Baryshkov
wrote:
>
> On Wed, 28 May 2025 at 19:50, Rob Clark wrote:
> >
> > On Tue, May 27, 2025 at 11:18 AM Dmitry Baryshkov
> > wrote:
> > >
> > > On Tue, May 27, 2025 at 12:55:06PM +0200, Konrad Dybcio wrote:
> > > > On 5/26/25 5:28 PM, Rob Clark wrote:
On Mon, 19 May 2025 at 19:14, Tomeu Vizoso wrote:
>
> This series adds a new driver for the NPU that Rockchip includes in its
> newer SoCs, developed by them on the NVDLA base.
>
> In its current form, it supports the specific NPU in the RK3588 SoC.
>
> The userspace driver is part of Mesa and an
vmwgfx's fencing predates dma_fence and as a result dma_fence_ops was never
properly implemented, especially with respect to enabling signaling.
Because of this dma_fence callbacks don't work properly. This change
implements enable_signaling properly so that dma_fence callbacks now
work as expecte
There was a possible race in vmw_update_seqno. Because of this race it
was possible for last_read_seqno to go backwards. Remove this function
and replace it with vmw_update_fences which now sets and returns the
last_read_seqno while holding the fence lock. This serialization via the
fence lock ensu
Add the pixel 1 stream for displayport-controller for the following
chipsets:
- sa8775p
- sc8180x
- sc8280xp
- sm8150
- sm8350
- sm8450
- sm8650
- x1e80100
Signed-off-by: Jessica Zhang
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 26
arch/arm64/boot/dts/qcom/sc8180x.
From: Abhinav Kumar
Current documentation of assigned-clock-parents for dp controller does not
describe its functionality correctly making it harder to extend it for
adding multiple streams.
Instead of fixing up the documentation, drop the assigned-clock-parents
along with the usages in the chip
From: Abhinav Kumar
Add x1e80100 to the dp-controller bindings, fix the
displayport-controller reg bindings, and drop
assigned-clock-parents
Signed-off-by: Abhinav Kumar
Signed-off-by: Jessica Zhang
---
.../devicetree/bindings/display/msm/dp-controller.yaml | 2 ++
.../devicetree/bindi
On some MSM chipsets, the display port controller is capable of supporting
two streams. To drive the second stream, the pixel clock for the
corresponding stream needs to be enabled. In order to add the bindings for
the pixel clock for the second stream, fixup the documentation of some of
the bindin
On Fri, May 30, 2025 at 04:01:40PM +0200, Peter Zijlstra wrote:
> I'm not really concerned with performance here, but more with the size
> of the code emitted by WARN_ONCE(). There are a *ton* of WARN sites,
> while only one report_bug() and printk().
>
> The really offensive thing is that this is
From: Abhinav Kumar
On some chipsets such as qcom,sa8775p-dp, qcom,sm8650-dp and some more,
the display port controller can support more than one pixel stream
(multi-stream transport).
To support MST on such chipsets, add the binding for stream 1 pixel
clock for display port controller.
Since t
From: Abhinav Kumar
Add DISP_CC_MDSS_DP_PIXEL1_* macros for SC7280
Signed-off-by: Abhinav Kumar
Signed-off-by: Jessica Zhang
---
include/dt-bindings/clock/qcom,dispcc-sc7280.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/dt-bindings/clock/qcom,dispcc-sc7280.h
b/include/dt-bi
From: Lad Prabhakar
Hi All,
This patch series adds support for the Display Unit (DU) and prepares
the MIPI DSI driver to support the Renesas RZ/V2H(P) SoC. These patches
were originally part of series [0], but I have split them into two parts
to make them easier to review and merge.
This patch
From: Lad Prabhakar
The MIPI DSI interface on the RZ/V2H(P) SoC is nearly identical to that of
the RZ/G2L SoC. While the LINK registers are the same for both SoCs, the
D-PHY registers differ. Additionally, the number of resets for DSI on
RZ/V2H(P) is two compared to three on the RZ/G2L.
To accom
From: Lad Prabhakar
Add DSI support for Renesas RZ/V2H(P) SoC.
Co-developed-by: Fabrizio Castro
Signed-off-by: Fabrizio Castro
Signed-off-by: Lad Prabhakar
---
v5->v6:
- Made use of GENMASK() macro for PLLCLKSET0R_PLL_*,
PHYTCLKSETR_* and PHYTHSSETR_* macros.
- Replaced 1000UL with 10 *
From: Lad Prabhakar
Add clock and reset entries for the DSI and LCDC peripherals.
Co-developed-by: Fabrizio Castro
Signed-off-by: Fabrizio Castro
Signed-off-by: Lad Prabhakar
---
v5->v6:
- Renamed CLK_DIV_PLLETH_LPCLK to CLK_CDIV4_PLLETH_LPCLK
- Renamed CLK_CSDIV_PLLETH_LPCLK to CLK_PLLETH_LP
From: Lad Prabhakar
Hi All,
This patch series adds DU/DSI clocks and provides support for the
MIPI DSI interface on the RZ/V2H(P) SoC. It was originally part of
series [0], but has now been split into 4 patches due to dependencies
on the clock driver, making it easier to review and merge.
[0]
From: Lad Prabhakar
Pass the HSFREQ in milli-Hz to the `dphy_init()` callback to improve
precision, especially for the RZ/V2H(P) SoC, where PLL dividers require
high accuracy.
These changes prepare the driver for upcoming RZ/V2H(P) SoC support.
Co-developed-by: Fabrizio Castro
Signed-off-by: F
From: Lad Prabhakar
Introduce the `RZ_MIPI_DSI_FEATURE_16BPP` flag in `rzg2l_mipi_dsi_hw_info`
to indicate support for 16BPP pixel formats. The RZ/V2H(P) SoC supports
16BPP, whereas this feature is missing on the RZ/G2L SoC.
Update the `mipi_dsi_host_attach()` function to check this flag before
From: Lad Prabhakar
Update the RZ/G2L MIPI DSI driver to calculate HSFREQ using the actual
VCLK rate instead of the mode clock. The relationship between HSCLK and
VCLK is:
vclk * bpp <= hsclk * 8 * lanes
Retrieve the VCLK rate using `clk_get_rate(dsi->vclk)`, ensuring that
HSFREQ accurately
From: Lad Prabhakar
The LCD controller (LCDC) on the RZ/V2H(P) SoC is composed of Frame
Compression Processor (FCPVD), Video Signal Processor (VSPD), and
Display Unit (DU).
There is one LCDC unit available on the RZ/V2H(P) SoC which is connected
to the DSI.
Signed-off-by: Lad Prabhakar
Reviewe
From: Lad Prabhakar
Simplify the high-speed clock frequency (HSFREQ) calculation by removing
the redundant multiplication and division by 8. The updated equation:
hsfreq = mode->clock * bpp / dsi->lanes;
produces the same result while improving readability and clarity.
Additionally, update
From: Lad Prabhakar
In preparation for adding support for the Renesas RZ/V2H(P) SoC, make the
"rst" reset control optional in the MIPI DSI driver. The RZ/V2H(P) SoC
does not provide this reset line, and attempting to acquire it using the
mandatory API causes probe failure.
Switching to devm_rese
From: Lad Prabhakar
Add LPCLK clock support in the RZ/G2L MIPI DSI driver via the optional
clock API. This clock is required by some SoCs like RZ/V2H(P) for proper
DPHY configuration, whereas it is absent on others like RZ/G2L.
Introduce a new `lpclk` field in the `rzg2l_mipi_dsi` structure and
From: Lad Prabhakar
In preparation for adding support for the Renesas RZ/V2H(P) SoC, this patch
introduces a mechanism to pass SoC-specific information via OF data in the
DSI driver. This enables the driver to adapt dynamically to various
SoC-specific requirements without hardcoding configuration
From: Lad Prabhakar
Introduce the `dphy_late_init` callback in `rzg2l_mipi_dsi_hw_info` to
allow additional D-PHY register configurations after enabling data and
clock lanes. This is required for the RZ/V2H(P) SoC but not for the
RZ/G2L SoC.
Modify `rzg2l_mipi_dsi_startup()` to invoke `dphy_late
From: Lad Prabhakar
Introduce `dphy_conf_clks` and `dphy_mode_clk_check` callbacks in
`rzg2l_mipi_dsi_hw_info` to configure the VCLK and validate
supported display modes.
On the RZ/V2H(P) SoC, the DSI PLL dividers need to be as accurate as
possible. To ensure compatibility with both RZ/G2L and R
From: Lad Prabhakar
The VCLK range for Renesas RZ/G2L SoC is 5.803 MHz to 148.5 MHz. Add a
minimum clock check in the mode_valid callback to ensure that the clock
value does not fall below the valid range.
Co-developed-by: Fabrizio Castro
Signed-off-by: Fabrizio Castro
Signed-off-by: Lad Prabh
From: Lad Prabhakar
The DU block on the RZ/V2H(P) SoC is identical to the one found on the
RZ/G2L SoC. However, it only supports the DSI interface, whereas the
RZ/G2L supports both DSI and DPI interfaces.
Due to this difference, a SoC-specific compatible string
'renesas,r9a09g057-du' is added fo
On Fri, 30 May 2025 at 02:15, Jessica Zhang
wrote:
>
> HPD state machine in msm dp display driver manages the state transitions
> between various HPD events and the expected state of driver to make sure
> both match up.
>
> Although originally done with the intent of managing userspace interaction
On 5/20/2025 4:27 AM, Tomeu Vizoso wrote:
- version = rocket_pc_read(core, VERSION);
- version += rocket_pc_read(core, VERSION_NUM) & 0x;
+ version = rocket_pc_readl(core, VERSION);
+ version += rocket_pc_readl(core, VERSION_NUM) & 0x;
This seems weird. Feels li
On Fri, May 30, 2025 at 07:36:05PM +0530, Jyothi Kumar Seerapu wrote:
>
>
> On 5/21/2025 6:15 PM, Dmitry Baryshkov wrote:
> > On Wed, May 21, 2025 at 03:58:48PM +0530, Jyothi Kumar Seerapu wrote:
> > >
> > >
> > > On 5/9/2025 9:31 PM, Dmitry Baryshkov wrote:
> > > > On 09/05/2025 09:18, Jyothi
First verify system_heap exporter has exclusive dmabuf access.
Build bio_vec from sgtable, then invoke target file's r/w callbacks for IO.
Outperforms buffer IO mmap/read by 250%, beats direct I/O udmabuf
copy_file_range by over 30% with initialization time significantly lower
than udmabuf.
Test d
On 5/20/2025 4:27 AM, Tomeu Vizoso wrote:
The NPU cores have their own access to the memory bus, and this isn't
cache coherent with the CPUs.
Add IOCTLs so userspace can mark when the caches need to be flushed, and
also when a writer job needs to be waited for before the buffer can be
accessed f
On Fri, 30 May 2025 at 17:05, Jyothi Kumar Seerapu
wrote:
>
>
>
> On 5/9/2025 11:48 AM, Jyothi Kumar Seerapu wrote:
> >
> >
> > On 5/6/2025 5:02 PM, Dmitry Baryshkov wrote:
> >> On Tue, May 06, 2025 at 04:48:43PM +0530, Jyothi Kumar Seerapu wrote:
> >>> GSI hardware generates an interrupt for each
On Fri, May 30, 2025 at 12:29:30PM +1000, Alexey Kardashevskiy wrote:
>
>
> On 30/5/25 00:41, Xu Yilun wrote:
> > > > > >
> > > > > > FLR to a bound device is absolutely fine, just break the CC state.
> > > > > > Sometimes it is exactly what host need to stop CC immediately.
> > > > > > The prob
On 5/20/2025 4:26 AM, Tomeu Vizoso wrote:
diff --git a/drivers/accel/rocket/rocket_device.h
b/drivers/accel/rocket/rocket_device.h
new file mode 100644
index
..55f4da252cfbd1f102c56e5009472deff59aaaec
--- /dev/null
+++ b/drivers/accel/rocket/rocket_device
On Thu, May 29, 2025 at 01:29:23PM -0300, Jason Gunthorpe wrote:
> On Thu, May 29, 2025 at 10:41:15PM +0800, Xu Yilun wrote:
>
> > > On AMD, the host can "revoke" at any time, at worst it'll see RMP
> > > events from IOMMU. Thanks,
> >
> > Is the RMP event firstly detected by host or guest? If by
On Fri, 30 May 2025 at 02:15, Jessica Zhang
wrote:
>
> From: Abhinav Kumar
>
> The checks in msm_dp_bridge_atomic_enable() for making sure that we are in
> ST_DISPLAY_OFF OR ST_MAINLINK_READY seem redundant.
>
> DRM fwk shall not issue any commits if state is not ST_MAINLINK_READY as
> msm_dp's a
On Fri, 30 May 2025 at 17:59, Jun Nie wrote:
>
> Dmitry Baryshkov 于2025年5月29日周四 02:22写道：
> >
> > On Mon, May 26, 2025 at 05:28:28PM +0800, Jun Nie wrote:
> > > Currently, SSPPs are assigned to a maximum of two pipes. However,
> > > quad-pipe usage scenarios require four pipes and involve configur
Add the support for:
- RGB888
- BGR888
Signed-off-by: Louis Chauvet
---
drivers/gpu/drm/vkms/vkms_formats.c | 7 +++
drivers/gpu/drm/vkms/vkms_plane.c | 2 ++
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/vkms/vkms_formats.c
b/drivers/gpu/drm/vkms/vkms_formats.c
index 2c5
On 5/16/2025 10:06 AM, Jeff Hugo wrote:
AIC100 devices generates Reliability, Availability, Serviceability events
via MHI QAIC_STATUS channel. Support such events and print a structured
log with details of the events, and if the event describes an uncorrected
error, reset the device to put it bac
在 2025/5/30 17:54, 00 1970 写道:
From: Baihan Li
When hibmc loaded failed, the driver use hibmc_unload to free the
resource, but the mutexes in mode.config are not init, which will
access an NULL pointer.
Fixes: b3df5e65cc03 ("drm/hibmc: Drop drm_vblank_cleanup")
Reported-by:oushixiong1...@163.c
On Wed, May 28, 2025 at 04:51:10PM +0300, Alexander Usyskin wrote:
> GSC NVM controller HW errors on quad access overlapping 1K border.
> Align 64bit read and write to avoid readq/writeq over 1K border.
>
> Acked-by: Miquel Raynal
> Signed-off-by: Alexander Usyskin
Reviewed-by: Raag Jadav
Dmitry Baryshkov 于2025年5月29日周四 02:22写道：
>
> On Mon, May 26, 2025 at 05:28:28PM +0800, Jun Nie wrote:
> > Currently, SSPPs are assigned to a maximum of two pipes. However,
> > quad-pipe usage scenarios require four pipes and involve configuring
> > two stages. In quad-pipe case, the first two pipes
Add a test to submit a single job against a scheduler with the timeout
configured and verify that if the job is still running, the timeout
handler will skip the reset and allow the job to complete.
Signed-off-by: Maíra Canal
---
drivers/gpu/drm/scheduler/tests/mock_scheduler.c | 5 +++
drivers/
On Wed, May 28, 2025 at 04:51:09PM +0300, Alexander Usyskin wrote:
> Register the on-die nvm device with the mtd subsystem.
> Refcount nvm object on _get and _put mtd callbacks.
> For erase operation address and size should be 4K aligned.
> For write operation address and size has to be 4bytes alig
Hi wangtao,
kernel test robot noticed the following build errors:
[auto build test ERROR on brauner-vfs/vfs.all]
[also build test ERROR on next-20250530]
[cannot apply to linus/master v6.15]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we
Xe can skip the reset if TDR has fired before the free job worker and can
also re-arm the timeout timer in some scenarios. Instead of using the
scheduler internals to add the job to the pending list, use the
DRM_GPU_SCHED_STAT_NO_HANG status to skip the reset and re-arm the timer.
Note that, in th
When the DRM scheduler times out, it's possible that the GPU isn't hung;
instead, a job may still be running, and there may be no valid reason to
reset the hardware. This can occur in two situations:
1. The GPU exposes some mechanism that ensures the GPU is still making
progress. By checkin
As more KUnit tests are introduced to evaluate the basic capabilities of
the `timedout_job()` hook, the test suite will continue to increase in
duration. To reduce the overall running time of the test suite, decrease
the scheduler's timeout for the timeout tests.
Before this commit:
[15:42:26] El
On 5/21/2025 6:15 PM, Dmitry Baryshkov wrote:
On Wed, May 21, 2025 at 03:58:48PM +0530, Jyothi Kumar Seerapu wrote:
On 5/9/2025 9:31 PM, Dmitry Baryshkov wrote:
On 09/05/2025 09:18, Jyothi Kumar Seerapu wrote:
Hi Dimitry, Thanks for providing the review comments.
On 5/6/2025 5:16 PM, Dmi
The formats XRGB and ARGB were already supported.
Add the support for:
- XBGR
- RGBX
- BGRX
- ABGR
- RGBA
- BGRA
Signed-off-by: Louis Chauvet
---
drivers/gpu/drm/vkms/vkms_formats.c | 19 +--
drivers/gpu/drm/vkms/vkms_plane.c | 7 ++-
2 file
The callback functions for line conversion are almost identical for
some format. The generic READ_LINE macro generate all the required
boilerplate to process a line.
Two overrides of this macro have been added to avoid duplication of
the same arguments every time.
Signed-off-by: Louis Chauvet
--
The formats XRGB16161616 and ARGB16161616 were already supported.
Add the support for:
- ABGR16161616
- XBGR16161616
Signed-off-by: Louis Chauvet
---
drivers/gpu/drm/vkms/vkms_formats.c | 6 ++
drivers/gpu/drm/vkms/vkms_plane.c | 2 ++
2 files changed, 8 insertions(+)
diff --git a/drivers
Some YUV format uses 16 bit values, so change the helper function for
conversion to support those new formats.
Add support for the YUV format P010
Signed-off-by: Louis Chauvet
---
drivers/gpu/drm/vkms/tests/vkms_format_test.c | 103 +-
drivers/gpu/drm/vkms/vkms_formats.c
The callback functions for line conversion are almost identical for
semi-planar formats. The generic READ_LINE_YUV_SEMIPLANAR macro
generate all the required boilerplate to process a line from a
semi-planar format.
Signed-off-by: Louis Chauvet
---
drivers/gpu/drm/vkms/vkms_formats.c | 75 +++
The formats NV 12/16/24/21/61/42 were already supported.
Add support for:
- P010
- P012
- P016
Signed-off-by: Louis Chauvet
---
drivers/gpu/drm/vkms/vkms_formats.c | 7 ++-
drivers/gpu/drm/vkms/vkms_plane.c | 3 +++
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/
The format RGB565 was already supported. Add the support for:
- BGR565
Signed-off-by: Louis Chauvet
---
drivers/gpu/drm/vkms/vkms_formats.c | 23 +++
drivers/gpu/drm/vkms/vkms_plane.c | 1 +
2 files changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/vkms/vkms_formats.
This series introduce a macro to generate a function to read simple
formats. It avoid duplication of the same logic for similar formats.
In addition, it also introduce multiple "easy" formats (rgb888 variants)
and also 16 bits yuv support (P01* formats).
PATCH 1 is the introduction of the macro
[AMD Official Use Only - AMD Internal Distribution Only]
Hi Mike,
We were trying to see if we can repro the issue on newer cards as well, but it
seems only 6000 series can repro at our end.
If you can repro more easily on other cards, please add "drm.debug=0x116
log_buf_len=20M" to your kernel
On 5/9/2025 11:48 AM, Jyothi Kumar Seerapu wrote:
On 5/6/2025 5:02 PM, Dmitry Baryshkov wrote:
On Tue, May 06, 2025 at 04:48:43PM +0530, Jyothi Kumar Seerapu wrote:
GSI hardware generates an interrupt for each transfer completion.
For multiple messages within a single transfer, this result
Panfrost can skip the reset if TDR has fired before the free-job worker.
Currently, since Panfrost doesn't take any action on these scenarios, the
job is being leaked, considering that `free_job()` won't be called.
To avoid such leaks, use the DRM_GPU_SCHED_STAT_NO_STAT status to skip the
reset an
+Mark because he loves a hack :-)
On Thu, May 29, 2025 at 12:36:55PM +0200, Alessandro Carminati wrote:
> > Like I said before; you need to do this on the report_bug() size of
> > things.
> >
> I fully understand your concerns, and I truly appreciate both yours
> and Josh’s feedback on this mat
Etnaviv can skip a hardware reset in two situations:
1. TDR has fired before the free-job worker and the timeout is spurious.
2. The GPU is still making progress on the front-end and we can give
the job a chance to complete.
Instead of relying on the scheduler internals, use the
DRM_GPU_
On Thu, May 29, 2025 at 01:27:38PM -0500, Rob Herring (Arm) wrote:
>
> On Thu, 29 May 2025 12:48:21 -0400, Frank Li wrote:
> > Convert himax,hx8357d.txt to yaml format.
> >
> > Additional changes:
> > - add spi parent node in examples.
> > - ref to spi-peripheral-props.yaml.
> > - change himax,hx
When a CL/CSD job times out, we check if the GPU has made any progress
since the last timeout. If so, instead of resetting the hardware, we skip
the reset and allow the timer to be rearmed. This gives long-running jobs
a chance to complete.
Use the DRM_GPU_SCHED_STAT_NO_HANG status to skip the res
When the DRM scheduler times out, it's possible that the GPU isn't hung;
instead, a job may still be running, and there may be no valid reason to
reset the hardware. This can occur in two situations:
1. The GPU exposes some mechanism that ensures the GPU is still making
progress. By checkin
Among the scheduler's statuses, the only one that indicates an error is
DRM_GPU_SCHED_STAT_ENODEV. Any status other than DRM_GPU_SCHED_STAT_ENODEV
signifies that the operation succeeded and the GPU is in a nominal state.
However, to provide more information about the GPU's status, it is needed
to
On Thu, 22 May 2025 11:33:00 +
"Shankar, Uma" wrote:
> One request though: Can we enhance the lut samples from existing 16bits to
> 32bits as lut precision is
> going to be more than 16 in certain hardware. While adding the new UAPI, lets
> extend this to 32 to make it future proof.
> Refer
From: Baihan Li
The local variable of irq name is passed to devm_request_threaded_irq(),
which will make request_irq failed. Using the global irq name instead
of it to fix.
Fixes: b11bc1ae4658 ("drm/hisilicon/hibmc: Add MSI irq getting and requesting
for HPD")
Signed-off-by: Baihan Li
---
dri
On Wed, May 28, 2025 at 04:51:07PM +0300, Alexander Usyskin wrote:
> In intel-dg, there is no access to the spi controller,
> the information is extracted from the descriptor region.
>
> CC: Lucas De Marchi
> Reviewed-by: Rodrigo Vivi
> Acked-by: Miquel Raynal
> Co-developed-by: Tomas Winkler
Hey,
I was looking into testing this with the xe code on PVC, and noticed some small
changes that would be useful to integrate before merging.
On 2025-05-28 15:51, Alexander Usyskin wrote:
> Enable access to internal non-volatile memory on DGFX
> with GSC/CSC devices via a child device.
> The nv
Hi
Am 30.05.25 um 12:10 schrieb Javier Martinez Canillas:
Thomas Zimmermann writes:
Map DRM FourCC codes to pixel descriptions with internal type struct
hdlcd_format. Reorder formats by preference. Avoid simplefb's struct
simplefb_format, which is for parsing "simple-framebuffer" DT nodes.
T
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