On Thu, Apr 17, 2025 at 09:02:15PM +0530, Gupta, Nipun wrote:
>
> Thanks for pointing out to the C file, but as these these system calls can
> support only synchronous operations, precludes their use for asynchronous
> operations. In the TLS handshakes, where multiple connections occur
> simultaneo
b_atomic_check(struct drm_device *drm,
struct drm_atomic_state *state);
---
base-commit: 119009db267415049182774196e3cce9e13b52ef
change-id: 20250419-tegra-drm-primary-ce47febefdaf
Best regards,
--
Aaron Kling
Hi Martijn, Hi Neil,
On Thu, Apr 10, 2025 at 8:46 PM wrote:
>
> Hi Martin,
>
> Thank you for the patch.
>
> I encountered this issue some time ago as well and had a possible fix in my
> tree (see
> below).
> My apologies for not upstreaming it earlier.
No worries, we're all busy with both, offli
The pull request you sent on Sat, 19 Apr 2025 15:19:47 +1000:
> https://gitlab.freedesktop.org/drm/kernel.git tags/drm-fixes-2025-04-19
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/51c7960b87f465d01ea8d8ff174e81dd69f3b2b4
Thank you!
--
Deet-doot-dot, I am a bot.
h
On Sat, Apr 19, 2025 at 07:50:01AM +0800, Mauro Carvalho Chehab wrote:
> As reported by Andy, the Kernel build system runs kernel-doc script for DRM,
> when W=1. Due to Python's normal behavior, its JIT compiler will create
> a bytecode and store it under scripts/lib/*/__pycache__. As one may be u
},
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, sofef00_panel_of_match);
---
base-commit: bc8aa6cdadcc00862f2b5720e5de2e17f696a081
change-id: 20250419-drop-s6e3fc2x01-support-d060a14a4791
Best regards,
--
David Heidelberg
Now that we have ACD support for GPU, add additional OPPs up to
Turbo L3 which are supported across all existing SKUs.
Signed-off-by: Akhil P Oommen
Reviewed-by: Konrad Dybcio
Tested-by: Maya Matuszczyk
Tested-by: Anthony Ruhier
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 16 +++-
Update GPU node to include acd level values.
Signed-off-by: Akhil P Oommen
Reviewed-by: Konrad Dybcio
Tested-by: Maya Matuszczyk
Tested-by: Anthony Ruhier
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot
Add a new schema which extends opp-v2 to support a new vendor specific
property required for Adreno GPUs found in Qualcomm's SoCs. The new
property called "qcom,opp-acd-level" carries a u32 value recommended
for each opp needs to be shared to GMU during runtime.
Also, update MAINTAINERS file inclu
Add a module param to disable ACD which will help to quickly rule it
out for any GPU issues.
Signed-off-by: Akhil P Oommen
Tested-by: Maya Matuszczyk
Tested-by: Anthony Ruhier
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 7 +++
drivers/gpu/drm/msm/adreno/adreno_device.c | 4
2 fil
Fix the following for qmp_get() errors:
1. Correctly handle probe defer for A6x GPUs
2. Ignore other errors because those are okay when GPU ACD is
not required. They are checked again during gpu acd probe.
Signed-off-by: Akhil P Oommen
Reviewed-by: Konrad Dybcio
Tested-by: Maya Matuszczyk
Test
When ACD feature is enabled, it triggers some internal calibrations
which result in a pretty long delay during the first HFI perf vote.
So, increase the HFI response timeout to match the downstream driver.
Signed-off-by: Akhil P Oommen
Tested-by: Maya Matuszczyk
Tested-by: Anthony Ruhier
---
d
ACD a.k.a Adaptive Clock Distribution is a feature which helps to reduce
the power consumption. In some chipsets, it is also a requirement to
support higher GPU frequencies. This patch adds support for GPU ACD by
sending necessary data to GMU and AOSS. The feature support for the
chipset is detecte
This series adds support for ACD feature for Adreno GPU which helps to
lower the power consumption on GX rail and also sometimes is a requirement
to enable higher GPU frequencies. At high level, following are the
sequences required for ACD feature:
1. Identify the ACD level data for each re
On 1/9/2025 2:10 AM, Akhil P Oommen wrote:
> Add a new schema which extends opp-v2 to support a new vendor specific
> property required for Adreno GPUs found in Qualcomm's SoCs. The new
> property called "qcom,opp-acd-level" carries a u32 value recommended
> for each opp needs to be shared to GMU d
el.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link:
https://lore.kernel.org/r/20250418065313.8972-4-bincai.liu%40mediatek.com
patch subject: [PATCH 3/5] drm/mediatek: Add dvo driver for mt8196
config: i386-buildonly-randconfig-001-20250419
(https://download.01.org/0day-ci/archiv
Hi Prabhakar,
Thanks for the patch.
> -Original Message-
> From: Prabhakar
> Sent: 18 April 2025 19:47
> Subject: [PATCH v3 15/15] drm: renesas: rz-du: mipi_dsi: Add support for
> RZ/V2H(P) SoC
>
> From: Lad Prabhakar
>
> Add DSI support for Renesas RZ/V2H(P) SoC.
>
> Co-developed-b
45911
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link:
https://lore.kernel.org/r/20250418065313.8972-4-bincai.liu%40mediatek.com
patch subject: [PATCH 3/5] drm/mediatek: Add dvo driver for mt8196
config: i386-buildonly-randconfig-006-20250419
(https://downl
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