Hi Linus,
Easter rc3 pull request, fixes in all the usuals, amdgpu, xe, msm,
with some i915/ivpu/mgag200/v3d fixes, then a couple of bits in
dma-buf/gem.
Hopefully has no easter eggs in it,
Regards,
Dave.
drm-fixes-2025-04-19:
drm fixes for 6.15-rc3
dma-buf:
- Correctly decrement refcounter on
There are no remaining users of mipi_dsi_dcs_write_seq and it can be
removed in favor of mipi_dsi_dcs_write_seq_multi.
Signed-off-by: Tejas Vipin
---
include/drm/drm_mipi_dsi.h | 22 --
1 file changed, 22 deletions(-)
diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm
Changes the samsung-sofef00 panel to use multi style functions for
improved error handling.
Signed-off-by: Tejas Vipin
---
drivers/gpu/drm/panel/panel-samsung-sofef00.c | 70 ++-
1 file changed, 21 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-samsung-s
panel-samsung-sofef00 is the last remaining user of
mipi_dsi_dcs_write_seq, so mipi_dsi_dcs_write_seq can be removed after
the panel has been changed to use mipi_dsi_*_multi functions.
Tejas Vipin (2):
drm/panel: panel-samsung-sofef00: transition to mipi_dsi wrapped
functions
drm/mipi-dsi:
On 17.04.2025 14:19, Boris Brezillon wrote:
> Right now the DRM_PANTHOR_BO_NO_MMAP flag is ignored by
> panthor_ioctl_bo_mmap_offset(), meaning BOs with this flag set can
> have a file offset but can't be mapped anyway, because
> panthor_gem_mmap() will filter them out.
>
> If we error out at mmap_
Hi Andy,
Em Wed, 16 Apr 2025 12:41:29 +0300
Andy Shevchenko escreveu:
> On Wed, Apr 16, 2025 at 05:38:11PM +0800, Mauro Carvalho Chehab wrote:
> > Em Wed, 16 Apr 2025 17:29:01 +0800
> > Mauro Carvalho Chehab escreveu:
>
> ...
>
> > Heh, trying to quickly write a patch before calling it a da
As reported by Andy, the Kernel build system runs kernel-doc script for DRM,
when W=1. Due to Python's normal behavior, its JIT compiler will create
a bytecode and store it under scripts/lib/*/__pycache__. As one may be using
O= and even having the sources on a read-only mount point, disable its
c
As reported by Andy, kernel-doc.py is creating a __pycache__
directory at build time.
Disable creation of __pycache__ for the libraries used by
kernel-doc.py, when excecuted via the build system or via
scripts/find-unused-docs.sh.
Reported-by: Andy Shevchenko
Closes: https://lore.kernel.org/linu
From: Dongwon Kim
Host KVM/QEMU loses all graphics resources submitted by the guest OS
upon resumption from sleep or hibernation. This results in invalid
resource errors when the guest OS attempts to interact with the host
regarding those resources.
To address this issue, the virtio-gpu driver n
From: Dongwon Kim
This patch series introduces a freeze and restore mechanism for
the virtio-gpu driver:
First patch adds `virtgpu_freeze` and `virtgpu_restore` functions.
These functions handle the deletion of virtio queues before suspension and
their recreation during the restoration process.
From: Dongwon Kim
virtio device needs to delete before VM suspend happens
then reinitialize all virtqueues again upon resume
Cc: Dmitry Osipenko
Cc: Vivek Kasireddy
Signed-off-by: Dongwon Kim
---
drivers/gpu/drm/virtio/virtgpu_drv.c | 53 +++-
drivers/gpu/drm/virtio/v
Hi Dave, Simona,
A few fixes for v6.15, as described below.
The following changes since commit 83ee6d2ec52f1378f3473ee8657d559bebdbda44:
dt-bindings: display/msm: dsi-controller-main: Add missing minItems
(2025-03-08 03:06:00 +0200)
are available in the Git repository at:
https://gitlab.fr
Left a few tiny comments to address before pushing upstream, mostly just style
stuff.
With those addressed, for the whole series:
Reviewed-by: Lyude Paul
On Fri, 2025-04-11 at 01:55 +0200, Danilo Krummrich wrote:
> This is the series for the initial DRM Rust abstractions, including DRM
> devic
On Fri, 2025-04-11 at 01:55 +0200, Danilo Krummrich wrote:
> +
> +/// The open callback of a `struct drm_file`.
> +pub(crate) extern "C" fn open_callback(
> +raw_dev: *mut bindings::drm_device,
> +raw_file: *mut bindings::drm_file,
> +) -> core::ffi::c_int {
> +/
On Fri, 2025-04-11 at 01:55 +0200, Danilo Krummrich wrote:
> From: Asahi Lina
>
> Implement the DRM driver `Registration`.
>
> The `Registration` structure is responsible to register and unregister a
> DRM driver. It makes use of the `Devres` container in order to allow the
> `Registration` to b
On Fri, 2025-04-11 at 01:55 +0200, Danilo Krummrich wrote:
> From: Asahi Lina
>
> Implement the DRM driver abstractions.
>
> The `Driver` trait provides the interface to the actual driver to fill
> in the driver specific data, such as the `DriverInfo`, driver features
> and IOCTLs.
>
> Reviewed
Not a review comment (but I should finish reading through this series in just
a moment) for
On Fri, 2025-04-11 at 01:55 +0200, Danilo Krummrich wrote:
> + // SAFETY:
> + // - The DRM core ensures the device lives while
> callbacks are being
>
(JFYI: I really like this and I think I'm going to use this approach in the
KMS bindings as well 👀)
On Fri, 2025-04-11 at 01:55 +0200, Danilo Krummrich wrote:
> In the Rust DRM device abstraction we need to allocate a struct
> drm_device.
>
> Currently, there are two options, the deprecated drm_d
On 18.04.2025 10:26, Boris Brezillon wrote:
On Fri, 18 Apr 2025 10:11:56 +0200
Boris Brezillon wrote:
> On Fri, 18 Apr 2025 03:27:07 +0100
> Adrián Larumbe wrote:
>
> > + static const char * const gem_state_flags_names[] = {
> > + [PANTHOR_DEBUGFS_GEM_STATE_FLAG_IMPORTED] = "imported
Hi Boris,
On 18.04.2025 10:04, Boris Brezillon wrote:
> On Fri, 18 Apr 2025 03:27:07 +0100
> Adrián Larumbe wrote:
>
> > +#ifdef CONFIG_DEBUG_FS
> > +static void
> > +panthor_gem_debugfs_format_flags(char flags_str[], int flags_len,
> > +const char * const names[], u32
On 19-04-2025 00:16, Prabhakar wrote:
+ * @freq: Target output frequency (in mHz)
Do you mind checking this one
+ *
+ * This function calculates the best set of PLL parameters (M, K, P, S) and
divider
+ * value (CSDIV) to achieve the desired frequency.
+ * There is no direct formula to ca
From: Lad Prabhakar
Introduce the `dphy_late_init` callback in `rzg2l_mipi_dsi_hw_info` to
allow additional D-PHY register configurations after enabling data and
clock lanes. This is required for the RZ/V2H(P) SoC but not for the
RZ/G2L SoC.
Modify `rzg2l_mipi_dsi_startup()` to invoke `dphy_late
From: Lad Prabhakar
In preparation for adding support for the Renesas RZ/V2H(P) SoC, this patch
introduces a mechanism to pass SoC-specific information via OF data in the
DSI driver. This enables the driver to adapt dynamically to various
SoC-specific requirements without hardcoding configuration
From: Lad Prabhakar
Add DSI support for Renesas RZ/V2H(P) SoC.
Co-developed-by: Fabrizio Castro
Signed-off-by: Fabrizio Castro
Signed-off-by: Lad Prabhakar
---
v2->v3:
- Simplifed V2H DSI timings array to save space
- Switched to use fsleep() instead of udelay()
v1->v2:
- Dropped unused macr
From: Lad Prabhakar
Introduce the `RZ_MIPI_DSI_FEATURE_16BPP` flag in `rzg2l_mipi_dsi_hw_info`
to indicate support for 16BPP pixel formats. The RZ/V2H(P) SoC supports
16BPP, whereas this feature is missing on the RZ/G2L SoC.
Update the `mipi_dsi_host_attach()` function to check this flag before
From: Lad Prabhakar
Update the RZ/G2L MIPI DSI driver to calculate HSFREQ using the actual
VCLK rate instead of the mode clock. The relationship between HSCLK and
VCLK is:
vclk * bpp <= hsclk * 8 * lanes
Retrieve the VCLK rate using `clk_get_rate(dsi->vclk)`, ensuring that
HSFREQ accurately
From: Lad Prabhakar
Introduce the `RZ_MIPI_DSI_FEATURE_LPCLK` feature flag in
`rzg2l_mipi_dsi_hw_info` to indicate the need for LPCLK configuration.
On the RZ/V2H(P) SoC, the LPCLK clock rate influences the required
DPHY register configuration, whereas on the RZ/G2L SoC, this clock
is not presen
From: Lad Prabhakar
Pass the HSFREQ in milli-Hz to the `dphy_init()` callback to improve
precision, especially for the RZ/V2H(P) SoC, where PLL dividers require
high accuracy.
These changes prepare the driver for upcoming RZ/V2H(P) SoC support.
Co-developed-by: Fabrizio Castro
Signed-off-by: F
From: Lad Prabhakar
Introduce `dphy_conf_clks` and `dphy_mode_clk_check` callbacks in
`rzg2l_mipi_dsi_hw_info` to configure the VCLK and validate
supported display modes.
On the RZ/V2H(P) SoC, the DSI PLL dividers need to be as accurate as
possible. To ensure compatibility with both RZ/G2L and R
From: Lad Prabhakar
The MIPI DSI interface on the RZ/V2H(P) SoC is nearly identical to that of
the RZ/G2L SoC. While the LINK registers are the same for both SoCs, the
D-PHY registers differ. Additionally, the number of resets for DSI on
RZ/V2H(P) is two compared to three on the RZ/G2L.
To accom
From: Lad Prabhakar
The DU block on the RZ/V2H(P) SoC is identical to the one found on the
RZ/G2L SoC. However, it only supports the DSI interface, whereas the
RZ/G2L supports both DSI and DPI interfaces.
Due to this difference, a SoC-specific compatible string
'renesas,r9a09g057-du' is added fo
From: Lad Prabhakar
Simplify the high-speed clock frequency (HSFREQ) calculation by removing
the redundant multiplication and division by 8. The updated equation:
hsfreq = (mode->clock * bpp) / (dsi->lanes);
produces the same result while improving readability and clarity.
Additionally, up
From: Lad Prabhakar
The LCD controller (LCDC) on the RZ/V2H(P) SoC is composed of Frame
Compression Processor (FCPVD), Video Signal Processor (VSPD), and
Display Unit (DU).
There is one LCDC unit available on the RZ/V2H(P) SoC which is connected
to the DSI.
Signed-off-by: Lad Prabhakar
---
v2-
From: Lad Prabhakar
The VCLK range for Renesas RZ/G2L SoC is 148.5 MHz to 5.803 MHz. Add a
minimum clock check in the mode_valid callback to ensure that the clock
value does not fall below the valid range.
Co-developed-by: Fabrizio Castro
Signed-off-by: Fabrizio Castro
Signed-off-by: Lad Prabh
From: Lad Prabhakar
Hi All,
This patch series adds support for the Display Unit (DU) and MIPI DSI
interface on the Renesas RZ/V2H(P) SoC. The initial patches add PLLDSI
clocks and reset entries for the DSI and LCDC and the later patches add
support for the DU and DSI drivers. The DU block is sim
From: Lad Prabhakar
Add support for PLLDSI and PLLDSI divider clocks.
Introduce the `renesas-rzv2h-dsi.h` header to centralize and share
PLLDSI-related data structures, limits, and algorithms between the RZ/V2H
CPG and DSI drivers.
The DSI PLL is functionally similar to the CPG's PLLDSI, but ha
From: Lad Prabhakar
Add clock and reset entries for the DSI and LCDC peripherals.
Co-developed-by: Fabrizio Castro
Signed-off-by: Fabrizio Castro
Signed-off-by: Lad Prabhakar
---
v2->v3:
- Reverted CSDIV0_DIVCTL2() to use DDIV_PACK()
- Renamed plleth_lpclk_div4 -> cdiv4_plleth_lpclk
- Renamed
On Mon, 03 Mar 2025 23:14:29 +0800 Jun Nie wrote:
> 2 or more SSPPs and dual-DSI interface are need for super wide panel.
> And 4 DSC are preferred for power optimal in this case due to width
> limitation of SSPP and MDP clock rate constrain. This patch set
> extends number of pipes to 4 and revis
On Tue, Apr 8, 2025 at 12:27 AM Daniel Thompson wrote:
> On Mon, Apr 07, 2025 at 05:51:17PM +0800, Pengyu Luo wrote:
> > Kinetic ktz8866, found in many android devices, nowadays, some oem use
> > dual ktz8866 to support a larger panel and higher brightness, original
> > driver would only handle h
On Tue, Apr 8, 2025 at 12:27 AM Daniel Thompson wrote:
> On Mon, Apr 07, 2025 at 05:51:17PM +0800, Pengyu Luo wrote:
> > Kinetic ktz8866, found in many android devices, nowadays, some oem use
> > dual ktz8866 to support a larger panel and higher brightness, original
> > driver would only handle h
On Fri, Apr 18, 2025 at 6:51 PM Jocelyn Falempe wrote:
>
> Link:
> https://lore.kernel.org/dri-devel/caniq72ke45eowckmhwhvmwxc03dxr4rnxxkvx+hvwdblopz...@mail.gmail.com/
> [1]
Thanks for fixing that -- some tags for your consideration:
Reported-by: Miguel Ojeda
Closes:
https://lore.kernel.org
On Mon, Apr 7, 2025 at 6:00 PM Krzysztof Kozlowski wrote:
> On 07/04/2025 11:51, Pengyu Luo wrote:
> > Kinetic ktz8866, found in many android devices, nowadays, some oem use
> > dual ktz8866 to support a larger panel and higher brightness, original
> > driver would only handle half backlight regi
Hi Mauro,
kernel test robot noticed the following build errors:
[auto build test ERROR on lwn/docs-next]
[also build test ERROR on drm-i915/for-linux-next drm-i915/for-linux-next-fixes
linus/master v6.15-rc2 next-20250417]
[cannot apply to masahiroy-kbuild/for-next masahiroy-kbuild/fixes]
[If yo
Hi!
> Function dispc_ovl_setup is not intended to work with the value OMAP_DSS_WB
> of the enum parameter plane.
>
> The value of this parameter is initialized in dss_init_overlays and in the
> current state of the code it cannot take this value so it's not a real
> problem.
>
> For the purposes
The i915_oa_stream_destroy() function directly accesses the
ratelimit_state structure's ->missed field, which work, but which also
makes it more difficult to change this field. Therefore, make use of
the ratelimit_state_get_miss() function instead of directly accessing
the ->missed field.
Signed-
The amdgpu_set_thermal_throttling_logging() function directly accesses
the ratelimit_state structure's ->missed field, which work, but which
also makes it more difficult to change this field. Therefore, make
use of the ratelimit_state_reset_miss() function instead of directly
accessing the ->misse
Recently added Initial LTTPR support in msm/dp has configured LTTPR(s)
to non-transparent mode to enable video output on X1E-based devices
that come with LTTPR on the motherboards. However, video would not work
if additional LTTPR(s) are present between sink and source, which is
the case for USB Ty
Hi Konstantin,
At 2025-04-17 14:57:58, "Konstantin Shabanov" wrote:
>As it isn't supported by hardware. At least, RK3399 doesn't support
>it. From the datasheet[1]
>("1.2.10 Video IN/OUT", "Display Interface", p. 17):
>
> Support AFBC function co-operation with GPU
>* support 2560x1600 UI
On Tue, Apr 15, 2025 at 8:33 AM Wentao Liang wrote:
>
> In vegam_populate_smc_boot_level(), the return value of
> phm_find_boot_level() is 0 or negative error code and the
> "if (result)" branch statement will never run into the true
> branch. Besides, this will skip setting the voltages later
> b
On Fri, 11 Apr 2025 19:59:37 +0800, Andy Yan wrote:
> It is not recommended for drivers to include UAPI header
> directly.
>
>
Applied to drm-misc-next, thanks!
[1/1] drm/bridge: dw-hdmi: Avoid including uapi headers
commit: 4890d68db651562ea80250f2c93205a5c0327a6a
Best regards,
--
With
From: Dmitry Baryshkov
Add compatible and device configuration for the Qualcomm SAR2130P
platform.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_mdss.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
On 01/04/2025 07:11, Dmitry Baryshkov wrote:
The analogix_dp_prepare_panel() returns immediately if there is no
attached panel. Drop several calls to this function which are performed
when dp->plat_data->panel is NULL.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/bridge/analogix/analog
drm_file will be used in usermode queues code to
enable better process information in logging and hence
add drm_file part of the userq_mgr struct.
update the drm_file pointer in userq_mgr for each
amdgpu_driver_open_kms.
Signed-off-by: Sunil Khatri
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/d
Hi Steve,
On 17.04.2025 15:25, Steven Price wrote:
> On 15/04/2025 20:15, Adrián Larumbe wrote:
> > Add a device DebugFS file that displays a complete list of all the DRM
> > GEM objects that are exposed to UM through a DRM handle.
> >
> > Since leaking object identifiers that might belong to a di
Convert fsl,tcon.txt to yaml format.
Signed-off-by: Frank Li
---
.../devicetree/bindings/display/fsl,tcon.txt | 17
.../bindings/display/fsl,vf610-tcon.yaml | 43 +++
MAINTAINERS | 2 +-
3 files changed, 44 insertions(+), 18 delet
On Thu, Apr 17, 2025 at 02:42:24PM -0400, Lyude Paul wrote:
> On Fri, 2025-04-11 at 01:55 +0200, Danilo Krummrich wrote:
> > +/// A base GEM object.
> > +///
> > +/// Invariants
> > +///
> > +/// `self.dev` is always a valid pointer to a `struct drm_device`.
> > +#[repr(C)]
> > +#[pin_data]
> > +pu
On 11/04/2025 21:19, Luca Ceresoli wrote:
Add power on/off delays for the Tianma TM070JDHG34-00.
Fixes: bf6daaa281f7 ("drm/panel: simple: Add Tianma TM070JDHG34-00 panel
support")
Cc: sta...@vger.kernel.org
Signed-off-by: Luca Ceresoli
---
Changed in v3:
- add Fixes: and Cc:
- remove regulat
Hi Geert,
Thanks for your feedback!
> From: Geert Uytterhoeven
> Sent: 16 April 2025 10:27
> Subject: Re: [PATCH v2 01/15] clk: renesas: rzv2h-cpg: Add support for DSI
> clocks
>
> Hi Prabhakar, Fabrizio,
>
> Thanks for your patch!
>
> On Tue, 8 Apr 2025 at 22:09, Prabhakar wrote:
> > From:
Convert ldb.txt to yaml format.
Additional changes
- fix clock-names order to match existed dts file.
- remove lvds-panel and iomuxc-gpr node in examples.
- fsl,imx6q-ldb fail back to fsl,imx53-ldb.
- add fsl,panel property to match existed dts.
Signed-off-by: Frank Li
---
change from v1 to v2
-
On Fri, Apr 18, 2025 at 11:37:21AM -0400, Tamir Duberstein wrote:
> Before Rust 1.29.0, Clippy introduced the `cast_lossless` lint [1]:
>
> > Rust’s `as` keyword will perform many kinds of conversions, including
> > silently lossy conversions. Conversion functions such as `i32::from`
> > will only
On Fri, Apr 18, 2025 at 11:37:20AM -0400, Tamir Duberstein wrote:
> In Rust 1.63.0, Clippy introduced the `as_underscore` lint [1]:
>
> > The conversion might include lossy conversion or a dangerous cast that
> > might go undetected due to the type being inferred.
> >
> > The lint is allowed by de
On 32bits ARM, u64/u64 is not supported [1], so change the algorithm
to use a simple fifo with decimal digits as u8 instead.
This is slower but should compile on all architecture.
Link:
https://lore.kernel.org/dri-devel/caniq72ke45eowckmhwhvmwxc03dxr4rnxxkvx+hvwdblopz...@mail.gmail.com/
[1]
Sign
On Fri, Apr 18, 2025 at 11:37:18AM -0400, Tamir Duberstein wrote:
> In Rust 1.72.0, Clippy introduced the `ptr_cast_constness` lint [1]:
>
> > Though `as` casts between raw pointers are not terrible,
> > `pointer::cast_mut` and `pointer::cast_const` are safer because they
> > cannot accidentally c
Initialize LTTPR before msm_dp_panel_read_sink_caps, as DPTX shall
(re)read DPRX caps after LTTPR detection, as required by DP 2.1,
Section 3.6.7.6.1.
Signed-off-by: Aleksandrs Vinarskis
---
drivers/gpu/drm/msm/dp/dp_display.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
Hi Dave, Simona
The first drm-xe-next PR towards 6.16 Nothing major worth pointing out,
a lot of work and improvents all over the drivers. There is a drm_gpusvm
kernel-doc fix that touches core drm.
Thanks,
Thomas
drm-xe-next-2025-04-17:
Core Changes:
Fix drm_gpusvm kernel-doc (Lucas)
Driver Ch
From: Himal Prasad Ghimiray
This commit adds a new flag, vram_only, to the drm_gpusvm structure. The
purpose of this flag is to ensure that the get_pages function allocates
memory exclusively from the device's VRAM. If the allocation from VRAM
fails, the function will return an -EFAULT error.
Si
On Fri, 11 Apr 2025 18:09:40 +0300, Dmitry Baryshkov wrote:
> The aux bridge uses devm_drm_of_get_bridge() from the panel bridge (and
> correctly selects DRM_PANEL_BRIDGE). However panel bridge is not a
> separate module, it is compiled into the drm_kms_helper.o. Select
> DRM_KMS_HELPER too to expr
drm_file will be used in usermode queues code to
enable better process information in logging and hence
add drm_file part of the userq_mgr struct.
update the drm_file pointer in userq_mgr for each
amdgpu_driver_open_kms.
Signed-off-by: Sunil Khatri
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
Continuing the theme from previous patches. This time round we deal with
the problem that it is possible to unbind the driver from the PCI device
with an active sync file fence.
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
Cc: Danilo Krummrich
Cc: Lucas De Marchi
Cc: Matthew Brost
Cc: Ph
Hi all,
Recently I mentioned to Danilo about some fence lifetime issues so here is a
rough series, more than anything intended to start the discussion.
Most of the problem statement can be found in the first patch but to briefly
summarise - because sched fence can outlive the scheduler, we can tr
Thomas Zimmermann wrote:
> Hi
>
> Am 16.04.25 um 17:22 schrieb Wakko Warner:
> > Thomas Zimmermann wrote:
> > > Fix an off-by-one error when setting the vblanking start in
> > > . Commit d6460bd52c27 ("drm/mgag200: Add dedicated
> > > variables for blanking fields") switched the value from
> > > c
Xe and probably some other drivers can tear down the internal state
referenced by exported sync file fence which then causes a null pointer
derefences on accessing said fence.
This is somewhat related to DRM scheduler design where sched fence is
supposed to be allowed to outlive the scheduler inst
Continuing the theme from previous patches. This time round we deal with
the problem that it is possible to unbind the driver from the PCI device
with an active sync file fence.
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
Cc: Danilo Krummrich
Cc: Lucas De Marchi
Cc: Matthew Brost
Cc: Ph
Add a new character string Panthor BO field, and a function that allows
setting it from within the driver.
Driver takes care of freeing the string when it's replaced or no longer
needed at object destruction time, but allocating it is the responsibility
of callers.
Signed-off-by: Adrián Larumbe
On 4/17/2025 3:51 PM, Tvrtko Ursulin wrote:
On 17/04/2025 11:01, Sunil Khatri wrote:
Fix the below warning.
scheduler/sched_main.c:397: warning: Function parameter or struct
member 'result' not described in 'drm_sched_job_done'
Reviewed-by: Tvrtko Ursulin
Signed-off-by: Sunil Khatri
---
Similar to the previous patch lets precede the fence->ops dereference with
the signaled check. This reduces the window to hit the race where sync
file can get into a signaled DRM scheduler fence which was left "dangling"
after the driver had potentially torn down the corresponding internal
state.
On Fri, 18 Apr 2025 03:27:07 +0100
Adrián Larumbe wrote:
> + static const char * const gem_state_flags_names[] = {
> + [PANTHOR_DEBUGFS_GEM_STATE_FLAG_IMPORTED] = "imported",
> + [PANTHOR_DEBUGFS_GEM_STATE_FLAG_EXPORTED] = "exported",
Okay, I think I know where the fl
From: Ayushi Makhija
Document the DSI CTRL on the SA8775P Platform.
Signed-off-by: Ayushi Makhija
Reviewed-by: Krzysztof Kozlowski
---
.../devicetree/bindings/display/msm/dsi-controller-main.yaml| 2 ++
1 file changed, 2 insertions(+)
diff --git
a/Documentation/devicetree/bindings/displ
On Fri, Apr 18, 2025 at 2:18 AM Christophe JAILLET
wrote:
>
> Le 18/04/2025 à 02:21, li...@treblig.org a écrit :
> > From: "Dr. David Alan Gilbert"
> >
> > radeon_doorbell_free() was added in 2013 by
> > commit 75efdee11b5d ("drm/radeon: implement simple doorbell page
> > allocator")
> > but neve
There is a spelling mistake in macro CARMINE_TOTAL_DIPLAY_MEM. Fix it.
Signed-off-by: Colin Ian King
---
drivers/video/fbdev/carminefb.c | 8
drivers/video/fbdev/carminefb.h | 2 +-
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/video/fbdev/carminefb.c b/drivers/
If we unbind a driver from the PCI device with an active DRM client,
subsequent read of the fdinfo data associated with the file descriptor in
question will not end well.
Protect the path with a drm_dev_enter/exit() pair.
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
Cc: Lucas De Marchi
Cc
Hi Geert,
On Wed, Apr 16, 2025 at 10:27 AM Geert Uytterhoeven
wrote:
>
> Hi Prabhakar, Fabrizio,
>
> Thanks for your patch!
>
> On Tue, 8 Apr 2025 at 22:09, Prabhakar wrote:
> > From: Lad Prabhakar
> >
> > Add support for PLLDSI and PLLDSI divider clocks.
> >
> > The `renesas-rzv2h-dsi.h` heade
In Rust 1.72.0, Clippy introduced the `ptr_cast_constness` lint [1]:
> Though `as` casts between raw pointers are not terrible,
> `pointer::cast_mut` and `pointer::cast_const` are safer because they
> cannot accidentally cast the pointer to another type.
There are only 2 affected sites:
- `*mut T
On 4/18/2025 6:40 AM, Connor Abbott wrote:
> On Thu, Apr 17, 2025, 1:50 PM Akhil P Oommen wrote:
>>
>> On 4/17/2025 9:02 PM, Connor Abbott wrote:
>>> On Thu, Apr 17, 2025 at 3:45 AM Akhil P Oommen
>>> wrote:
On 4/10/2025 11:13 PM, Konrad Dybcio wrote:
> From: Konrad Dybcio
>
>
On 16/04/2025 14:24, Miguel Ojeda wrote:
On Wed, Apr 16, 2025 at 2:21 PM Miguel Ojeda wrote:
`///` should still be used for private items [1]. Some of the items in
this file do so already, so do it for a few other clear candidates in
the file.
I just pushed it to drm-misc-next
Thanks,
--
In Rust 1.63.0, Clippy introduced the `as_underscore` lint [1]:
> The conversion might include lossy conversion or a dangerous cast that
> might go undetected due to the type being inferred.
>
> The lint is allowed by default as using `_` is less wordy than always
> specifying the type.
Always sp
In Rust 1.66.0, Clippy introduced the `as_ptr_cast_mut` lint [1]:
> Since `as_ptr` takes a `&self`, the pointer won’t have write
> permissions unless interior mutability is used, making it unlikely
> that having it as a mutable pointer is correct.
There is only one affected callsite, and the chan
In Rust 1.51.0, Clippy introduced the `ptr_as_ptr` lint [1]:
> Though `as` casts between raw pointers are not terrible,
> `pointer::cast` is safer because it cannot accidentally change the
> pointer's mutability, nor cast the pointer to other types like `usize`.
There are a few classes of changes
In Rust 1.78.0, Clippy introduced the `ref_as_ptr` lint [1]:
> Using `as` casts may result in silently changing mutability or type.
While this doesn't eliminate unchecked `as` conversions, it makes such
conversions easier to scrutinize. It also has the slight benefit of
removing a degree of free
Before Rust 1.29.0, Clippy introduced the `cast_lossless` lint [1]:
> Rust’s `as` keyword will perform many kinds of conversions, including
> silently lossy conversions. Conversion functions such as `i32::from`
> will only perform lossless conversions. Using the conversion functions
> prevents con
This started with a patch that enabled `clippy::ptr_as_ptr`. Benno
Lossin suggested I also look into `clippy::ptr_cast_constness` and I
discovered `clippy::as_ptr_cast_mut`. This series now enables all 3
lints. It also enables `clippy::as_underscore` which ensures other
pointer casts weren't missed
On 4/16/2025 4:26 AM, Maciej Falkowski wrote:
From: Andrzej Kacprowski
Correct setup of D0i2 disable which was
by mistake set up to value 1 and use BIT(1) instead.
Fixes: 011529fe8112 ("accel/ivpu: Implement D0i2 disable test mode")
Signed-off-by: Andrzej Kacprowski
Signed-off-by: Maciej Falk
On 4/16/2025 4:26 AM, Maciej Falkowski wrote:
From: Karol Wachowski
Fix improper use of dct_active_percent field in DCT interrupt handler
causing DCT to never get enabled. Set dct_active_percent internally before
IPC to ensure correct driver value even if IPC fails.
Set default DCT value to 30
On 4/16/2025 4:25 AM, Maciej Falkowski wrote:
From: Karol Wachowski
Introduce a heartbeat-based Timeout Detection and Recovery (TDR) mechanism.
The enhancement aims to improve the reliability of device hang detection by
monitoring heartbeat updates.
Each progressing inference will update heart
On Thu, Apr 17, 2025 at 1:26 PM Song Liu wrote:
>
> On Thu, Apr 17, 2025 at 9:05 AM T.J. Mercier wrote:
> >
> > On Wed, Apr 16, 2025 at 9:56 PM Song Liu wrote:
> > >
> > > On Wed, Apr 16, 2025 at 7:09 PM T.J. Mercier wrote:
> > > >
> > > > On Wed, Apr 16, 2025 at 6:26 PM Song Liu wrote:
> > >
On Fri, Apr 18, 2025 at 11:09 AM Boqun Feng wrote:
>
> On Fri, Apr 18, 2025 at 08:08:02AM -0400, Tamir Duberstein wrote:
> > On Thu, Apr 17, 2025 at 4:12 PM Boqun Feng wrote:
> > >
> > > On Thu, Apr 17, 2025 at 03:26:14PM -0400, Tamir Duberstein wrote:
> > > [...]
> > > > >
> > > > > > O
Hi Geert,
Thank you for the review.
On Wed, Apr 16, 2025 at 10:35 AM Geert Uytterhoeven
wrote:
>
> Hi Prabhakar, Fabrizio,
>
> On Tue, 8 Apr 2025 at 22:09, Prabhakar wrote:
> > From: Lad Prabhakar
> >
> > Add DSI support for Renesas RZ/V2H(P) SoC.
> >
> > Co-developed-by: Fabrizio Castro
> >
On Fri, Apr 18, 2025 at 08:08:02AM -0400, Tamir Duberstein wrote:
> On Thu, Apr 17, 2025 at 4:12 PM Boqun Feng wrote:
> >
> > On Thu, Apr 17, 2025 at 03:26:14PM -0400, Tamir Duberstein wrote:
> > [...]
> > > >
> > > > > Ok(())
> > > > > }
> > > > > diff --git a/rust/kernel/device_id.
Hi Geert,
Thank you for the review.
On Tue, Apr 15, 2025 at 4:51 PM Geert Uytterhoeven wrote:
>
> Hi Prabhakar,
>
> On Tue, 8 Apr 2025 at 22:09, Prabhakar wrote:
> > From: Lad Prabhakar
> >
> > Add clock and reset entries for the DSI and LCDC peripherals.
> >
> > Co-developed-by: Fabrizio Cast
Hi Geert,
Thank you for the review.
On Wed, Apr 16, 2025 at 10:27 AM Geert Uytterhoeven
wrote:
>
> Hi Prabhakar, Fabrizio,
>
> Thanks for your patch!
>
> On Tue, 8 Apr 2025 at 22:09, Prabhakar wrote:
> > From: Lad Prabhakar
> >
> > Add support for PLLDSI and PLLDSI divider clocks.
> >
> > The
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