From: Lad Prabhakar <prabhakar.mahadev-lad...@bp.renesas.com> Hi All,
This patch series adds support for the Display Unit (DU) and MIPI DSI interface on the Renesas RZ/V2H(P) SoC. The initial patches add PLLDSI clocks and reset entries for the DSI and LCDC and the later patches add support for the DU and DSI drivers. The DU block is similar to the RZ/G2L SoC, but the DSI interface is slightly different. The patches include updates to the device tree bindings, clock and reset controllers, and the DU driver to accommodate these changes. Note, my initial intention was to split the clock patches and the DU/DSI driver patches into two separate series. However, I found that sending them together will make it easier for the reviewers to understand clock related changes. Note, the clock patches apply on top of the below patch series: - https://lore.kernel.org/all/20250407165202.197570-1-prabhakar.mahadev-lad...@bp.renesas.com/ v2->v3: - Update the commit message for patch 1/15 to clarify the purpose of `renesas-rzv2h-dsi.h` header - Used mul_u32_u32() in rzv2h_cpg_plldsi_div_determine_rate() - Replaced *_mhz to *_millihz for clarity - Updated u64->u32 for fvco limits - Initialized the members in declaration order for RZV2H_CPG_PLL_DSI_LIMITS() macro - Used clk_div_mask() in rzv2h_cpg_plldsi_div_recalc_rate() - Replaced `unsigned long long` with u64 - Dropped rzv2h_cpg_plldsi_clk_recalc_rate() and reused rzv2h_cpg_pll_clk_recalc_rate() instead - In rzv2h_cpg_plldsi_div_set_rate() followed the same style of RMW-operation as done in the other functions - Renamed rzv2h_cpg_plldsi_set_rate() to rzv2h_cpg_pll_set_rate() - Dropped rzv2h_cpg_plldsi_clk_register() and reused rzv2h_cpg_pll_clk_register() instead - Added a gaurd in renesas-rzv2h-dsi.h header - Reverted CSDIV0_DIVCTL2() to use DDIV_PACK() - Renamed plleth_lpclk_div4 -> cdiv4_plleth_lpclk - Renamed plleth_lpclk -> plleth_lpclk_gear - Collected reviewed tag from Krzysztof for patch 3/15 - Dropped !dsi->info check in rzg2l_mipi_dsi_probe() as it is not needed. - Simplifed V2H DSI timings array to save space - Switched to use fsleep() instead of udelay() v1->v2: - Rebased the changes on top of v6.15-rc1 - Kept the sort order for schema validation - Added `port@1: false` for RZ/V2H(P) SoC - Added enum for RZ/V2H as suggested by Krzysztof as the list will grow in the future (while adding RZ/G3E SoC). - Added Reviewed-by tag from Biju and Krzysztof. - Replaced individual flags as reset flag - Dropped unused macros - Added missing LPCLK flag to rzvv2h info - Dropped FCP and VSP documentation patch and sent them separately Cheers, Prabhakar Lad Prabhakar (15): clk: renesas: rzv2h-cpg: Add support for DSI clocks clk: renesas: r9a09g057: Add clock and reset entries for DSI and LCDC dt-bindings: display: renesas,rzg2l-du: Add support for RZ/V2H(P) SoC dt-bindings: display: bridge: renesas,dsi: Add support for RZ/V2H(P) SoC drm: renesas: rz-du: Add support for RZ/V2H(P) SoC drm: renesas: rz-du: mipi_dsi: Add min check for VCLK range drm: renesas: rz-du: mipi_dsi: Simplify HSFREQ calculation drm: renesas: rz-du: mipi_dsi: Use VCLK for HSFREQ calculation drm: renesas: rz-du: mipi_dsi: Add OF data support drm: renesas: rz-du: mipi_dsi: Use mHz for D-PHY frequency calculations drm: renesas: rz-du: mipi_dsi: Add feature flag for 16BPP support drm: renesas: rz-du: mipi_dsi: Add dphy_late_init() callback for RZ/V2H(P) drm: renesas: rz-du: mipi_dsi: Add function pointers for configuring VCLK and mode validation drm: renesas: rz-du: mipi_dsi: Add support for LPCLK handling drm: renesas: rz-du: mipi_dsi: Add support for RZ/V2H(P) SoC .../bindings/display/bridge/renesas,dsi.yaml | 116 +++- .../bindings/display/renesas,rzg2l-du.yaml | 23 +- drivers/clk/renesas/r9a09g057-cpg.c | 63 +++ drivers/clk/renesas/rzv2h-cpg.c | 237 ++++++++- drivers/clk/renesas/rzv2h-cpg.h | 17 + drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c | 11 + .../gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 498 ++++++++++++++++-- .../drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h | 36 +- include/linux/clk/renesas-rzv2h-dsi.h | 211 ++++++++ 9 files changed, 1144 insertions(+), 68 deletions(-) create mode 100644 include/linux/clk/renesas-rzv2h-dsi.h -- 2.49.0
