As it isn't supported by hardware. At least, RK3399 doesn't support
it. From the datasheet[1]
("1.2.10 Video IN/OUT", "Display Interface", p. 17):
Support AFBC function co-operation with GPU
* support 2560x1600 UI
Manually tested on RockPro64 (rk3399):
- ARM_AFBC modifier is used for 1920x1
Em Wed, 16 Apr 2025 12:36:06 +0300
Andy Shevchenko escreveu:
> On Wed, Apr 16, 2025 at 05:29:01PM +0800, Mauro Carvalho Chehab wrote:
> > Em Wed, 16 Apr 2025 17:19:17 +0800
> > Mauro Carvalho Chehab escreveu:
> > > Em Wed, 16 Apr 2025 11:34:16 +0300
> > > Jani Nikula escreveu:
> > > > On We
> -Original Message-
> From: Intel-xe On Behalf Of Murthy,
> Arun R
> Sent: Friday, March 28, 2025 10:36 AM
> To: Pekka Paalanen
> Cc: intel...@lists.freedesktop.org; intel-...@lists.freedesktop.org; dri-
> de...@lists.freedesktop.org; Kandpal, Suraj ;
> harry.wentl...@amd.com; alex.h.
On 2025-04-14 22:55, Konrad Dybcio wrote:
On 3/15/25 3:57 PM, Barnabás Czémán wrote:
From: Dang Huynh
Add initial support for MSM8937 SoC.
Signed-off-by: Dang Huynh
Co-developed-by: Barnabás Czémán
Signed-off-by: Barnabás Czémán
---
[...]
+ power-domains = <&cpu_p
On Thu, Apr 17, 2025 at 02:16:31AM GMT, Dmitry Baryshkov wrote:
> From: Dmitry Baryshkov
>
> Describe DisplayPort controller present on Qualcomm SAR2130P platform.
>
> Signed-off-by: Dmitry Baryshkov
Addresses do not match. You re-authored the commit, so now everywhere is
mess.
Best regards,
On 17/04/2025 07:39, Ayushi Makhija wrote:
> From: Ayushi Makhija
>
> Document DSI controller and phy on SA8775P platform.
>
> Signed-off-by: Ayushi Makhija
Reviewed-by: Krzysztof Kozlowski
Best regards,
Krzysztof
Mixing GPU and CPU atomics does not work unless a strict migration
policy of GPU atomics must be device memory. Enforce a policy of must be
in VRAM with a retry loop of 2 attempts, if retry loop fails abort
fault.
v2:
- Only retry migration on atomics
- Drop alway migrate modparam
Signed-off-by
As it isn't supported by hardware. At least, RK3399 doesn't support
it. From the datasheet[1]
("1.2.10 Video IN/OUT", "Display Interface", p. 17):
Support AFBC function co-operation with GPU
* support 2560x1600 UI
Manually tested on RockPro64 (rk3399):
- ARM_AFBC modifier is used for 1920x1
Ensure GPU can make forward progress on an atomic SVM GPU fault by
giving the GPU a timeslice of 5ms
v2:
- Reduce timeslice to 5ms
- Double timeslice on retry
- Split out GPU SVM changes into independent patch
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/xe/xe_svm.c | 2 ++
1 file change
Add timeslicing support to GPU SVM which will guarantee the GPU a
minimum execution time on piece of physical memory before migration back
to CPU. Intended to implement strict migration policies which require
memory to be in a certain placement for correct execution.
Signed-off-by: Matthew Brost
Minimal set of patches to enable compute UMD SVM atomics.
Collaboration with Himal.
Matt
Himal Prasad Ghimiray (1):
drm/gpusvm: Introduce vram_only flag for VRAM allocation
Matthew Brost (4):
drm/xe: Strict migration policy for atomic SVM faults
drm/gpusvm: Add timeslicing support to GPU
Add some informal control for atomic SVM fault GPU timeslice to be able
to play around with values and tweak performance.
v2:
- Reduce timeslice default value to 5ms
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/xe/xe_debugfs.c | 38
drivers/gpu/drm/xe/xe_d
On Tue, Apr 15, 2025 at 6:23 AM Wentao Liang wrote:
>
> The return value of fiji_populate_smc_boot_level() is needs to be checked.
> An error handling is also needed to phm_find_boot_level() to reset the
> boot level when the function fails. A proper implementation can be found
> in tonga_populate
Add jobs to run KUnit tests using tools/testing/kunit/kunit.py tool.
Signed-off-by: Vignesh Raman
Reviewed-by: Maxime Ripard
---
v3:
- Add KUnit tests to the kunit stage.
v2:
- Use LLVM/Clang instead of GCC to avoid architecture-specific
toolchains for cross-compiling.
---
drivers/gp
Add jobs to run dt_binding_check and dtbs_check. If warnings are seen,
exit with a non-zero error code while configuring them as warning in
the GitLab CI pipeline.
Signed-off-by: Vignesh Raman
Reviewed-by: Maxime Ripard
Acked-by: Dmitry Baryshkov
---
v3:
- Add dt-binding-check and dtbs-check
Per-segment link training requires knowing the number of LTTPRs
(if any) present. Store the count during LTTPRs' initialization.
Signed-off-by: Aleksandrs Vinarskis
---
drivers/gpu/drm/msm/dp/dp_display.c | 17 +++--
drivers/gpu/drm/msm/dp/dp_link.h| 1 +
2 files changed, 12 ins
Take into account LTTPR capabilities when selecting maximum allowed
link rate, number of data lines.
Signed-off-by: Aleksandrs Vinarskis
---
drivers/gpu/drm/msm/dp/dp_display.c | 5 ++---
drivers/gpu/drm/msm/dp/dp_link.h| 3 +++
drivers/gpu/drm/msm/dp/dp_panel.c | 12 +++-
3 file
DisplayPort requires per-segment link training when LTTPR are switched
to non-transparent mode, starting with LTTPR closest to the source.
Only when each segment is trained individually, source can link train
to sink.
Implement per-segment link traning when LTTPR(s) are detected, to
support extern
On Wed, Apr 16, 2025 at 6:26 PM Song Liu wrote:
>
> On Wed, Apr 16, 2025 at 4:40 PM T.J. Mercier wrote:
> >
> > On Wed, Apr 16, 2025 at 4:08 PM Song Liu wrote:
> > >
> > > On Wed, Apr 16, 2025 at 3:51 PM T.J. Mercier wrote:
> > > [...]
> > > > >
> > > > > IIUC, the iterator simply traverses ele
On Wed, Mar 19, 2025 at 07:52:20AM -0700, Rob Clark wrote:
> From: Rob Clark
>
> It is standing in the way of drm_gpuvm / VM_BIND support. Not to
> mention frequently broken and rarely tested. And I think only needed
> for a 10yr old not quite upstream SoC (msm8974).
Well... MSM8974 is quite u
On Wed, Apr 16, 2025 at 4:40 PM T.J. Mercier wrote:
>
> On Wed, Apr 16, 2025 at 4:08 PM Song Liu wrote:
> >
> > On Wed, Apr 16, 2025 at 3:51 PM T.J. Mercier wrote:
> > [...]
> > > >
> > > > IIUC, the iterator simply traverses elements in a linked list. I feel
> > > > it is
> > > > an overkill t
On 4/15/25 11:25 PM, Stephen Rothwell wrote:
> Hi all,
>
> News: there will be no linux-next releases this coming Friday or Monday
> or next Friday.
>
> Changes since 20250415:
>
on x86_64:
ld: drivers/gpu/drm/xe/xe_vsec.o: in function `xe_vsec_init':
xe_vsec.c:(.text+0x21a): undefined refe
From: Dmitry Baryshkov
Add the SAR2130P compatible to clients compatible list, the device
require identity domain.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Konrad Dybcio
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/iommu/arm/ar
On Wed, Apr 16, 2025 at 4:08 PM Song Liu wrote:
>
> On Wed, Apr 16, 2025 at 3:51 PM T.J. Mercier wrote:
> [...]
> > >
> > > IIUC, the iterator simply traverses elements in a linked list. I feel it
> > > is
> > > an overkill to implement a new BPF iterator for it.
> >
> > Like other BPF iterators
From: Dmitry Baryshkov
Qualcomm SAR2130P requires slightly different setup for the DSI PHY. It
is a 5nm PHY (like SM8450), so supplies are the same, but the rest of
the configuration is the same as SM8550 DSI PHY.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c |
On Wed, Mar 19, 2025 at 07:52:18AM -0700, Rob Clark wrote:
> From: Rob Clark
>
> Just some tidying up.
Probably there is nothing more to say.
Reviewed-by: Dmitry Baryshkov
>
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/msm/msm_gpu.h | 44 +++
> 1 fil
From: Dmitry Baryshkov
Add display controller, two DSI hosts, two DSI PHYs and a single DP
controller. Link DP to the QMP Combo PHY.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sar2130p.dtsi | 395 +++
From: Dmitry Baryshkov
Add DPU driver support for the Qualcomm SAR2130P platform. It is mostly
the same as SM8550, minor differences in the CDP configuration.
Signed-off-by: Dmitry Baryshkov
---
.../drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h | 434 +
drivers/gpu/drm/msm
From: Dmitry Baryshkov
Describe the Mobile Display SubSystem (MDSS) device present on the
Qualcomm SAR2130P platform. It looks pretty close to SM8550 on the
system level. SAR2130P features two DSI hosts and single DisplayPort
controller.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Krzysztof Ko
From: Dmitry Baryshkov
Describe MIPI DSI PHY present on Qualcomm SAR2130P platform.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Krzysztof Kozlowski
---
Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/
From: Dmitry Baryshkov
Describe DisplayPort controller present on Qualcomm SAR2130P platform.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Krzysztof Kozlowski
---
Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation
From: Dmitry Baryshkov
Describe MIPI DSI controller present on Qualcomm SAR2130P platform.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Krzysztof Kozlowski
---
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git
a/Documen
On Wed, Mar 19, 2025 at 07:52:17AM -0700, Rob Clark wrote:
> From: Rob Clark
>
> This is a more descriptive name.
>
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +-
> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 6 ++--
> drivers/gpu/drm/msm/adreno/adreno_gpu.h
On Wed, Apr 16, 2025 at 3:51 PM T.J. Mercier wrote:
[...]
> >
> > IIUC, the iterator simply traverses elements in a linked list. I feel it is
> > an overkill to implement a new BPF iterator for it.
>
> Like other BPF iterators such as kmem_cache_iter or task_iter.
> Cgroup_iter iterates trees inst
On Wed, Apr 16, 2025 at 3:02 PM Song Liu wrote:
>
> On Mon, Apr 14, 2025 at 3:53 PM T.J. Mercier wrote:
> [...]
> > +
> > +BTF_ID_LIST_GLOBAL_SINGLE(bpf_dmabuf_btf_id, struct, dma_buf)
> > +DEFINE_BPF_ITER_FUNC(dmabuf, struct bpf_iter_meta *meta, struct dma_buf
> > *dmabuf)
> > +
> > +static voi
Reviewed-by: Alex Hung
On 4/13/25 21:14, Wentao Liang wrote:
The function fill_stream_properties_from_drm_display_mode() calls the
function drm_hdmi_avi_infoframe_from_display_mode() and the
function drm_hdmi_vendor_infoframe_from_display_mode(), but does
not check its return value. Log the err
On Wed, Apr 16, 2025 at 04:58:18PM -0400, Alyssa Rosenzweig wrote:
> > - spin_lock_irqsave(&crtc->dev->event_lock, flags);
> > if (crtc->state->event) {
> > - drm_crtc_vblank_get(crtc);
> > - adp->event = crtc->state->event;
> > + spin_lock_irqsave(&crtc->dev->ev
Hi Dave, Simona,
Fixes for 6.15.
The following changes since commit 8ffd015db85fea3e15a77027fda6c02ced4d2444:
Linux 6.15-rc2 (2025-04-13 11:54:49 -0700)
are available in the Git repository at:
https://gitlab.freedesktop.org/agd5f/linux.git
tags/amd-drm-fixes-6.15-2025-04-16
for you to fe
On Wed, Apr 16, 2025 at 04:54:38PM -0400, Alyssa Rosenzweig wrote:
> > This is preferable to driver changes since keeps the device powered on
> > if the adpdrm module is not available during boot.
>
> Struggling to parse this sentence, do you mean to say:
>
> > Driver changes are preferred, since
On Mon, Apr 14, 2025 at 3:53 PM T.J. Mercier wrote:
[...]
> +
> +BTF_ID_LIST_GLOBAL_SINGLE(bpf_dmabuf_btf_id, struct, dma_buf)
> +DEFINE_BPF_ITER_FUNC(dmabuf, struct bpf_iter_meta *meta, struct dma_buf
> *dmabuf)
> +
> +static void *dmabuf_iter_seq_start(struct seq_file *seq, loff_t *pos)
> +{
>
On Wed, Apr 16, 2025 at 4:34 AM Christian König
wrote:
>
>
>
> Am 15.04.25 um 19:19 schrieb Juan Yescas:
> > This change sets the allocation orders for the different page sizes
> > (4k, 16k, 64k) based on PAGE_SHIFT. Before this change, the orders
> > for large page sizes were calculated incorrect
Convert ldb.txt to yaml format.
Additional changes
- fix clock-names order to match existed dts file.
- remove lvds-panel and iomuxc-gpr node in examples.
- fsl,imx6q-ldb fail back to fsl,imx53-ldb.
Signed-off-by: Frank Li
---
.../bindings/display/imx/fsl,imx6q-ldb.yaml | 182
On Tue, 15 Apr 2025, Jani Nikula wrote:
> Resend of Egor's patches [1].
>
> [1] https://lore.kernel.org/r/20250214110643.506740-1-sdore...@sdore.me
>
> Cc: Egor Vorontsov
>
> Egor Vorontsov (2):
> drm/edid: Implement DisplayID Type IX & X timing blocks parsing
> drm/edid: Refactor DisplayID t
Reviewed-by: Alyssa Rosenzweig
Le Wed , Apr 16, 2025 at 10:25:27PM +0200, Janne Grunau via B4 Relay a écrit :
> From: Janne Grunau
>
> The lock is used in the interrupt handler so use spin_lock_irqsave to
> disable interrupts and avoid deadlocks with the irq handler.
>
> Fixes: 332122eba628 ("
lank interrupts in crtc's
.atomic_enable" then uses the expected drm_crtc_vblank_on() call to
enable vblank interrupts.
[Patch 4/4] "drm: adp: Remove pointless irq_lock spinlock" removes an
unnecessary spinlock protecting the irq handler from itself.
[1]
https://lore.kernel.org
Hello Doug,
On 13/04/25 07:22, Doug Anderson wrote:
Hi,
On Fri, Apr 11, 2025 at 2:23 AM Jayesh Choudhary wrote:
Enable NO_EOT and SYNC flags for DSI to use VIDEO_SYNC_PULSE_MODE
with EOT disabled.
Any chance you could add some details to this commit message? Your
subject says that these fl
On 4/15/25 11:25 PM, Stephen Rothwell wrote:
> Hi all,
>
> News: there will be no linux-next releases this coming Friday or Monday
> or next Friday.
>
> Changes since 20250415:
on x86_64:
# CONFIG_SHMEM is not set
CONFIG_DRM_TTM=m
ERROR: modpost: "shmem_writeout" [drivers/gpu/drm/ttm/ttm.ko
From: Janne Grunau
drm_crtc_vblank_get() may fail when it's called before
drm_crtc_vblank_on() on a resetted CRTC. This occurs in
drm_crtc_helper_funcs' atomic_flush() calls after
drm_atomic_helper_crtc_reset() for example directly after probe.
Send the vblank event directly in such cases.
Avoids
Reviewed-by: Alyssa Rosenzweig
Le Wed , Apr 16, 2025 at 10:25:30PM +0200, Janne Grunau via B4 Relay a écrit :
> From: Janne Grunau
>
> Interrupt handlers run with interrupts disabled so it is not necessary
> to protect them against reentrancy.
>
> Signed-off-by: Janne Grunau
> ---
> drivers/
Reviewed-by: Alyssa Rosenzweig
Le Wed , Apr 16, 2025 at 10:25:29PM +0200, Janne Grunau via B4 Relay a écrit :
> From: Janne Grunau
>
> Calling drm_crtc_vblank_on() drm_crtc_helper_funcs' atomic_enable is
> expected to enable vblank interrupts. It may have been avoided here to
> due to drm_crtc_
> - spin_lock_irqsave(&crtc->dev->event_lock, flags);
> if (crtc->state->event) {
> - drm_crtc_vblank_get(crtc);
> - adp->event = crtc->state->event;
> + spin_lock_irqsave(&crtc->dev->event_lock, flags);
> +
> + if (drm_crtc_vblank_get(crtc)
> This is preferable to driver changes since keeps the device powered on
> if the adpdrm module is not available during boot.
Struggling to parse this sentence, do you mean to say:
> Driver changes are preferred, since that patch keeps the device
> powered on if the adpdrm module is not available
On 4/16/25 10:33 PM, barnabas.cze...@mainlining.org wrote:
> On 2025-04-14 22:55, Konrad Dybcio wrote:
>> On 3/15/25 3:57 PM, Barnabás Czémán wrote:
>>> From: Dang Huynh
>>>
>>> Add initial support for MSM8937 SoC.
>>>
>>> Signed-off-by: Dang Huynh
>>> Co-developed-by: Barnabás Czémán
>>> Signed
From: Janne Grunau
The lock is used in the interrupt handler so use spin_lock_irqsave to
disable interrupts and avoid deadlocks with the irq handler.
Fixes: 332122eba628 ("drm: adp: Add Apple Display Pipe driver")
Signed-off-by: Janne Grunau
---
drivers/gpu/drm/adp/adp_drv.c | 5 +++--
1 file
On 2025-04-14 22:55, Konrad Dybcio wrote:
On 3/15/25 3:57 PM, Barnabás Czémán wrote:
From: Dang Huynh
Add initial support for MSM8937 SoC.
Signed-off-by: Dang Huynh
Co-developed-by: Barnabás Czémán
Signed-off-by: Barnabás Czémán
---
[...]
+ power-domains = <&cpu_p
On Wed, Dec 18, 2024 at 10:08:26PM +0100, A. Sverdlin wrote:
> From: Alexander Sverdlin
>
> Add bindings for Texas Instruments' LP8864/LP8866 LED-backlight drivers.
> Note that multiple channels in these models are used for load-balancing and
> brightness is controlled gobally, so from a user per
From: Janne Grunau
Interrupt handlers run with interrupts disabled so it is not necessary
to protect them against reentrancy.
Signed-off-by: Janne Grunau
---
drivers/gpu/drm/adp/adp_drv.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/adp/adp_drv.c b/drivers/gpu/drm/a
From: Janne Grunau
Calling drm_crtc_vblank_on() drm_crtc_helper_funcs' atomic_enable is
expected to enable vblank interrupts. It may have been avoided here to
due to drm_crtc_vblank_get()'s error behavior after
drm_crtc_vblank_reset(). With that fixed in the preceding change the
driver can call d
On Wed, Apr 16, 2025 at 11:11:03AM -0700, Matthew Brost wrote:
> Minimal set of patches to enable compute UMD SVM atomics.
>
> Collaboration with Himal.
>
> Sending as RFC to see if we should pursue merging this series ASAP, the
> solution of timeslicing may not be the final solution but it is qu
From: Himal Prasad Ghimiray
This commit adds a new flag, vram_only, to the drm_gpusvm structure. The
purpose of this flag is to ensure that the get_pages function allocates
memory exclusively from the device's VRAM. If the allocation from VRAM
fails, the function will return an -EFAULT error.
Si
On Tue, 15 Apr 2025 17:29:42 -0400, Frank Li wrote:
> Convert fsl-imx-drm.txt to yaml format and create 5 yaml files for
> differences purpose.
>
> Additional changes:
> - add missed include file in examples.
> - add clocks, clock-names for ipu.
>
> Signed-off-by: Frank Li
> ---
> .../imx/fsl
On Wed, Apr 16, 2025 at 01:53:34PM -0400, Tamir Duberstein wrote:
> On Wed, Apr 16, 2025 at 1:51 PM Boqun Feng wrote:
> >
> > On Wed, Apr 16, 2025 at 01:36:10PM -0400, Tamir Duberstein wrote:
> > > In Rust 1.78.0, Clippy introduced the `ref_as_ptr` lint [1]:
> > >
> > > > Using `as` casts may resu
Add some informal control for atomic SVM fault GPU timeslice to be able
to play around with values and tweak performance.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/xe/xe_debugfs.c | 38
drivers/gpu/drm/xe/xe_device.c | 1 +
drivers/gpu/drm/xe/xe_de
Mixing GPU and CPU atomics does not work unless a strict migration
policy of GPU atomics must be device memory. Enforce a policy of must be
in VRAM with a retry loop of 2 attempts, if retry loop fails abort
fault.
Signed-off-by: Himal Prasad Ghimiray
Signed-off-by: Matthew Brost
---
drivers/gpu
Ensure GPU can make forward progress on an atomic SVM GPU fault by
giving the GPU a timeslice of 10 MS.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/drm_gpusvm.c | 9 +
drivers/gpu/drm/xe/xe_svm.c | 1 +
include/drm/drm_gpusvm.h | 5 +
3 files changed, 15 insertions(+)
diff
Minimal set of patches to enable compute UMD SVM atomics.
Collaboration with Himal.
Sending as RFC to see if we should pursue merging this series ASAP, the
solution of timeslicing may not be the final solution but it is quite
simple as a stopgate / software enabling.
Matt
Himal Prasad Ghimiray
-Wflex-array-member-not-at-end was introduced in GCC-14, and we are
getting ready to enable it, globally.
Use the `DEFINE_RAW_FLEX()` helper for a few on-stack definitions
of a flexible structure where the size of the flexible-array member
is known at compile-time, and refactor the rest of the cod
On Wed, Apr 16, 2025 at 01:36:10PM -0400, Tamir Duberstein wrote:
> In Rust 1.78.0, Clippy introduced the `ref_as_ptr` lint [1]:
>
> > Using `as` casts may result in silently changing mutability or type.
>
> While this doesn't eliminate unchecked `as` conversions, it makes such
> conversions easi
On Wed, Apr 16, 2025 at 1:51 PM Boqun Feng wrote:
>
> On Wed, Apr 16, 2025 at 01:36:10PM -0400, Tamir Duberstein wrote:
> > In Rust 1.78.0, Clippy introduced the `ref_as_ptr` lint [1]:
> >
> > > Using `as` casts may result in silently changing mutability or type.
> >
> > While this doesn't elimina
In Rust 1.63.0, Clippy introduced the `as_underscore` lint [1]:
> The conversion might include lossy conversion or a dangerous cast that
> might go undetected due to the type being inferred.
>
> The lint is allowed by default as using `_` is less wordy than always
> specifying the type.
Always sp
On 3/19/2025 8:22 PM, Rob Clark wrote:
> From: Rob Clark
>
> In the next commit, a way for userspace to opt-in to userspace managed
> VM is added. For this to work, we need to defer creation of the VM
> until it is needed.
>
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/msm/adreno/a6xx_g
In Rust 1.51.0, Clippy introduced the `ptr_as_ptr` lint [1]:
> Though `as` casts between raw pointers are not terrible,
> `pointer::cast` is safer because it cannot accidentally change the
> pointer's mutability, nor cast the pointer to other types like `usize`.
There are a few classes of changes
In Rust 1.66.0, Clippy introduced the `as_ptr_cast_mut` lint [1]:
> Since `as_ptr` takes a `&self`, the pointer won’t have write
> permissions unless interior mutability is used, making it unlikely
> that having it as a mutable pointer is correct.
There is only one affected callsite, and the chan
Before Rust 1.29.0, Clippy introduced the `cast_lossless` lint [1]:
> Rust’s `as` keyword will perform many kinds of conversions, including
> silently lossy conversions. Conversion functions such as `i32::from`
> will only perform lossless conversions. Using the conversion functions
> prevents con
In Rust 1.78.0, Clippy introduced the `ref_as_ptr` lint [1]:
> Using `as` casts may result in silently changing mutability or type.
While this doesn't eliminate unchecked `as` conversions, it makes such
conversions easier to scrutinize. It also has the slight benefit of
removing a degree of free
This started with a patch that enabled `clippy::ptr_as_ptr`. Benno
Lossin suggested I also look into `clippy::ptr_cast_constness` and I
discovered `clippy::as_ptr_cast_mut`. This series now enables all 3
lints. It also enables `clippy::as_underscore` which ensures other
pointer casts weren't missed
In Rust 1.72.0, Clippy introduced the `ptr_cast_constness` lint [1]:
> Though `as` casts between raw pointers are not terrible,
> `pointer::cast_mut` and `pointer::cast_const` are safer because they
> cannot accidentally cast the pointer to another type.
There are only 2 affected sites:
- `*mut T
On 3/19/2025 8:22 PM, Rob Clark wrote:
> From: Rob Clark
>
> Now that we've realigned deletion and allocation, switch over to using
> drm_gpuvm/drm_gpuva. This allows us to support multiple VMAs per BO per
> VM, to allow mapping different parts of a single BO at different virtual
> addresses, wh
On 3/19/2025 8:22 PM, Rob Clark wrote:
> From: Rob Clark
>
> It is standing in the way of drm_gpuvm / VM_BIND support. Not to
> mention frequently broken and rarely tested. And I think only needed
> for a 10yr old not quite upstream SoC (msm8974).
>
> Maybe we can add support back in later, bu
On Wed, Apr 16, 2025 at 01:40:15PM +0200, Michal Wilczynski wrote:
>
>
> On 4/15/25 18:38, Conor Dooley wrote:
> > On Mon, Apr 14, 2025 at 08:52:56PM +0200, Michal Wilczynski wrote:
> >> Extend the TH1520 AON firmware bindings to describe the GPU clkgen reset
> >> line, required for proper GPU cl
On 16/04/2025 15:25, Michal Wilczynski wrote:
> On 2/19/25 15:02, Michal Wilczynski wrote:
>> All IMG Rogue GPUs include a reset line that participates in the
>> power-up sequence. On some SoCs (e.g., T-Head TH1520 and Banana Pi
>> BPI-F3), this reset line is exposed and must be driven explicitly t
Hi
Am 16.04.25 um 17:22 schrieb Wakko Warner:
Thomas Zimmermann wrote:
Fix an off-by-one error when setting the vblanking start in
. Commit d6460bd52c27 ("drm/mgag200: Add dedicated
variables for blanking fields") switched the value from
crtc_vdisplay to crtc_vblank_start, which DRM helpers cop
ommits/T-J-Mercier/dma-buf-Rename-and-expose-debugfs-symbols/20250415-065354
> base: https://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf-next.git net
> patch link:
> https://lore.kernel.org/r/20250414225227.3642618-3-tjmercier%40google.com
> patch subject: [PATCH 2/4] bpf: Add
Hi,
On Sat, Apr 12, 2025 at 9:00 PM Tejas Vipin wrote:
>
> Changes the boe-bf060y8m-aj0 panel to use multi style functions for
> improved error handling. Additionally the MIPI_DSI_MODE_LPM flag is set
> after the off commands are run in boe_bf060y8m_aj0_off regardless of any
> failures, and regul
On Wed, 16 Apr 2025 16:16:05 +0100
Steven Price wrote:
> On 15/04/2025 10:47, Boris Brezillon wrote:
> > On Mon, 14 Apr 2025 16:34:35 +0100
> > Steven Price wrote:
> >
> >> On 14/04/2025 13:47, Boris Brezillon wrote:
> >>> On Fri, 11 Apr 2025 16:39:02 +0200
> >>> Boris Brezillon wrote:
> >
On 15/04/2025 10:47, Boris Brezillon wrote:
> On Mon, 14 Apr 2025 16:34:35 +0100
> Steven Price wrote:
>
>> On 14/04/2025 13:47, Boris Brezillon wrote:
>>> On Fri, 11 Apr 2025 16:39:02 +0200
>>> Boris Brezillon wrote:
>>>
On Fri, 11 Apr 2025 15:13:26 +0200
Christian König wrote:
>>
On 14-04-2025 00:22, Lukas Wunner wrote:
On Fri, Apr 11, 2025 at 10:21:03AM +0530, Gupta, Nipun wrote:
On 10-04-2025 13:06, Krzysztof Kozlowski wrote:
On Wed, Apr 09, 2025 at 11:00:32PM GMT, Nipun Gupta wrote:
The AMD PKI accelerator driver provides a accel interface to interact
with the de
On Wed, 16 Apr 2025 15:26:42 +0100
Steven Price wrote:
> On 15/04/2025 11:57, Boris Brezillon wrote:
> > Right now the DRM_PANTHOR_BO_NO_MMAP flag is ignored by
> > panthor_ioctl_bo_mmap_offset(), meaning BOs with this flag set can
> > still be mmap-ed.
> >
> > Fortunately, this bug only impacts
Can you resend, I can't seem to find the original emails.
Additionally, all of the NISLANDS structures are unused in amdgpu, so
those could be removed.
Alex
On Wed, Apr 16, 2025 at 12:48 AM Gustavo A. R. Silva
wrote:
>
> Hi all,
>
> Friendly ping (second one): who can take this patch, please? 🙂
>
On Thu, 27 Feb 2025 23:43:29 +0100
Ulf Hansson wrote:
Hi Ulf,
sorry for the delay, I actually changed to code according to your comments
back then already, just now find time to come back to this.
> On Fri, 21 Feb 2025 at 02:00, Andre Przywara wrote:
> >
> > The Allwinner Power Reset Clock Man
On Fri, 21 Feb 2025 19:10:33 +0100
Jernej Škrabec wrote:
> Dne petek, 21. februar 2025 ob 01:57:59 Srednjeevropski standardni čas je
> Andre Przywara napisal(a):
> > The Allwinner Power Reset Clock Management (RPCM) block contains a few
> > bits that control some power domains. The most prominen
On 4/16/2025 7:55 PM, Jani Nikula wrote:
On Wed, 16 Apr 2025, Sunil Khatri wrote:
Add a drm helper macro which append the process information for
the drm_file over drm_err.
Signed-off-by: Sunil Khatri
---
include/drm/drm_file.h | 41 +
1 file changed,
On Wed, Apr 16, 2025 at 3:32 PM Michal Wilczynski
wrote:
>
> On 4/15/25 18:42, Rafael J. Wysocki wrote:
> > On Mon, Apr 14, 2025 at 8:53 PM Michal Wilczynski
> > wrote:
> >>
> >> Introduce a new dev_pm_info flag - platform_resources_managed, to
> >> indicate whether platform PM resources such as
> > The 3x4 CTM colorop is not yet explicit on whether it clamps its inputs
> > or outputs. Should all colorops be explicit about it?
> >
>
> Do we expect all HW/drivers to be able to support the same behavior?
> Is this critical to using the colorop?
It doesn't need to be the same on all hardware,
On 15/04/2025 11:57, Boris Brezillon wrote:
> Right now the DRM_PANTHOR_BO_NO_MMAP flag is ignored by
> panthor_ioctl_bo_mmap_offset(), meaning BOs with this flag set can
> still be mmap-ed.
>
> Fortunately, this bug only impacts user BOs, because kernel BOs are not
> exposed to userspace (they do
On 2/19/25 15:02, Michal Wilczynski wrote:
> All IMG Rogue GPUs include a reset line that participates in the
> power-up sequence. On some SoCs (e.g., T-Head TH1520 and Banana Pi
> BPI-F3), this reset line is exposed and must be driven explicitly to
> ensure proper initialization. On others, su
On Wed, 16 Apr 2025, Sunil Khatri wrote:
> Add a drm helper macro which append the process information for
> the drm_file over drm_err.
>
> Signed-off-by: Sunil Khatri
> ---
> include/drm/drm_file.h | 41 +
> 1 file changed, 41 insertions(+)
>
> diff --git
On 14/04/2025 14:01, Boris Brezillon wrote:
> The panthor_gpu_coherency_init() call has been moved around, but the
> error path hasn't been adjusted accordingly. Make sure we undo what
> has been done before this call in case of failure.
>
> Fixes: 7d5a3b22f5b5 ("drm/panthor: Call panthor_gpu_cohe
change the DRM_ERROR to drm_file_err to ad process name
and pid to the logging.
Signed-off-by: Sunil Khatri
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 52 +++
1 file changed, 29 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c
b
add process and pid information in the userqueue error
logging to make it more useful in resolving the error
by logs. drm_file_err logs pid and process name by
default.
Sample log:
[ 42.444297] [drm:amdgpu_userqueue_wait_for_signal [amdgpu]] *ERROR* Timed
out waiting for fence f=1c74d97
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