On 12/30/24 7:41 PM, Andre Przywara wrote:
> On Fri, 27 Dec 2024 20:06:30 +0530
> Parthiban wrote:
>
>> On 12/27/24 6:30 PM, Parthiban Nallathambi wrote:
>>> This series depends on [1] for the eMMC/MMC controller to work and
>>> [2] (lined up for 6.14) which adds support for the sram nodes and
>>
On Tue, Dec 31, 2024 at 01:43:11AM +0100, Martin Blumenstingl wrote:
> Hello Dmitry,
>
> this is great work - thanks for your efforts!
>
> To give some context:
> I am working on a HDMI controller driver for the Amlogic Meson8/8b/8m2
> SoCs. Unfortunately the driver is not mature enough for upstr
On Mon, Dec 30, 2024 at 08:32:30PM +, Srinivas Kandagatla wrote:
>
>
> On 30/12/2024 18:22, Dmitry Baryshkov wrote:
> > On Mon, Dec 30, 2024 at 04:15:42PM +, Srinivas Kandagatla wrote:
> > >
> > > On Wed, 18 Dec 2024 15:54:27 +0530, Ekansh Gupta wrote:
> > > > This patch series adds the
Quoting Miquel Raynal (2024-12-23 10:43:13)
> Hi Maxime,
>
> On 17/12/2024 at 13:47:53 +01, Maxime Ripard wrote:
>
> > On Thu, Nov 21, 2024 at 06:41:14PM +0100, Miquel Raynal wrote:
> >> There are mainly two ways to change a clock frequency.
> >
> > There's much more than that :)
>
> "mainly"
>
Quoting Miquel Raynal (2024-12-23 10:38:20)
> Hi Stephen,
>
> >> +/* do not passively change this clock rate during subtree rate
> >> propagation */
> >> +#define CLK_NO_RATE_CHANGE_DURING_PROPAGATION BIT(14)
> >
> > Why doesn't rate locking work?
>
> Can you be more specific? What function from
On Thu, 19 Dec 2024 08:25:29 +0100, Ahmad Fatoum wrote:
> Add compatible strings for TI SN65LVDS822, a FlatLink LVDS receiver.
>
> Signed-off-by: Ahmad Fatoum
> ---
> To: Andrzej Hajda (maintainer:DRM DRIVERS FOR
> BRIDGE CHIPS)
> To: Neil Armstrong (maintainer:DRM DRIVERS FOR
> BRIDGE CHIP
Hello Dmitry,
this is great work - thanks for your efforts!
To give some context:
I am working on a HDMI controller driver for the Amlogic Meson8/8b/8m2
SoCs. Unfortunately the driver is not mature enough for upstream
submission (all I have is the vendor driver which serves as reference).
That sa
From: Palmer Dabbelt
Without this I get
CC [M]
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn401/dcn401_resource.o
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn401/dcn401_resource.c: In
function ‘dcn401_dpp_create’:
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn401/dcn
On Thu, Dec 26, 2024 at 02:51:12PM -0800, Jessica Zhang wrote:
>
>
> On 12/19/2024 9:44 PM, Dmitry Baryshkov wrote:
> > On Mon, Dec 16, 2024 at 04:43:28PM -0800, Jessica Zhang wrote:
> > > We cannot support both CWB and CDM simultaneously as this would require
> > > 2 CDM blocks and currently our
On Mon, Dec 30, 2024 at 10:44:25PM +0100, Marek Vasut wrote:
> On 12/30/24 8:04 AM, Ying Liu wrote:
> > On 12/26/2024, Marek Vasut wrote:
> > > On 12/24/24 5:21 AM, Dmitry Baryshkov wrote:
> > > > On Tue, Dec 24, 2024 at 02:46:14AM +0100, Marek Vasut wrote:
> > > > > The dw-hdmi output_port is set
On Mon, Dec 30, 2024 at 11:11:35PM +0100, Marek Vasut wrote:
> On 12/30/24 8:18 AM, Liu Ying wrote:
>
> [...]
>
> > > diff --git a/drivers/gpu/drm/mxsfb/Kconfig b/drivers/gpu/drm/mxsfb/Kconfig
> > > index 264e74f455547..07fb6901996ae 100644
> > > --- a/drivers/gpu/drm/mxsfb/Kconfig
> > > +++ b/dr
On Tue, 31 Dec 2024 02:41:05 +0530, Akhil P Oommen wrote:
> Add a new schema which extends opp-v2 to support a new vendor specific
> property required for Adreno GPUs found in Qualcomm's SoCs. The new
> property called "qcom,opp-acd-level" carries a u32 value recommended
> for each opp needs to b
On 12/30/24 8:04 AM, Ying Liu wrote:
On 12/26/2024, Marek Vasut wrote:
On 12/24/24 5:21 AM, Dmitry Baryshkov wrote:
On Tue, Dec 24, 2024 at 02:46:14AM +0100, Marek Vasut wrote:
The dw-hdmi output_port is set to 1 in order to look for a connector
next bridge in order to get DRM_BRIDGE_ATTACH_NO
On 12/30/24 8:18 AM, Liu Ying wrote:
[...]
diff --git a/drivers/gpu/drm/mxsfb/Kconfig b/drivers/gpu/drm/mxsfb/Kconfig
index 264e74f455547..07fb6901996ae 100644
--- a/drivers/gpu/drm/mxsfb/Kconfig
+++ b/drivers/gpu/drm/mxsfb/Kconfig
@@ -30,6 +30,7 @@ config DRM_IMX_LCDIF
select DRM_CLIEN
On 12/30/24 7:57 AM, Liu Ying wrote:
[...]
diff --git a/drivers/gpu/drm/bridge/imx/Kconfig
b/drivers/gpu/drm/bridge/imx/Kconfig
index 9a480c6abb856..d8e9fbf75edbb 100644
--- a/drivers/gpu/drm/bridge/imx/Kconfig
+++ b/drivers/gpu/drm/bridge/imx/Kconfig
@@ -27,6 +27,7 @@ config DRM_IMX8MP_DW_HDM
On 12/30/24 8:29 AM, Liu Ying wrote:
[...]
@@ -139,21 +140,35 @@ static int mxsfb_attach_bridge(struct mxsfb_drm_private
*mxsfb)
if (!bridge)
return -ENODEV;
- ret = drm_bridge_attach(&mxsfb->encoder, bridge, NULL, 0);
+ ret = drm_bridge_attach(&mxsfb->encoder
Now that we have ACD support for GPU, add additional OPPs up to
Turbo L3 which are supported across all existing SKUs.
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dt
Update GPU node to include acd level values.
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index 88805629ed2
Add a new schema which extends opp-v2 to support a new vendor specific
property required for Adreno GPUs found in Qualcomm's SoCs. The new
property called "qcom,opp-acd-level" carries a u32 value recommended
for each opp needs to be shared to GMU during runtime.
Also, update MAINTAINERS file inclu
Add a module param to disable ACD which will help to quickly rule it
out for any GPU issues.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 7 +++
drivers/gpu/drm/msm/adreno/adreno_device.c | 4
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/
Fix the following for qmp_get() errors:
1. Correctly handle probe defer for A6x GPUs
2. Ignore other errors because those are okay when GPU ACD is
not required. They are checked again during gpu acd probe.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 5 +++--
1 file
ACD a.k.a Adaptive Clock Distribution is a feature which helps to reduce
the power consumption. In some chipsets, it is also a requirement to
support higher GPU frequencies. This patch adds support for GPU ACD by
sending necessary data to GMU and AOSS. The feature support for the
chipset is detecte
This series adds support for ACD feature for Adreno GPU which helps to
lower the power consumption on GX rail and also sometimes is a requirement
to enable higher GPU frequencies. At high level, following are the
sequences required for ACD feature:
1. Identify the ACD level data for each re
On Mon, 2024-12-30 at 16:03 -0500, Steven Rostedt wrote:
> >
>
> I'll start making it into an official patch. Can I add your "Tested-
> by" to it?
>
> -- Steve
Terrific thank you and sure:
Tested-by: Gene C
--
Gene
signature.asc
Description: This is a digitally signed message part
On Mon, 30 Dec 2024 15:52:14 -0500
Genes Lists wrote:
> On Mon, 2024-12-30 at 14:50 -0500, Steven Rostedt wrote:
> > On Mon, 30 Dec 2024 14:13:29 -0500
> > Steven Rostedt wrote:
> >
> > > I guess the "fix" would be to have the check code ignore pointer to
> > > arrays, assuming they are "ok".
On Mon, 2024-12-30 at 14:50 -0500, Steven Rostedt wrote:
> On Mon, 30 Dec 2024 14:13:29 -0500
> Steven Rostedt wrote:
>
> > I guess the "fix" would be to have the check code ignore pointer to
> > arrays, assuming they are "ok".
>
> Can you try this patch?
>
> -- Steve
Confirmed - all quiet now
On 30/12/2024 18:22, Dmitry Baryshkov wrote:
On Mon, Dec 30, 2024 at 04:15:42PM +, Srinivas Kandagatla wrote:
On Wed, 18 Dec 2024 15:54:27 +0530, Ekansh Gupta wrote:
This patch series adds the listed bug fixes that have been missing
in upstream fastRPC driver:
- Page address for registe
On Mon, 2024-12-30 at 14:50 -0500, Steven Rostedt wrote:
> On Mon, 30 Dec 2024 14:13:29 -0500
> Steven Rostedt wrote:
>
> > I guess the "fix" would be to have the check code ignore pointer to
> > arrays, assuming they are "ok".
>
> Can you try this patch?
Yep will do. Will report back shortly.
On Mon, 30 Dec 2024 14:13:29 -0500
Steven Rostedt wrote:
> I guess the "fix" would be to have the check code ignore pointer to
> arrays, assuming they are "ok".
Can you try this patch?
-- Steve
diff --git a/kernel/trace/trace_events.c b/kernel/trace/trace_events.c
index 1545cc8b49d0..770e7ed91
On Mon, 30 Dec 2024 13:55:00 -0500
Genes Lists wrote:
> On Fri, 2024-12-27 at 11:15 -0500, Genes Lists wrote:
> > I have not had a chance to bisect this yet but since its in stable
> > thought it best to share sooner than later.
> >
> > If noone spots anything, I will do a bisect soon as I can.
On Fri, 2024-12-27 at 11:15 -0500, Genes Lists wrote:
> I have not had a chance to bisect this yet but since its in stable
> thought it best to share sooner than later.
>
> If noone spots anything, I will do a bisect soon as I can. Boot
> completes and aside from this error things seem fine.
>
>
On Mon, Dec 30, 2024 at 10:24 AM Boqun Feng wrote:
>
> On Sat, Dec 28, 2024 at 01:52:28AM -0800, Boqun Feng wrote:
> > On Fri, Dec 27, 2024 at 06:03:45PM -0800, Suren Baghdasaryan wrote:
> > > On Fri, Dec 27, 2024 at 4:19 PM Hillf Danton wrote:
> > > >
> > > > On Fri, 27 Dec 2024 04:59:22 -0800
>
On Mon, Dec 30, 2024 at 04:15:42PM +, Srinivas Kandagatla wrote:
>
> On Wed, 18 Dec 2024 15:54:27 +0530, Ekansh Gupta wrote:
> > This patch series adds the listed bug fixes that have been missing
> > in upstream fastRPC driver:
> > - Page address for registered buffer(with fd) is not calculate
A specific allocation for the encoder is not strictly necessary at this
point, but in order to implement dynamic configuration of VKMS (configFS),
it will be easier to have one allocation per encoder.
Reviewed-by: Maxime Ripard
Reviewed-by: José Expósito
Signed-off-by: Louis Chauvet
---
drive
A specific allocation for the connector is not strictly necessary
at this point, but in order to implement dynamic configuration of
VKMS (configFS), it will be easier to have one allocation per
connector.
Reviewed-by: Maxime Ripard
Reviewed-by: José Expósito
Signed-off-by: Louis Chauvet
---
dr
A specific allocation for the CRTC is not strictly necessary at this
point, but in order to implement dynamic configuration of VKMS (configFS),
it will be easier to have one allocation per CRTC.
Signed-off-by: Louis Chauvet
---
drivers/gpu/drm/vkms/vkms_crtc.c | 32 +
: f8a2397baf041a5cee408b082334bb09c7e161df
change-id: 20240909-b4-vkms-allocated-9f5508fa
prerequisite-message-id:
20241230-google-vkms-managed-v6-0-15c7d65cd...@bootlin.com
prerequisite-patch-id: b608594ad493a41000ee703792eac4b23f9e35dc
prerequisite-patch-id: 5697aa87c44bbf3eda8a1ba424465dc792545d4c
prerequisite-patch-id
The current VKMS driver uses non-managed function to create connectors. It
is not an issue yet, but in order to support multiple devices easily,
convert this code to use drm and device managed helpers.
Reviewed-by: Maxime Ripard
Reviewed-by: Maíra Canal
Signed-off-by: Louis Chauvet
---
drivers
The current VKMS driver uses non-managed function to create
writeback connectors. It is not an issue yet, but in order
to support multiple devices easily, convert this code to
use drm and device managed helpers.
Reviewed-by: José Expósito
Signed-off-by: Louis Chauvet
---
drivers/gpu/drm/vkms/vk
To allows driver to only use drmm objects, add helper to create
drm_writeback_connectors with automated lifetime management.
Signed-off-by: Louis Chauvet
---
drivers/gpu/drm/drm_writeback.c | 69 +
include/drm/drm_writeback.h | 8 +
2 files change
The current VKMS driver uses non-managed function to create encoders. It
is not an issue yet, but in order to support multiple devices easily,
convert this code to use drm and device managed helpers.
Reviewed-by: Maxime Ripard
Reviewed-by: Maíra Canal
Signed-off-by: Louis Chauvet
---
drivers/g
Currently there is no cleanup function for writeback connectors. To allows
implementation of drmm variant of writeback connector, create a cleanup
function that can be used to properly remove all the writeback-specific
properties and allocations.
This also introduce an helper to cleanup only the d
To simplify the memory managment, this series replace all manual drm
object managment by drm-managed one. This way the VKMS code don't have to
manage it directly and the DRM core will handle the object destruction.
No functional changes are intended in this series.
PATCH 1/8: Migrate connector ma
The current implementation of drm_writeback_connector initialization does
not properly clean up all resources in case of failure (allocated
properties and possible_encoders). Add this cleaning in case of failure.
Signed-off-by: Louis Chauvet
---
drivers/gpu/drm/drm_writeback.c | 15 +++--
As the old drm and the new drmm variants of drm_writeback_connector
requires almost the same initialization, create an internal helper to do
most of the initialization work.
Signed-off-by: Louis Chauvet
---
drivers/gpu/drm/drm_writeback.c | 87 +
1 file ch
The current VKMS driver uses managed function to create crtc, but
don't use it to properly clean the crtc workqueue. It is not an
issue yet, but in order to support multiple devices easily,
convert this code to use drm and device managed helpers.
Reviewed-by: Maxime Ripard
Reviewed-by: Maíra Cana
On Sat, Dec 28, 2024 at 01:52:28AM -0800, Boqun Feng wrote:
> On Fri, Dec 27, 2024 at 06:03:45PM -0800, Suren Baghdasaryan wrote:
> > On Fri, Dec 27, 2024 at 4:19 PM Hillf Danton wrote:
> > >
> > > On Fri, 27 Dec 2024 04:59:22 -0800
> > > > Hello,
> > > >
> > > > syzbot found the following issue o
On Mon, 30 Dec 2024, Dmitry Baryshkov wrote:
> On Mon, Dec 30, 2024 at 03:18:35PM +0200, Jani Nikula wrote:
>> On Thu, 26 Dec 2024, Abel Vesa wrote:
>> > On 24-12-11 15:42:27, Johan Hovold wrote:
>> >> On Wed, Dec 11, 2024 at 03:04:12PM +0200, Abel Vesa wrote:
>> >>
>> >> > +/**
>> >> > + * drm
From: Tvrtko Ursulin
Instead of maintaining the dependencies in an xarray and then handling
them one by one every time the scheduler picks the same entity for
execution (requiring potentially multiple worker invocations for a job
to actually get submitted), lets maintain them in a dma_fence_array
From: Tvrtko Ursulin
Now that the run queue to scheduler relationship is always 1:1 we can
embed it (the run queue) directly in the scheduler struct and save on
some allocation error handling code and such.
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
Cc: Danilo Krummrich
Cc: Matthew Bro
From: Tvrtko Ursulin
Add a dma_fence_unwrap_merge_context() helper which works exactly the same
as the existing dma_fence_unwrap_merge() apart that instead of always
allocating a new fence context it allows the caller to specify it.
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
Cc: Danilo
From: Tvrtko Ursulin
There is no reason to queue just a single job if scheduler can take more
and re-queue the worker to queue more. We can simply feed the hardware
with as much as it can take in one go and hopefully win some latency.
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
Cc: Danil
From: Tvrtko Ursulin
Now that the scheduling policy is deadline based it feels completely
natural to allow propagating externaly set deadlines to the scheduler.
Scheduler deadlines are not a guarantee but as the dma-fence facility is
already in use by userspace lets wire it up.
Signed-off-by: T
From: Tvrtko Ursulin
If the new deadline policy is at least as good as FIFO and we can afford
to remove round-robin, we can simplify the scheduler code by making the
scheduler to run queue relationship always 1:1 and remove some code.
Also, now that the FIFO policy is gone the tree of entities i
From: Tvrtko Ursulin
If a job depends on another job from the same context it will be naturally
ordered by the submission queue. We can therefore ignore those before
adding them to the dependency tracking xarray.
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
Cc: Danilo Krummrich
Cc: Matth
From: Tvrtko Ursulin
No driver is using the update_job_credits() schduler vfunc
so lets remove it.
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
Cc: Danilo Krummrich
Cc: Matthew Brost
Cc: Philipp Stanner
---
drivers/gpu/drm/scheduler/sched_main.c | 13 -
include/drm/gpu_sch
From: Tvrtko Ursulin
Deadline scheduling policy should be a fairer flavour of FIFO with two
main advantages being that it can naturally connect with the dma-fence
deadlines, and secondly that it can get away with multiple run queues per
scheduler.
>From the latter comes the fairness advantage. W
From: Tvrtko Ursulin
Lets move all the code dealing with struct drm_sched_rq into a separate
compilation unit. Advantage being sched_main.c is left with a clearer set
of responsibilities.
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
Cc: Danilo Krummrich
Cc: Matthew Brost
Cc: Philipp Sta
From: Tvrtko Ursulin
Round-robin being the non-default policy and unclear how much it is used,
we can notice that it can be implemented using the FIFO data structures if
we only invent a fake submit timestamp which is monotonically increasing
inside drm_sched_rq instances.
So instead of remember
From: Tvrtko Ursulin
When a job's dependency is on a same scheduler we pipeline the two
directly to the backend by replacing the dependency with the scheduled
instead of the finished fence. Ordering is handled by the backend.
Instead of doing this fence substitution at the time of popping the jo
From: Tvrtko Ursulin
Move the code dealing with entities entering and exiting run queues to
helpers to logically separate it from jobs entering and exiting entities.
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
Cc: Danilo Krummrich
Cc: Matthew Brost
Cc: Philipp Stanner
---
drivers/gpu
From: Tvrtko Ursulin
Replacing FIFO with a flavour of deadline driven scheduling and removing round-
robin. Connecting the scheduler with dma-fence deadlines. First draft and
testing by different drivers and feedback would be nice. I was only able to test
it with amdgpu. Other drivers may not ev
From: Tvrtko Ursulin
There is no need to keep entities with no jobs in the tree so lets remove
it once the last job is consumed. This keeps the tree smaller which is
nicer and more efficient.
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
Cc: Danilo Krummrich
Cc: Matthew Brost
Cc: Philipp
On Wed, 18 Dec 2024 15:54:27 +0530, Ekansh Gupta wrote:
> This patch series adds the listed bug fixes that have been missing
> in upstream fastRPC driver:
> - Page address for registered buffer(with fd) is not calculated
> properly.
> - Page size calculation for non-registered buffer(copy buffe
From: Rob Clark
Debugging incorrect UAPI usage tends to be a bit painful, so add a
helper macro to make it easier to add debug logging which can be enabled
at runtime via drm.debug.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 21
drivers/gpu/drm/msm/msm_drv.
6.12-stable review patch. If anyone has any objections, please let me know.
--
From: John Harrison
[ Upstream commit 5dce85fecb87751ec94526e1ac516dd7871e2e0c ]
Adding lockdep checking to the coredump code showed that there was an
existing violation. The dev_coredumpm_timeout()
On Thu, Dec 19, 2024 at 10:52:32AM +0800, Yongbang Shi wrote:
> Does everyone have a question with the patch?
-:225: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'reg_value' - possible
side-effects?
#225: FILE: drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h:23:
+#define dp_field_modify(reg_value, ma
On Mon, Dec 30, 2024 at 07:04:51AM +, Ying Liu wrote:
> On 12/26/2024, Marek Vasut wrote:
> > On 12/24/24 5:21 AM, Dmitry Baryshkov wrote:
> > > On Tue, Dec 24, 2024 at 02:46:14AM +0100, Marek Vasut wrote:
> > >> The dw-hdmi output_port is set to 1 in order to look for a connector
> > >> next b
Hello,
On Wed, 25 Dec 2024 23:15:53 +0800
kerne test robot wrote:
> the WARN added in this commit is hit in our tests, below just FYI.
>
> kernel test robot noticed
> "WARNING:at_drivers/gpu/drm/drm_connector.c:#drm_connector_cleanup[drm]" on:
...
> [ 75.546607][ T377] i915 :00:02.0: [
Hi, Angelo:
AngeloGioacchino Del Regno 於
2024年12月19日 週四 下午7:27寫道：
>
> Registers DSI_VM_CMD and DSI_SHADOW_DEBUG start at different
> addresses in both MT8186 and MT8188 compared to the older IPs.
>
> Add two members in struct mtk_dsi_driver_data to specify the
> offsets for these two registers on
Hi, Fei:
Fei Shao 於 2024年11月5日 週二 下午5:02寫道：
>
> The MediaTek DP hardware supports audio and exposes a DAI, so the
> '#sound-dai-cells' property is needed for describing the DAI links.
>
> Reference the dai-common.yaml schema to allow '#sound-dai-cells' to be
> used, and filter out non-DP compatib
On Sat, Dec 28, 2024 at 09:20:17PM +, Jesse Van Gavere wrote:
> Hey all,
>
> (Hope this is not a duplicate as my first mail didn't seem to have
> gone through) For one of our new boards I have to get the ADV7513 chip
> working with TIDSS, the driver for this expects a bridge chip to have
> ato
On Tue, 17 Dec 2024, Jani Nikula wrote:
> Having cec.h include linux/debugfs.h leads to all users of all cec
> headers include and depend on debugfs.h and its dependencies for no
> reason. Drop the include from cec.h, and include debugfs.h and
> seq_file.h where needed.
>
> Sort all the modified i
Hi, Liankun:
Liankun Yang 於 2024年10月25日 週五 下午4:31寫道：
>
> Fix dp mode valid issue to avoid abnormal display of limit state.
>
> After DP passes link training, it can express the lane count of the
> current link status is good. Calculate the maximum bandwidth supported
> by DP using the current lan
On Thu, Dec 26, 2024 at 02:33:01PM +0800, Damon Ding wrote:
> Complete the register names of CMN_REG(0081) and CMN_REG(0087) to their
> full version, and it can help to better match the datasheet.
>
> Signed-off-by: Damon Ding
> ---
> drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 6 +++---
Hi, Liankun:
Liankun Yang 於 2024年10月25日 週五 下午4:32寫道：
>
> Setting up misc0 for Pixel Encoding Format.
>
> According to the definition of YCbCr in spec 1.2a Table 2-96,
> 0x1 << 1 should be written to the register.
>
> Use switch case to distinguish RGB, YCbCr422,
> and unsupported color formats.
On Fri, 27 Dec 2024 20:06:30 +0530
Parthiban wrote:
> On 12/27/24 6:30 PM, Parthiban Nallathambi wrote:
> > This series depends on [1] for the eMMC/MMC controller to work and
> > [2] (lined up for 6.14) which adds support for the sram nodes and
> > display engine extends it's usage. Idea of this
On Fri, 27 Dec 2024 18:31:05 +0530
Parthiban Nallathambi wrote:
Hi,
> Display clock uses 1 mixer without rotation support is same
> as v3s. There is also a hidden independent display engine
> with independent tcon_top available in A100/A133 bin (based
> on vendor BSP).
>
> Add new compatible fo
On Fri, 27 Dec 2024 18:30:53 +0530
Parthiban Nallathambi wrote:
Hi,
> A100/A133 uses one mixer without rotation support, which is same
> as sun8i v3s. Add it with fallback to v3s compatible.
>
> Signed-off-by: Parthiban Nallathambi
> ---
> .../devicetree/bindings/clock/allwinner,sun8i-a83t-de
On Mon, Dec 30, 2024 at 08:05:33AM +, Sandor Yu wrote:
>
> > On Wed, Dec 25, 2024 at 07:57:01AM +, Sandor Yu wrote:
> > > >
> > > > On Tue, Dec 17, 2024 at 02:51:47PM +0800, Sandor Yu wrote:
> > > > > Add a new DRM DisplayPort and HDMI bridge driver for Candence
> > > > MHDP8501
> > > > >
cocci warnings: (new ones prefixed by >>)
>> drivers/gpu/drm/mediatek/mtk_drm_drv.c:1092:2-3: Unneeded semicolon
Fixes: 4c932840db1d ("drm/mediatek: Implement OF graphs support for display
paths")
Reported-by: kernel test robot
Closes:
https://lore.kernel.org/oe-kbuild-all/202412022048.ky2zhxz4
On Mon, Dec 30, 2024 at 03:18:35PM +0200, Jani Nikula wrote:
> On Thu, 26 Dec 2024, Abel Vesa wrote:
> > On 24-12-11 15:42:27, Johan Hovold wrote:
> >> On Wed, Dec 11, 2024 at 03:04:12PM +0200, Abel Vesa wrote:
> >>
> >> > +/**
> >> > + * drm_dp_lttpr_set_transparent_mode - set the LTTPR in tran
On Thu, Dec 26, 2024 at 02:33:09PM +0800, Damon Ding wrote:
> With the previous patch related to the support of getting panel from
> the DP AUX bus, the &analogix_dp_device.aux can be obtained from the
> &analogix_dp_plat_data.aux.
>
> Furthermore, the assignment of &analogix_dp_plat_data.connecto
On 24.12.2024 9:51 AM, Krzysztof Kozlowski wrote:
> On 23/12/2024 22:31, Akhil P Oommen wrote:
>> On 12/23/2024 5:24 PM, Dmitry Baryshkov wrote:
>>> On Mon, Dec 23, 2024 at 12:31:27PM +0100, Konrad Dybcio wrote:
On 4.12.2024 7:18 PM, Akhil P Oommen wrote:
> On 11/16/2024 1:17 AM, Dmitry Ba
On Thu, 26 Dec 2024, Abel Vesa wrote:
> On 24-12-11 15:42:27, Johan Hovold wrote:
>> On Wed, Dec 11, 2024 at 03:04:12PM +0200, Abel Vesa wrote:
>>
>> > +/**
>> > + * drm_dp_lttpr_set_transparent_mode - set the LTTPR in transparent mode
>> > + * @aux: DisplayPort AUX channel
>> > + * @enable: Ena
On Mon, Dec 30, 2024 at 10:11:57AM +0800, Liu Ying wrote:
> i.MX8qxp Display Controller display engine consists of all processing
> units that operate in a display clock domain. Add minimal feature
> support with FrameGen and TCon so that the engine can output display
> timings. The FrameGen driv
On Thu, Dec 26, 2024 at 02:33:08PM +0800, Damon Ding wrote:
> Move drm_of_find_panel_or_bridge() a little later and combine it with
> component_add() into a new function rockchip_dp_link_panel(). The function
> will serve as done_probing() callback of devm_of_dp_aux_populate_bus(),
> aiding to supp
On Thu, Dec 26, 2024 at 02:33:05PM +0800, Damon Ding wrote:
> Add support to configurate link rate, lane count, voltage swing and
> pre-emphasis with phy_configure(). It is helpful in application scenarios
> where analogix controller is mixed with the phy of other vendors.
>
> Signed-off-by: Damon
On Thu, Dec 26, 2024 at 02:33:04PM +0800, Damon Ding wrote:
> Add max_link_rate and max_lane_count configs for RK3588.
>
> Signed-off-by: Damon Ding
> ---
> drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 4
> 1 file changed, 4 insertions(+)
>
Reviewed-by: Dmitry Baryshkov
--
With
On Thu, Dec 26, 2024 at 02:33:03PM +0800, Damon Ding wrote:
> Add basic support for RBR/HBR/HBR2 link rates, and the voltage swing and
> pre-emphasis configurations of each link rate have been verified according
> to the eDP 1.3 requirements.
Well... Please describe what's happening here. That the
On Mon, Dec 30, 2024 at 10:11:58AM +0800, Liu Ying wrote:
> i.MX8qxp Display Controller pixel engine consists of all processing
> units that operate in the AXI bus clock domain. Add drivers for
> ConstFrame, ExtDst, FetchLayer, FetchWarp and LayerBlend units, as
> well as a pixel engine driver, so
On Thu, Dec 26, 2024 at 02:33:02PM +0800, Damon Ding wrote:
> Adding the '_MASK' suffix to all registers ensures consistency in the
> naming convention for register macros throughout the file.
Nit: usually it would be "Add the '_MASK' suffix [...] in order to
ensure consistency [...]".
>
> Signe
On Thu, Dec 26, 2024 at 02:33:00PM +0800, Damon Ding wrote:
> According to the datasheet, setting the dig_clk_sel bit of CMN_REG(0097)
> to 1'b1 selects LCPLL as the reference clock, while setting it to 1'b0
> selects the ROPLL.
>
> Signed-off-by: Damon Ding
> ---
> drivers/phy/rockchip/phy-rock
On Mon, 30 Dec 2024 17:22:41 +0530, Anandu Krishnan E wrote:
> During fastrpc_rpmsg_probe, if secure device node registration
> succeeds but non-secure device node registration fails, the secure
> device node deregister is not called during error cleanup. Add proper
> exit paths to ensure proper
During fastrpc_rpmsg_probe, if secure device node registration
succeeds but non-secure device node registration fails, the secure
device node deregister is not called during error cleanup. Add proper
exit paths to ensure proper cleanup in case of error.
Fixes: 3abe3ab3cdab ("misc: fastrpc: add sec
From: Hermes Wu
When running the HDCP CTS test with UNIGRAF DPR-100.
KSV list must be read from DP_AUX_HDCP_KSV_FIFO in an AUX request,
and can not separate with multiple read requests.
The AUX operation command "CMD_AUX_GET_KSV_LIST" reads the KSV list
with AUX FIFO and is able to read DP_AUX_H
From: Hermes Wu
DisplayPort AUX protocol supports I2C transport which is capable of
reading EDID or supports MCCS.
In drm_dp_helper, drm_dp_i2c_xfer() packs I2C requests into a
sequence of AUX requests.
it6505_aux_i2c_operation() is implemented to match drm_dp_i2c_xfer()
operactions.
it6505_aux_
From: Hermes Wu
When HDCP negotiation with a repeater device.
Checking SHA V' matching must retry 3 times before restarting HDCP.
Signed-off-by: Hermes Wu
---
drivers/gpu/drm/bridge/ite-it6505.c | 32 +++-
1 file changed, 19 insertions(+), 13 deletions(-)
diff --gi
From: Hermes Wu
The hardware AUX FIFO is 16 bytes
Change definition of AUX_FIFO_MAX_SIZE to 16
Fixes: b5c84a9edcd4 ("drm/bridge: add it6505 driver")
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Hermes Wu
---
drivers/gpu/drm/bridge/ite-it6505.c | 2 +-
1 file changed, 1 insertion(+), 1 deletio
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