On Thu, Dec 26, 2024 at 02:33:00PM +0800, Damon Ding wrote: > According to the datasheet, setting the dig_clk_sel bit of CMN_REG(0097) > to 1'b1 selects LCPLL as the reference clock, while setting it to 1'b0 > selects the ROPLL. > > Signed-off-by: Damon Ding <damon.d...@rock-chips.com> > --- > drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) >
Reviewed-by: Dmitry Baryshkov <dmitry.barysh...@linaro.org> -- With best wishes Dmitry
