The commit 45b58669e532 ("drm/ssd130x: Allocate buffer in the plane's
.atomic_check() callback") moved the allocation of the intermediate and
HW buffers from the encoder's .atomic_enable callback to primary plane's
.atomic_check callback.
This was suggested by Maxime Ripard because drivers aren't
Thierry Reding writes:
Hello Thierry,
> From: Thierry Reding
>
> Tegra DRM doesn't support display on Tegra234 and later, so make sure
> not to remove any existing framebuffers in that case.
>
I see, this makes sense to me.
Acked-by: Javier Martinez Canillas
A couple of comments below thoug
Hi,
On 7/15/23 17:46, Randy Dunlap wrote:
> Mark the DRM_MODE_COLORIMETRY_COUNT enum value as private in
> kernel-doc to prevent a build warning:
>
> include/drm/drm_connector.h:527: warning: Enum value
> 'DRM_MODE_COLORIMETRY_COUNT' not described in enum 'drm_colorspace'
>
> Fixes: c627087cb16
On 8/29/2023 7:05 PM, Dmitry Baryshkov wrote:
On Tue, 29 Aug 2023 at 22:21, Abhinav Kumar wrote:
On 8/29/2023 12:15 PM, Dmitry Baryshkov wrote:
On Tue, 29 Aug 2023 at 22:09, Abhinav Kumar wrote:
On 8/29/2023 11:51 AM, Dmitry Baryshkov wrote:
On Tue, 29 Aug 2023 at 20:22, Abhinav Ku
On Tue, 29 Aug 2023 at 22:21, Abhinav Kumar wrote:
>
>
>
> On 8/29/2023 12:15 PM, Dmitry Baryshkov wrote:
> > On Tue, 29 Aug 2023 at 22:09, Abhinav Kumar
> > wrote:
> >>
> >>
> >>
> >> On 8/29/2023 11:51 AM, Dmitry Baryshkov wrote:
> >>> On Tue, 29 Aug 2023 at 20:22, Abhinav Kumar
> >>> wrote:
On 8/17/2023 12:27 PM, Abhinav Kumar wrote:
On 8/17/2023 11:50 AM, Dmitry Baryshkov wrote:
On 08/08/2023 02:49, Abhinav Kumar wrote:
On 6/4/2023 7:45 AM, Dmitry Baryshkov wrote:
The atomic_mode_set() callback only sets the phys_enc's IRQ data. As
the
INTF and WB are statically allocate
On 6/4/2023 7:45 AM, Dmitry Baryshkov wrote:
Follow the _dpu_encoder_irq_control() change and split the
_dpu_encoder_resource_control_helper() into enable and disable parts.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 45 +
1 file
On 6/4/2023 7:45 AM, Dmitry Baryshkov wrote:
The single helper for both enable and disable cases is too complicated,
especially if we start adding more code to these helpers. Split it into
irq_enable and irq_disable cases.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/d
On Wed, 30 Aug 2023 at 08:38, Danilo Krummrich wrote:
>
> nouveau_fence_emit() can fail before and after initializing the
> dma-fence and hence before and after initializing the dma-fence' kref.
>
> In order to avoid nouveau_fence_emit() potentially failing before
> dma-fence initialization pass t
nouveau_fence_emit() can fail before and after initializing the
dma-fence and hence before and after initializing the dma-fence' kref.
In order to avoid nouveau_fence_emit() potentially failing before
dma-fence initialization pass the channel to nouveau_fence_new() already
and perform the required
Javier Martinez Canillas writes:
> Geert Uytterhoeven writes:
>
>> The .need_pwm and .need_chargepump fields in struct ssd130x_deviceinfo
>> are flags that can have only two possible values: 0 and 1.
>> Reduce kernel size by changing their types from int to bool.
>>
>> Signed-off-by: Geert Uytte
Javier Martinez Canillas writes:
> Geert Uytterhoeven writes:
>
>> The native display format is monochrome light-on-dark (R1).
>> Hence add support for R1, so monochrome applications not only look
>> better, but also avoid the overhead of back-and-forth conversions
>> between R1 and XR24.
>>
>>
Javier Martinez Canillas writes:
[...]
> The change makes sense to me.
>
> Reviewed-by: Javier Martinez Canillas
>
I've also tested this patch now and found no regressions.
Tested-by: Javier Martinez Canillas
--
Best regards,
Javier Martinez Canillas
Core Platforms
Red Hat
Hi Dave
Nice to e-meet you.
On 8/29/2023 7:13 AM, Dave Stevenson wrote:
Hi Neil
On Mon, 28 Aug 2023 at 09:49, wrote:
Hi Jessica,
On 25/08/2023 20:37, Jessica Zhang wrote:
On 8/21/2023 3:01 AM, neil.armstr...@linaro.org wrote:
Hi Maxime,
On 21/08/2023 10:17, Maxime Ripard wrote:
Hi,
This reverts commit 3a31e8b89b7240d9a17ace8a1ed050bdcb560f9e.
We still need to call dcn20_adjust_freesync_v_startup() for older DCN3+
ASICs otherwise it can cause DP to HDMI 2.1 PCONs to fail to light up.
So, reintroduce the reverted code and limit it to ASICs older than
DCN31.
Cc: sta...@vger.ke
The files fbmem.c, fb_defio.c, fbsysfs.c, fbmon.c, modedb.c, and
fbcmap.c were moved to drivers/video/fbdev, and subsequently to
drivers/video/fbdev/core, in the commits listed below.
Reported by kalekale in #kernel (Libera IRC).
Fixes: f7018c213502 ("video: move fbdev to drivers/video/fbdev")
Fi
On 2023-08-29 12:03, Uma Shankar wrote:
Add the documentation for the new proposed Plane Color Pipeline.
Co-developed-by: Chaitanya Kumar Borah
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
.../gpu/rfc/plane_color_pipeline.rst | 394 ++
1 f
+CC Naseer and Chris, FYI
See https://patchwork.freedesktop.org/series/123024/ for whole series.
On 2023-08-29 12:03, Uma Shankar wrote:
Introduction
Modern hardwares have various color processing capabilities both
at pre-blending and post-blending phases in the color pipeline.
Th
On 8/29/2023 12:15 PM, Dmitry Baryshkov wrote:
On Tue, 29 Aug 2023 at 22:09, Abhinav Kumar wrote:
On 8/29/2023 11:51 AM, Dmitry Baryshkov wrote:
On Tue, 29 Aug 2023 at 20:22, Abhinav Kumar wrote:
On 8/29/2023 9:43 AM, Dmitry Baryshkov wrote:
On Tue, 29 Aug 2023 at 19:37, Abhinav Ku
On Tue, 29 Aug 2023 at 22:09, Abhinav Kumar wrote:
>
>
>
> On 8/29/2023 11:51 AM, Dmitry Baryshkov wrote:
> > On Tue, 29 Aug 2023 at 20:22, Abhinav Kumar
> > wrote:
> >>
> >>
> >>
> >> On 8/29/2023 9:43 AM, Dmitry Baryshkov wrote:
> >>> On Tue, 29 Aug 2023 at 19:37, Abhinav Kumar
> >>> wrote:
On 8/29/2023 11:51 AM, Dmitry Baryshkov wrote:
On Tue, 29 Aug 2023 at 20:22, Abhinav Kumar wrote:
On 8/29/2023 9:43 AM, Dmitry Baryshkov wrote:
On Tue, 29 Aug 2023 at 19:37, Abhinav Kumar wrote:
On 8/29/2023 2:26 AM, Dmitry Baryshkov wrote:
On Tue, 29 Aug 2023 at 12:22, wrote:
O
On 2023-08-29 11:03, Jani Nikula wrote:
On Tue, 29 Aug 2023, Jani Nikula wrote:
On Tue, 29 Aug 2023, Alex Deucher wrote:
On Tue, Aug 29, 2023 at 6:48 AM Jani Nikula wrote:
On Wed, 23 Aug 2023, Jani Nikula wrote:
On Tue, 22 Aug 2023, Alex Hung wrote:
On 2023-08-22 06:01, Jani Nikula
On Tue, 29 Aug 2023 at 20:22, Abhinav Kumar wrote:
>
>
>
> On 8/29/2023 9:43 AM, Dmitry Baryshkov wrote:
> > On Tue, 29 Aug 2023 at 19:37, Abhinav Kumar
> > wrote:
> >>
> >>
> >>
> >> On 8/29/2023 2:26 AM, Dmitry Baryshkov wrote:
> >>> On Tue, 29 Aug 2023 at 12:22, wrote:
>
> On 28/08
The function dp_link_parse_sink_count() is really just
drm_dp_read_sink_count(). It debug prints out the bit for content
protection (DP_SINK_CP_READY), but that is not useful beyond debug
because 'link->dp_link.sink_count' is overwritten to only contain the
sink_count in this same function. Just us
Use the common function drm_dp_read_sink_count() instead of open-coding
it. This shrinks the kernel text a tiny bit.
Cc: Vinod Polimera
Cc: Kuogee Hsieh
Signed-off-by: Stephen Boyd
---
drivers/gpu/drm/msm/dp/dp_panel.c | 19 +++
1 file changed, 7 insertions(+), 12 deletions(-)
This function is simply drm_dp_is_branch() so use that instead of
open-coding it.
Cc: Vinod Polimera
Cc: Kuogee Hsieh
Signed-off-by: Stephen Boyd
---
drivers/gpu/drm/msm/dp/dp_display.c | 9 +
1 file changed, 1 insertion(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_displa
These are open-coded versions of common functions. Replace them with the
common code to improve readability.
Cc: Vinod Polimera
Cc: Kuogee Hsieh
Signed-off-by: Stephen Boyd
---
drivers/gpu/drm/msm/dp/dp_panel.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu
The member 'aux_cfg_update_done' is always false. This is dead code that
never runs. Remove it.
Cc: Vinod Polimera
Cc: Kuogee Hsieh
Signed-off-by: Stephen Boyd
---
drivers/gpu/drm/msm/dp/dp_panel.c | 15 ---
1 file changed, 15 deletions(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_pa
We read the downstream port count and capability info but never use it
anywhere. Remove 'ds_port_cnt' and 'ds_cap_info' and any associated code
from this driver. Fold the check for 'dfp_present' into a call to
drm_dp_is_branch() at the one place it is used to get rid of any member
storage related t
This function duplicates the common function drm_dp_read_dpcd_caps().
The array of DPCD registers filled in is one size larger than the
function takes, but from what I can tell that extra byte was never used.
Resize the array and use the common function to reduce the code here.
Cc: Vinod Polimera
This driver open-codes a few of the DPCD register reads when it can be
simplified by using the helpers instead. This series reworks the MSM DP
driver to use the DPCD helpers and removes some dead code along the way.
There's the potential for even more code reduction around the test
registers, but I
Hello emersion
Since you told me the presentation in XDC 2020, I was thinking what we
need for the video codec hardware, I don't have much experience with
the situation that presentation addressed, sharing between GPU.
I think we must cover the case with and without IOMMU attached to the
d
On Tue, Aug 29, 2023 at 02:35:34PM -0400, James Zhu wrote:
>
> On 2023-08-29 14:33, Matthew Wilcox wrote:
> > On Tue, Aug 29, 2023 at 01:34:22PM -0400, James Zhu wrote:
> > > > > > @@ -1067,7 +1055,7 @@ static void drm_core_exit(void)
> > > > > > unregister_chrdev(DRM_MAJOR, "drm");
>
Hi Krzysztof,
thanks for your quick feedback.
You're right: This series mixes up too many things. I'll split up and
re-send.
(And fix my typos, indeed)
Best Regards,
Alex
Am 29.08.23 um 19:40 schrieb Krzysztof Kozlowski:
On 29/08/2023 19:16, Alex Bee wrote:
From: Finley Xiao
According
On 2023-08-29 14:33, Matthew Wilcox wrote:
On Tue, Aug 29, 2023 at 01:34:22PM -0400, James Zhu wrote:
@@ -1067,7 +1055,7 @@ static void drm_core_exit(void)
unregister_chrdev(DRM_MAJOR, "drm");
debugfs_remove(drm_debugfs_root);
drm_sysfs_destroy();
- idr_destroy(&d
On Tue, Aug 29, 2023 at 01:34:22PM -0400, James Zhu wrote:
> > > > @@ -1067,7 +1055,7 @@ static void drm_core_exit(void)
> > > > unregister_chrdev(DRM_MAJOR, "drm");
> > > > debugfs_remove(drm_debugfs_root);
> > > > drm_sysfs_destroy();
> > > > - idr_destroy(&drm_minor
On Tue, Aug 29, 2023 at 03:30:24PM +0200, Michael Walle wrote:
> Hi Nícolas,
>
> > > But the real reason I've enabled it was because I'll get an kernel
> > > oops otherwise. I thought it might be some quirk that you'll need
> > > both,
> > > because eDP will register even if theres no display - as
On 29/08/2023 14:57, Daniel Vetter wrote:
On Thu, Aug 24, 2023 at 01:42:30PM -0300, Helen Koike wrote:
Fix the following warning:
Documentation/gpu/automated_testing.rst:55: WARNING: Inline emphasis
start-string without end-string.
Reported-by: Stephen Rothwell
Signed-off-by: Helen Koike
On Thu, Aug 24, 2023 at 01:42:30PM -0300, Helen Koike wrote:
> Fix the following warning:
>
> Documentation/gpu/automated_testing.rst:55: WARNING: Inline emphasis
> start-string without end-string.
>
> Reported-by: Stephen Rothwell
> Signed-off-by: Helen Koike
Applied this, sorry for the dela
On Tue, Aug 29, 2023 at 03:19:41PM +0200, Michael Walle wrote:
> mtk_drm_find_possible_crtc_by_comp() assumed that the main path will
> always have the CRTC with id 0, the ext id 1 and the third id 2. This
> is only true if the paths are all available. But paths are optional (see
> also comment in
On Fri, 11 Aug 2023 17:08:20 +0100
Steven Price wrote:
> On 09/08/2023 17:53, Boris Brezillon wrote:
> > Add an entry for the Panthor driver to the MAINTAINERS file.
> >
> > v2:
> > - New commit
> >
> > Signed-off-by: Boris Brezillon
> > ---
> >
> > If anyone from Arm wants to volunteer to be
On Mon, 21 Aug 2023 12:31:29 +0100
Steven Price wrote:
> On 09/08/2023 17:53, Boris Brezillon wrote:
> > This is the last piece missing to expose the driver to the outside
> > world.
> >
> > This is basically a wrapper between the ioctls and the other logical
> > blocks.
> >
> > v2:
> > - Renam
On 29/08/2023 19:16, Alex Bee wrote:
> From: Finley Xiao
>
> According to the TRM there are no specific cpll_peri, gpll_div2_peri or
> gpll_div3_peri gates, but a single clk_peri_src gate and the peri mux
> directly connects to the plls respectivly the pll divider clocks.
> Fix this by creating a
On 8/11/23 04:31, Matthew Brost wrote:
DRM_SCHED_POLICY_SINGLE_ENTITY creates a 1 to 1 relationship between
scheduler and entity. No priorities or run queue used in this mode.
Intended for devices with firmware schedulers.
v2:
- Drop sched / rq union (Luben)
Signed-off-by: Matthew Brost
---
On Tue, Aug 29, 2023 at 12:30:01PM -0400, Rodrigo Vivi wrote:
Also the uapi should be reviewed and scrutinized before xe
is accepted upstream and we shouldn't cause regression.
Link:
https://lore.kernel.org/all/20230630100059.122881-1-thomas.hellst...@linux.intel.com
Signed-off-by: Rodrigo Vivi
On 2023-08-28 17:08, Michał Winiarski wrote:
On Fri, Aug 25, 2023 at 12:59:26PM -0400, James Zhu wrote:
On 2023-07-24 17:14, Michał Winiarski wrote:
IDR is deprecated, and since XArray manages its own state with internal
locking, it simplifies the locking on DRM side.
Additionally, don't use
On 29/08/2023 19:16, Alex Bee wrote:
> Add the reset controls for all 4 cpu cores.
This we see from the diff. Commit should say why.
Best regards,
Krzysztof
On 29/08/2023 19:16, Alex Bee wrote:
> RK312x SoCs have 8KB of SRAM.
> Add the respective device tree node for it.
>
> Signed-off-by: Alex Bee
> ---
This really does not depend on your MFD, GPU nor ASoC changes. Keep
independent work for different subsystems separate.
Best regards,
Krzysztof
On 29/08/2023 19:16, Alex Bee wrote:
> Currently there is only a SoC devicetree for RK3128 although RK312x
> SoC family consits of (at least) RK3126(C) and RK3128.
>
> This splits up the currently existing rk3128.dtsi in rk312x.dtsi which
> contains the common definitions for both SoCs and rk3128.
On 8/29/2023 9:43 AM, Dmitry Baryshkov wrote:
On Tue, 29 Aug 2023 at 19:37, Abhinav Kumar wrote:
On 8/29/2023 2:26 AM, Dmitry Baryshkov wrote:
On Tue, 29 Aug 2023 at 12:22, wrote:
On 28/08/2023 19:07, Abhinav Kumar wrote:
Hi Neil
Sorry I didnt respond earlier on this thread.
On 8/2
On 29/08/2023 19:16, Alex Bee wrote:
> Add Geniatech XPI-3128, a RK3128 based single board computer.
>
> Signed-off-by: Alex Bee
> ---
> Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +
> 1 file changed, 5 insertions(+)
Acked-by: Krzysztof Kozlowski
Best regards,
Krzysztof
On 29/08/2023 19:16, Alex Bee wrote:
> Add compatible for RK3128's S/PDIF.
>
Subject: ASoC: dt-bindings: rockchip,spdif:
> Signed-off-by: Alex Bee
> ---
Acked-by: Krzysztof Kozlowski
---
This is an automated instruction, just in case, because many review tags
are being ignored. If you know
On 29/08/2023 19:16, Alex Bee wrote:
> Rockchip RK312x SoC family has a Mali400 MP2.
> Add a compatible for it.
>
> Signed-off-by: Alex Bee
> ---
Acked-by: Krzysztof Kozlowski
Best regards,
Krzysztof
On 29/08/2023 19:16, Alex Bee wrote:
> Document Rockchip RK3128 SoC compatible for qos registers.
>
> Signed-off-by: Alex Bee
> ---
> Documentation/devicetree/bindings/mfd/syscon.yaml | 1 +
You should probably split patches per subsystem, if you want it to get
applied.
Acked-by: Krzysztof Kozl
Add the S/PDIF block for RK3128 SoC.
Signed-off-by: Alex Bee
---
arch/arm/boot/dts/rockchip/rk3128.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi
b/arch/arm/boot/dts/rockchip/rk3128.dtsi
index 2339232ae2d7..874c97297c63 100644
---
Both RK3126 and RK3128 have a 2-channel I2S IP block.
Add the respective node for it.
Signed-off-by: Alex Bee
---
arch/arm/boot/dts/rockchip/rk312x.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/rockchip/rk312x.dtsi
b/arch/arm/boot/dts/rockchip/rk31
Add the gmac node for RK3128 SoC.
Signed-off-by: Alex Bee
---
arch/arm/boot/dts/rockchip/rk3128.dtsi | 26 ++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi
b/arch/arm/boot/dts/rockchip/rk3128.dtsi
index 874c97297c63..54a2768153c0 1
RK312x SoCs have Mali400 MP2 GPU.
Add the respective device tree node and the correspondending opp-table.
The frequencies and voltages have been taken from downstream kernel and
work fine for both RK3126 and RK3128.
Signed-off-by: Alex Bee
---
arch/arm/boot/dts/rockchip/rk312x.dtsi | 44 +++
XPI-3128 is RK3128 based SBC form Geniatec in RPi form factor
Specs:
- Rockchip RK3128
- 1 GB DDR3 DRAM
- 8/16 GB eMMC
- TF card slot
- 100 MBit ethernet / RJ45
- optional Marvell 88W8897 (USB version)
- 3 x USB host (onboard GL852G hub connected to SoC ehci host)
- 1 x USB otg
- 1 x Type-C (solel
Without setting the parent for SCLK_USB480M the clock will use xin24m as
it's default parent. While this is generally not an issue for the usb
blocks to work, but the clock driver will "think" it runs at 24 MHz.
That becomes an issue for RK312x since SCLK_USB480M can be a parent for
other HW blocks
This will allow frequency-scaling for the cpu cores.
Operating frequencies and voltages have been taken from Rockchip's
downstream kernel.
Signed-off-by: Alex Bee
---
arch/arm/boot/dts/rockchip/rk312x.dtsi | 43 +++---
1 file changed, 39 insertions(+), 4 deletions(-)
diff --
Add the power controller node and the correspondending qos nodes for
RK312x.
Signed-off-by: Alex Bee
---
arch/arm/boot/dts/rockchip/rk312x.dtsi | 82 ++
1 file changed, 82 insertions(+)
diff --git a/arch/arm/boot/dts/rockchip/rk312x.dtsi
b/arch/arm/boot/dts/rockchip/rk3
Currently the Rockchip timer source clocks are set to xin24 for no obvious
reason and the "real" timer clocks (SCLK_TIMER*) will get disabled during
boot process as the have no user. That will make the SoC stuck as no timer
source exists.
Fixes: a0201bff6259 ("ARM: dts: rockchip: add rk3128 soc dt
Currently there is only a SoC devicetree for RK3128 although RK312x
SoC family consits of (at least) RK3126(C) and RK3128.
This splits up the currently existing rk3128.dtsi in rk312x.dtsi which
contains the common definitions for both SoCs and rk3128.dtsi, rk3126.dtsi
respectivly.
The differentia
Add the AHB clocks for both the ehci and ohci controller.
Signed-off-by: Alex Bee
---
arch/arm/boot/dts/rockchip/rk312x.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/rockchip/rk312x.dtsi
b/arch/arm/boot/dts/rockchip/rk312x.dtsi
index 019aa92c0cfa..b13957d55500 100
For bringup of the non-boot cpu cores the enable-method for RK3036 can be
re-used.
This adds a (small) chunk of SRAM for execution of the SMP trampoline code
and the respective enable-method property to the cpus.
Signed-off-by: Alex Bee
---
arch/arm/boot/dts/rockchip/rk312x.dtsi | 6 ++
1
RK312x SoCs have 8KB of SRAM.
Add the respective device tree node for it.
Signed-off-by: Alex Bee
---
arch/arm/boot/dts/rockchip/rk312x.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/rockchip/rk312x.dtsi
b/arch/arm/boot/dts/rockchip/rk312x.dtsi
index 4d3422ab
RK3128 has a second I2S block with 8 playback channels.
It's internally hard-wired to the HDMI-TX, thus only usable with it.
Signed-off-by: Alex Bee
---
arch/arm/boot/dts/rockchip/rk3128.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/rockchip/rk3128.dt
Add the reset controls for all 4 cpu cores.
Signed-off-by: Alex Bee
---
arch/arm/boot/dts/rockchip/rk312x.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/rockchip/rk312x.dtsi
b/arch/arm/boot/dts/rockchip/rk312x.dtsi
index 7aba97b2c990..b195ac525c37 100644
--- a/ar
Rockchip RK312x SoC family has a Mali400 MP2.
Add a compatible for it.
Signed-off-by: Alex Bee
---
Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml
b/Documentation/devicetree
The driver currently won't probe correctly if those values are missing.
They have been taken from dowstream kernel and match those of other
Rockchip SoCs.
Signed-off-by: Alex Bee
---
arch/arm/boot/dts/rockchip/rk312x.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/r
While RK3126's CPU cores can operate at the same frequencies as RK3128, but
it needs higher voltages.
The values have been taken from vendor's downstream kernel.
Signed-off-by: Alex Bee
---
arch/arm/boot/dts/rockchip/rk3126.dtsi | 27 ++
1 file changed, 27 insertions(+)
The Rockchip timer linux driver can handle a maximum of 2 timers and will
get confused if more of them exist.
RK3128 only needs timer0, timer1 and timer5. The latter is the source
for the arm-timer and its clock is prevented from being disabled in the
clock driver so it can get disabled in the devi
The pincontrol for sd card detection is currently missing.
Add it.
Signed-off-by: Alex Bee
---
arch/arm/boot/dts/rockchip/rk312x.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/rockchip/rk312x.dtsi
b/arch/arm/boot/dts/rockchip/rk312x.dtsi
index 19bd6448d122..53882
SCLK_SDMMC is the parent for SCLK_SDMMC_DRV and SCLK_SDMMC_SAMPLE, but
used with the (more) correct name sclk_sdmmc. SD card tuning does currently
fail as the parent can't be found under that name
There is no need to suffix the name with '0' since RK312x SoCs do have a
single sdmmc controller - so
The Cortex-A7 timer has 4 interrupts.
Add the mssing one.
Fixes: a0201bff6259 ("ARM: dts: rockchip: add rk3128 soc dtsi")
Signed-off-by: Alex Bee
---
arch/arm/boot/dts/rockchip/rk3128.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rockchip/rk3128.dts
Like most other Rockchip ARM SoCs, the PL330 needs the
arm,pl330-periph-burst quirk in order to work as expected.
Add it.
Fixes: a0201bff6259 ("ARM: dts: rockchip: add rk3128 soc dtsi")
Signed-off-by: Alex Bee
---
arch/arm/boot/dts/rockchip/rk3128.dtsi | 1 +
1 file changed, 1 insertion(+)
diff
Commit 51a9b2c03dd3 ("phy: rockchip-inno-usb2: Handle ID IRQ") added ID
detection interrupt registers. However the current implementation assumes
that falling and rising edge interrupt are always enabled in registers
spaning over subsequent bits.
That is not the case for RK312x's version of the phy
From: Finley Xiao
HCLK_OTG gate is located in CRU_CLKGATE5_CON, not in CRU_CLKGATE3_CON.
CRU_CLKGATE3_CON bit 13 is already (correctly) defined for ACLK_GPU.
Fixes: f6022e88faca ("clk: rockchip: add clock controller for rk3128")
Signed-off-by: Finley Xiao
[added commit message]
Signed-off-by: A
Document Rockchip RK3128 SoC compatible for qos registers.
Signed-off-by: Alex Bee
---
Documentation/devicetree/bindings/mfd/syscon.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml
b/Documentation/devicetree/bindings/mfd/syscon.yaml
inde
The register address for i2c0 is missing a 0x to mark it as hex.
Fixes: a0201bff6259 ("ARM: dts: rockchip: add rk3128 soc dtsi")
Signed-off-by: Alex Bee
---
arch/arm/boot/dts/rockchip/rk3128.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rockchip/rk312
From: Finley Xiao
According to the TRM there are no specific cpll_peri, gpll_div2_peri or
gpll_div3_peri gates, but a single clk_peri_src gate and the peri mux
directly connects to the plls respectivly the pll divider clocks.
Fix this by creating a single gated composite.
Also rename all occurre
Add registers to support the 2-port usb2 phy found in RK312x SoC familiy.
Signed-off-by: Alex Bee
---
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 48 +++
1 file changed, 48 insertions(+)
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
b/drivers/phy/rockchip/phy-r
Add Geniatech XPI-3128, a RK3128 based single board computer.
Signed-off-by: Alex Bee
---
Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml
b/Documentation/devicetree/bindings/arm/rock
Add compatible for RK3128's S/PDIF.
Signed-off-by: Alex Bee
---
Documentation/devicetree/bindings/sound/rockchip-spdif.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/sound/rockchip-spdif.yaml
b/Documentation/devicetree/bindings/sound/rockchip-spdif.ya
Hi list,
this series fixes some issues I found when testing my "new" RK3128 board
with the mainline kernel and adds some core functionality like SMP bringup,
usb and networking.
The propably most distinctive change is the split up of the DTs for the
different SoCs of this platform: RK3126 and RK3
On 8/29/23 18:45, Nick Desaulniers wrote:
Helge,
A recent change in clang made it better about spotting snprintf that
will result in truncation. Nathan reported the following instances:
drivers/video/fbdev/neofb.c:1959:3: warning: 'snprintf' will always be
truncated; specified size is 16, but f
On Tue, 29 Aug 2023, Jani Nikula wrote:
> On Tue, 29 Aug 2023, Alex Deucher wrote:
>> On Tue, Aug 29, 2023 at 6:48 AM Jani Nikula wrote:
>>>
>>> On Wed, 23 Aug 2023, Jani Nikula wrote:
>>> > On Tue, 22 Aug 2023, Alex Hung wrote:
>>> >> On 2023-08-22 06:01, Jani Nikula wrote:
>>> >>> Over the p
Helge,
A recent change in clang made it better about spotting snprintf that
will result in truncation. Nathan reported the following instances:
drivers/video/fbdev/neofb.c:1959:3: warning: 'snprintf' will always be
truncated; specified size is 16, but format string expands to at least
17 [-Wforti
On Tue, 29 Aug 2023 at 19:37, Abhinav Kumar wrote:
>
>
>
> On 8/29/2023 2:26 AM, Dmitry Baryshkov wrote:
> > On Tue, 29 Aug 2023 at 12:22, wrote:
> >>
> >> On 28/08/2023 19:07, Abhinav Kumar wrote:
> >>> Hi Neil
> >>>
> >>> Sorry I didnt respond earlier on this thread.
> >>>
> >>> On 8/28/2023 1:
On 29/08/2023 16:18, Flavio Suligoi wrote:
> Hi Krzysztof,
>
> Thanks for your quick replay and corrections!
> Just some questions about some of your remarks:
>
>>> @@ -0,0 +1,202 @@
>>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2
>>> +---
>>
>>> +
>>> + reg:
>>> +maxItem
On 8/29/2023 2:26 AM, Dmitry Baryshkov wrote:
On Tue, 29 Aug 2023 at 12:22, wrote:
On 28/08/2023 19:07, Abhinav Kumar wrote:
Hi Neil
Sorry I didnt respond earlier on this thread.
On 8/28/2023 1:49 AM, neil.armstr...@linaro.org wrote:
Hi Jessica,
On 25/08/2023 20:37, Jessica Zhang wrote
On Fri, 18 Aug 2023 16:38:57 +0100
Steven Price wrote:
> > +/**
> > + * sched_queue_work() - Queue a scheduler work.
> > + * @sched: Scheduler object.
> > + * @wname: Work name.
> > + *
> > + * Conditionally queues a scheduler work if no reset is
> > pending/in-progress.
> > + */
> > +#define sc
Nouveau has landed the GPU VA helpers, support and documentation
already and Xe is already using the upstream GPU VA.
Signed-off-by: Rodrigo Vivi
---
Documentation/gpu/rfc/xe.rst | 36 ++--
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/Documentat
Also the uapi should be reviewed and scrutinized before xe
is accepted upstream and we shouldn't cause regression.
Link:
https://lore.kernel.org/all/20230630100059.122881-1-thomas.hellst...@linux.intel.com
Signed-off-by: Rodrigo Vivi
---
Documentation/gpu/rfc/xe.rst | 6 --
1 file changed,
The consensus is for individual drivers VM_BIND uapis with
the GPUVA helpers that are already implemented and merged
upstream.
The merged GPUVA documentation also establish some overall
rules for the locking to be followed by the drivers.
Signed-off-by: Rodrigo Vivi
---
Documentation/gpu/rfc/xe
Xe is already using devcoredump infrastructure as the primary
error state and all the changes needed for user space error
replay and other useful logs are getting added into xe_devcoredump.
Link:
https://gitlab.freedesktop.org/drm/xe/kernel/-/blob/drm-xe-next/drivers/gpu/drm/xe/xe_devcoredump.c
S
On Tue, 29 Aug 2023, Alex Deucher wrote:
> On Tue, Aug 29, 2023 at 6:48 AM Jani Nikula wrote:
>>
>> On Wed, 23 Aug 2023, Jani Nikula wrote:
>> > On Tue, 22 Aug 2023, Alex Hung wrote:
>> >> On 2023-08-22 06:01, Jani Nikula wrote:
>> >>> Over the past years I've been trying to unify the override
On Tue, Aug 29, 2023 at 12:15:46PM +0200, Flavio Suligoi wrote:
> The Monolithic Power (MPS) MP3309C is a WLED step-up converter, featuring a
> programmable switching frequency to optimize efficiency.
> The brightness can be controlled either by I2C commands (called "analog"
> mode) or by a PWM inp
On Fri, 18 Aug 2023 15:39:03 +0100
Steven Price wrote:
> I'm not sure whether we should really be describing this structure in
> the kernel. Beyond the size the kernel has no reason to be looking at
> the internals and the spec does have a warning that the layout may change.
Yeah, I guess I just
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