[PATCH 06/31] clk: rockchip: rk3128: Fix hclk_otg gate

[Alex Bee]

From: Finley Xiao <finley.x...@rock-chips.com>

HCLK_OTG gate is located in CRU_CLKGATE5_CON, not in CRU_CLKGATE3_CON.
CRU_CLKGATE3_CON bit 13 is already (correctly) defined for ACLK_GPU.

Fixes: f6022e88faca ("clk: rockchip: add clock controller for rk3128")
Signed-off-by: Finley Xiao <finley.x...@rock-chips.com>
[added commit message]
Signed-off-by: Alex Bee <knaerz...@gmail.com>
---
 drivers/clk/rockchip/clk-rk3128.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-rk3128.c 
b/drivers/clk/rockchip/clk-rk3128.c
index fcacfe758829..17bacf6dd6e7 100644
--- a/drivers/clk/rockchip/clk-rk3128.c
+++ b/drivers/clk/rockchip/clk-rk3128.c
@@ -484,7 +484,7 @@ static struct rockchip_clk_branch common_clk_branches[] 
__initdata = {
        GATE(HCLK_I2S_2CH, "hclk_i2s_2ch", "hclk_peri", 0, 
RK2928_CLKGATE_CON(7), 2, GFLAGS),
        GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, 
RK2928_CLKGATE_CON(9), 13, GFLAGS),
        GATE(HCLK_HOST2, "hclk_host2", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 
3, GFLAGS),
-       GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 0, RK2928_CLKGATE_CON(3), 13, 
GFLAGS),
+       GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 13, 
GFLAGS),
        GATE(0, "hclk_peri_ahb", "hclk_peri", CLK_IGNORE_UNUSED, 
RK2928_CLKGATE_CON(9), 14, GFLAGS),
        GATE(HCLK_SPDIF, "hclk_spdif", "hclk_peri", 0, RK2928_CLKGATE_CON(10), 
9, GFLAGS),
        GATE(HCLK_TSP, "hclk_tsp", "hclk_peri", 0, RK2928_CLKGATE_CON(10), 12, 
GFLAGS),
-- 
2.42.0