Add registers to support the 2-port usb2 phy found in RK312x SoC familiy.

Signed-off-by: Alex Bee <knaerz...@gmail.com>
---
 drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 48 +++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c 
b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
index a4a1716e67bd..9ea08be533cc 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -1374,6 +1374,53 @@ static int rockchip_usb2phy_probe(struct platform_device 
*pdev)
        return ret;
 }
 
+static const struct rockchip_usb2phy_cfg rk3128_phy_cfgs[] = {
+       {
+               .reg = 0x17c,
+               .num_ports      = 2,
+               .clkout_ctl     = { 0x0190, 15, 15, 1, 0 },
+               .port_cfgs      = {
+                       [USB2PHY_PORT_OTG] = {
+                               .phy_sus        = { 0x017c, 8, 0, 0, 0x1d1 },
+                               .bvalid_det_en  = { 0x017c, 14, 14, 0, 1 },
+                               .bvalid_det_st  = { 0x017c, 15, 15, 0, 1 },
+                               .bvalid_det_clr = { 0x017c, 15, 15, 0, 1 },
+                               .idfall_det_en  = { 0x01a0, 2, 2, 0, 1 },
+                               .idfall_det_st  = { 0x01a0, 3, 3, 0, 1 },
+                               .idfall_det_clr = { 0x01a0, 3, 3, 0, 1 },
+                               .idrise_det_en  = { 0x01a0, 0, 0, 0, 1 },
+                               .idrise_det_st  = { 0x01a0, 1, 1, 0, 1 },
+                               .idrise_det_clr = { 0x01a0, 1, 1, 0, 1 },
+                               .ls_det_en      = { 0x017c, 12, 12, 0, 1 },
+                               .ls_det_st      = { 0x017c, 13, 13, 0, 1 },
+                               .ls_det_clr     = { 0x017c, 13, 13, 0, 1 },
+                               .utmi_bvalid    = { 0x014c, 5, 5, 0, 1 },
+                               .utmi_id        = { 0x014c, 8, 8, 0, 1 },
+                               .utmi_ls        = { 0x014c, 7, 6, 0, 1 },
+                       },
+                       [USB2PHY_PORT_HOST] = {
+                               .phy_sus        = { 0x0194, 8, 0, 0, 0x1d1 },
+                               .ls_det_en      = { 0x0194, 14, 14, 0, 1 },
+                               .ls_det_st      = { 0x0194, 15, 15, 0, 1 },
+                               .ls_det_clr     = { 0x0194, 15, 15, 0, 1 }
+                       }
+               },
+               .chg_det = {
+                       .opmode         = { 0x017c, 3, 0, 5, 1 },
+                       .cp_det         = { 0x02c0, 6, 6, 0, 1 },
+                       .dcp_det        = { 0x02c0, 5, 5, 0, 1 },
+                       .dp_det         = { 0x02c0, 7, 7, 0, 1 },
+                       .idm_sink_en    = { 0x0184, 8, 8, 0, 1 },
+                       .idp_sink_en    = { 0x0184, 7, 7, 0, 1 },
+                       .idp_src_en     = { 0x0184, 9, 9, 0, 1 },
+                       .rdm_pdwn_en    = { 0x0184, 10, 10, 0, 1 },
+                       .vdm_src_en     = { 0x0184, 12, 12, 0, 1 },
+                       .vdp_src_en     = { 0x0184, 11, 11, 0, 1 },
+               },
+       },
+       { /* sentinel */ }
+};
+
 static const struct rockchip_usb2phy_cfg rk3228_phy_cfgs[] = {
        {
                .reg = 0x760,
@@ -1749,6 +1796,7 @@ static const struct rockchip_usb2phy_cfg 
rv1108_phy_cfgs[] = {
 
 static const struct of_device_id rockchip_usb2phy_dt_match[] = {
        { .compatible = "rockchip,px30-usb2phy", .data = &rk3328_phy_cfgs },
+       { .compatible = "rockchip,rk3128-usb2phy", .data = &rk3128_phy_cfgs },
        { .compatible = "rockchip,rk3228-usb2phy", .data = &rk3228_phy_cfgs },
        { .compatible = "rockchip,rk3308-usb2phy", .data = &rk3308_phy_cfgs },
        { .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs },
-- 
2.42.0

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