Hi Tomi,
Thank you for the patch.
On Friday 19 February 2016 11:47:40 Tomi Valkeinen wrote:
> Errata i878 says that MPU should not be used to access RAM and DMM at
> the same time. As it's not possible to prevent MPU accessing RAM, we
> need to access DMM via a proxy.
>
> This patch changes DMM
ent
projects in OpenCL, OpenGL or Mesa.
Awaiting a positive response.
Regards,
Abheek Ghosh
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Hi Zach,
On 2 February 2016 at 23:37, Zach Reizner wrote:
> The prime fd to handle ioctl was not used with rockchip before. Support
> was added in order to support potential uses (e.g. zero-copy video
> decode, camera).
>
Similar patch came around a few months ago and got this reply [1]. If
the s
On Tue, Feb 23, 2016 at 3:56 PM, Rob Clark wrote:
> On Tue, Feb 23, 2016 at 6:29 PM, Emil Velikov
> wrote:
>> Hi Zach,
>>
>> On 2 February 2016 at 23:37, Zach Reizner wrote:
>>> The prime fd to handle ioctl was not used with rockchip before. Support
>>> was added in order to support potential u
Hi Tomi,
Thank you for the patch.
On Friday 19 February 2016 11:47:39 Tomi Valkeinen wrote:
> This patch adds wrapper functions for readl() and writel(), dmm_read()
> and dmm_write(), so that we can implement workaround for errata i878.
>
> Signed-off-by: Tomi Valkeinen
Reviewed-by: Laurent Pi
Hi Tomi,
Thank you for the patch.
On Friday 19 February 2016 11:47:38 Tomi Valkeinen wrote:
> A DMM timeout "timed out waiting for done" has been observed on DRA7
> devices. The timeout happens rarely, and only when the system is under
> heavy load.
>
> Debugging showed that the timeout can be m
Hello Abheek,
On 23 February 2016 at 18:08, Abheek Ghosh wrote:
> Hi,
> I am Abheek Ghosh, sophomore from Indian Institute of Technology, Guwahati.
> I read the Summer of Code and DRM pages, as well as Mehul's discussion but
> didn't get much help. I have strong C/C++ skills and familiar with Ope
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Picked it up.
Thanks,
Inki Dae
2016ë
02ì 12ì¼ 22:31ì Chanho Park ì´(ê°) ì´ ê¸:
> This patch adds a exynos5420 driver data to support mic_bypass
> option to bypass the mic from display out path.
> The mic(Mobile image compressor) compresses RGB data from fimd
> and send the compressed d
On Tue, Feb 23, 2016 at 6:29 PM, Emil Velikov
wrote:
> Hi Zach,
>
> On 2 February 2016 at 23:37, Zach Reizner wrote:
>> The prime fd to handle ioctl was not used with rockchip before. Support
>> was added in order to support potential uses (e.g. zero-copy video
>> decode, camera).
>>
> Similar p
From: Ville Syrjälä
DP dual mode type 1 DVI adaptors aren't required to implement any
registers, so it's a bit hard to detect them. The best way would
be to check the state of the CONFIG1 pin, but we have no way to
do that. So as a last resort, check the VBT to see if the HDMI
port is in fact a
From: Ville Syrjälä
To save a bit of power, let's try to turn off the TMDS output buffers
in DP++ adaptors when we're not driving the port.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_hdmi.c | 27 +--
2 files
From: Ville Syrjälä
Try to detect the max TMDS clock limit for the DP++ adaptor (if any)
and take it into account when checking the port clock.
Note that as with the sink (HDMI vs. DVI) TMDS clock limit we'll ignore
the adaptor TMDS clock limit in the modeset path, in case users are
already "o
From: Ville Syrjälä
Add a helper which aids in he identification of DP dual mode (aka. DP++)
adaptors. There are several types of adaptors specified:
type 1 DVI, type 1 HDMI, type 2 DVI, type 2 HDMI
Type 1 adaptors have a max TMDS clock limit of 165MHz, type 2 adaptors
may go as high as 300MHz
From: Ville Syrjälä
While looking at a regression caused by i915's use of 12bpc HDMI mode,
I ended up reading the DP dual mode spec, and that lead to this patch
series.
I intentionally made the basics of the helper look somewhat like
Thierry's HDMI 2.0 SCDC stuff [1], except with a few less bu
On Tue, Feb 23, 2016 at 11:00:21AM +0800, Xinliang Liu wrote:
> Add ADE display controller binding doc.
> Add DesignWare DSI Host Controller v1.20a binding doc.
>
> v5:
> - Remove endpoint unit address of dsi output port.
> - Add "hisilicon,noc-syscon" property for ADE NOC QoS syscon.
> - Add "res
On 02/23/16 17:32, Tomi Valkeinen wrote:
> On 23/02/16 17:26, Jyri Sarha wrote:
>
>>> You didn't comment on why this is not an error? Why should the driver
>>> continue even if crtc->port is missing?
>>>
>>
>> At least for the time being if the drm_of_find_possible_crtcs() fails
>> the tda998x driv
but
gives a scary WARN.
Tomi
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r that case as well, except that as
far as I know there is no mechanism to have the display engines choose
per access, whether or not to use the SMMU.
Thierry
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ntoo, hence
you guys got a patch. i don't know why you're upset about this.
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On 02/23/16 17:19, Tomi Valkeinen wrote:
>
>
> On 23/02/16 17:03, Jyri Sarha wrote:
>> Initialize port device node pointer in the tilcdc crtc. Fixes "Falling
>> back to first CRTC" warning from tda998x driver.
>>
>> The tda998x encoder driver calls drm_of_find_possible_crtcs() to
>> initialize poss
ot;port");
> + }
> + WARN_ON(!crtc->port);
> + }
You didn't comment on why this is not an error? Why should the driver
continue even if crtc->port is missing?
Tomi
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As it turns out, resuming DP MST is racey since we don't make sure MST
is ready before we start modesetting, it just usually happens to be
ready in time. This isn't the case on all systems, particularly a
ThinkPad T560 with displays connected through the dock. On these
systems, resuming the laptop
On Mon, Feb 22, 2016 at 02:32:32PM +0200, Oleksandr Natalenko wrote:
> Ville, Daniel,
>
> any additional info I could provide? I have to return dual-link DVI
> cable back, so let me know if I could reveal more details if necessary.
Unfortunately I'm out of ideas for now. Daniel is on vacation.
A
able
URL:
<https://lists.freedesktop.org/archives/dri-devel/attachments/20160223/f427c76b/attachment.sig>
Use devm_kzalloc() and devm_kcalloc() for private data allocation at
driver load time.
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 4 +---
drivers/gpu/drm/tilcdc/tilcdc_drv.c| 19 +++
drivers/gpu/drm/tilcdc/tilcdc_panel.c | 20 ++--
Initialize port device node pointer in the tilcdc crtc. Fixes "Falling
back to first CRTC" warning from tda998x driver.
The tda998x encoder driver calls drm_of_find_possible_crtcs() to
initialize possible_crtcs of struct drm_encoder. The crtc->port needs
to be initialized for drm_of_find_possible_
Disable the sync lost interrupt if it fires on every frame for 50
consecutive frames in a row. This is relatively sure sign of the sync
lost interrupt being stuck and firing on every frame even if the
display otherwise appears to work OK.
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tilcdc/tilc
Add ratelimited prints on sync lost and FIFO underrun interrupts.
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 8
drivers/gpu/drm/tilcdc/tilcdc_drv.c | 4 ++--
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
Removes the duplicate LCDC_INT_ENABLE_SET_REG-entry in registers array.
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tilcdc/tilcdc_drv.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.c
b/drivers/gpu/drm/tilcdc/tilcdc_drv.c
index 964e192
Fix interrupt enable/disable code for version 2 tilcdc. In version 2
tilcdc there is a separate register for disabling interrupts. Writing
0 to enable registers bits does not have any effect. The interrupt
clear register works the same way, writing 1 to specific bit disables
the interrupt and writi
From: Tomi Valkeinen
Do not update the next frame buffer close to vertical blank. This is
to avoid situation when the frame changes between writing of
LCDC_DMA_FB_BASE_ADDR_0_REG and LCDC_DMA_FB_CEILING_ADDR_0_REG.
Signed-off-by: Tomi Valkeinen
[Added description to the patch]
Signed-off-by: Jy
From: Tomi Valkeinen
Get rid of complex ping-pong mechanism and replace it with simpler
single buffer flipping code.
The LCDC HW appears to be designed mainly static framebuffers in
mind. There are two modes of operation, either static single buffer,
or ping pong double buffering with two static
From: Tomi Valkeinen
Cleanup irq handling. Clear the irq status unconditionally and
restructure the status bit conditions.
Signed-off-by: Tomi Valkeinen
[Added description to the patch]
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 9 +
1 file changed, 5 inserti
From: Tomi Valkeinen
Remove broken error handling. The condition for handling the
LCDC_SYNC_LOST and LCDC_FIFO_UNDERFLOW could never be satisfied as the
LCDC_SYNC_LOST interrupt is not enabled. Also the requirement to have
both LCDC_SYNC_LOST and LCDC_FIFO_UNDERFLOW fired at once before
handling
From: Tomi Valkeinen
Split reset to a separate function and use usleep_range(250, 1000)
instead of msleep(1) to to keep the reset bit on long enough.
Signed-off-by: Tomi Valkeinen
[Added description to the patch, changed mdelay(500) to usleep_range(250, 1000)]
Signed-off-by: Jyri Sarha
---
dr
From: Tomi Valkeinen
Disable crtc on unload. Call tilcdc_crtc_dpms() with DRM_MODE_DPMS_OFF
in the beginning of unload function.
Signed-off-by: Tomi Valkeinen
[Added description to the patch]
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tilcdc/tilcdc_drv.c | 2 ++
1 file changed, 2 insertion
From: Tomi Valkeinen
Cleanup runtime PM handling. Before the patch the usage of pm_runtime
calls was inconsistent and hard to follow. After the update the
pm_runtime calls are removed from set_scanout() and called around
major operations that access the HW. After the patch the DPMS code does
not
Allocate suspend/resume register storage based on the actual number
registers the driver is aware of. The static allocation for register
storage had fallen behind badly.
Reported-by: Michael Bode
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tilcdc/tilcdc_drv.c | 21 -
drive
From: Grygorii Strashko
Fix build error when !CONFIG_CPU_FREQ
drivers/gpu/drm/tilcdc/tilcdc_drv.c: In function 'tilcdc_load':
drivers/gpu/drm/tilcdc/tilcdc_drv.c:327:1: error: label 'fail_put_clk' defined
but not used [-Werror=unused-label]
fail_put_clk:
^
Signed-off-by: Grygorii Strashko
Si
There is nothing special about tilcdc HW when the video memory is
concerned. Just using the standard drm helpers for implementation is
enough.
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tilcdc/tilcdc_drv.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drive
From: Darren Etheridge
The LCD controller must be deactivated and all DMA transactions stopped
when the suspend power state is entered otherwise the PRCM causes the L3
bus to get stuck in transition state.
This commit forces the lcdc to be shut down and waits for all pending DMA
transactions to
From: Darren Etheridge
The frame_done interrupt was only being enabled when the vsync
interrupts were being enabled by DRM. However the frame_done is
used to determine if the LCD controller has successfully completed
the raster_enable, raster_disable commands and the vsync interrupts
are not alw
From: Darren Etheridge
On BeagleBone Black if no HDMI monitor is connected and suspend
is requested a kernel panic will result:
root at am335x-evm:~# echo mem > /sys/power/state
[ 65.548710] PM: Syncing filesystems ... done.
[ 65.631311] Freezing user space processes ... (elapsed 0.006 seconds)
From: Dave Gerlach
Update tilcdc driver to set the state of the pins to:
- "default on resume
- "sleep" on suspend
By optionally putting the pins into sleep state in the suspend callback
we can accomplish two things.
- minimize current leakage from pins and thus save power,
- prevent the IP from
From: Tomi Valkeinen
LCDC hardware does not support fb pitch that is different (i.e. larger)
than the screen size. The driver currently does no checks for this, and
the results of too big pitch are are flickering and lower fps.
This issue easily happens when using libdrm's modetest tool with non
From: Darren Etheridge
Updating the tilcdc DRM driver code to calculate the LCD controller
pixel clock more accurately. Based on a suggested implementation by
Tomi Valkeinen.
The current code does not work correctly and produces wrong results
with many requested clock rates. It also oddly uses t
One more round to fix the last issues commented by Tomi Valkeinen.
Changes since v2:
- 09/22 "drm/tilcdc: Allocate register storage based on the actual number
registers"
- Fixed typo in the description
- 21/22 "drm/tilcdc: Initialize crtc->port"
- Changed the code to hand
;
device->dev.parent = host1x->dev;
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Hi Jitao,
[auto build test ERROR on drm/drm-next]
[also build test ERROR on v4.5-rc5 next-20160223]
[if your patch is applied to the wrong git tree, please drop us a note to help
improving the system]
url:
https://github.com/0day-ci/linux/commits/Jitao-Shi/Documentation-bridge-Add
On 02/23/2016 02:48 PM, Tomi Valkeinen wrote:
>
> On 22/02/16 22:10, Rob Herring wrote:
>
>>> If we want all DSI host controllers to use a common binding to describe
>>> lanes, we'd need to go with the most flexible one, and the driver
>>> restricts it to the subsets that we support.
>
> True, bu
; > > .hdisplay = 2560,
> > > > @@ -1256,6 +1279,9 @@ static const struct of_device_id
> > platform_of_match[]
> > > > = {
> > > > .compatible = "lg,lb070wv8",
> > > > .data = &lg_lb070wv8,
> > > > }, {
> > > > + .compatible = "lg,lp120up1",
> > > > + .data = &lg_lp120up1,
> > > > + }, {
> > > > .compatible = "lg,lp129qe",
> > > > .data = &lg_lp129qe,
> > > > }, {
> > > > --
> > > > 1.7.9.5
> > > >
> > > >
> > > > ___
> > > > linux-arm-kernel mailing list
> > > > linux-arm-kernel at lists.infradead.org
> > > > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> > > >
> >
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assignee for the bug.
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This patch adds drm_bridge driver for parade DSI to eDP bridge chip.
Signed-off-by: Jitao Shi
---
Changes since v10:
- Tuning PS8640 reset sleep pins squence
The following patches are needed to support dsi host through none dsi bus:
https://patchwork.kernel.org/patch/8289181/ ("drm/dsi: check
Add documentation for DT properties supported by
ps8640 DSI-eDP converter.
Signed-off-by: Jitao Shi
Acked-by: Rob Herring
Reviewed-by: Philipp Zabel
---
Chnages since v10:
- set sleep reset pin as GPIO_ACTIVE_LOW
---
.../devicetree/bindings/display/bridge/ps8640.txt | 43 ++
Any comments on this?
Also added Manfred, Tomi and Boris to CC which previously attended in
similar discussions.
Previous discussions:
http://thread.gmane.org/gmane.linux.kernel.api/12830
http://thread.gmane.org/gmane.comp.video.dri.devel/96240/
I think one of the main observation so far was tha
The default DMA mask covers a 32 bits address range, but tegradrm can
address more than that. Set the DMA mask to the actual addressable range
to avoid the use of unneeded bounce buffers.
Signed-off-by: Alexandre Courbot
---
Thierry, I am not absolutely sure whether the size is correct and applie
The current settings leaves the DRM device's dma_ops field NULL, which
makes it use the dummy DMA ops on arm64 and return an error whenever we
try to import a buffer. Call of_dma_configure() with a NULL node (since
the device is not spawn from the device tree) so that
arch_setup_dma_ops() is called
https://bugzilla.kernel.org/show_bug.cgi?id=112921
Alex Deucher changed:
What|Removed |Added
CC||alexdeucher at gmail.com
--- Comment #4 f
*/
Tomi
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On 02/23/2016 12:57 AM, Rob Herring wrote:
> On Mon, Feb 22, 2016 at 5:07 AM, Archit Taneja
> wrote:
>>
>>
>> On 02/22/2016 08:24 AM, Rob Herring wrote:
>>>
>>> On Mon, Feb 15, 2016 at 12:23:26PM +0530, Archit Taneja wrote:
Add HDMI PHY bindings. Update the example to use HDMI PHY.
>>
On 23 February 2016 at 14:51, Oded Gabbay wrote:
> On Tue, Feb 23, 2016 at 5:10 AM, Xinliang Liu
> wrote:
>> On 15 February 2016 at 19:04, Oded Gabbay wrote:
>>> On Sun, Feb 14, 2016 at 2:58 PM, Daniel Vetter wrote:
On Sun, Feb 14, 2016 at 11:16:52AM +0200, Oded Gabbay wrote:
> Follow
On 23/02/16 00:52, Matt Roper wrote:
> On Mon, Feb 22, 2016 at 02:18:10PM +, Lionel Landwerlin wrote:
>> Patch based on a previous series by Shashank Sharma.
>>
>> v2: Do not read GAMMA_MODE register to figure what mode we're in
>>
>> v3: Program PREC_PAL_GC_MAX to clamp pixel values > 1.0
>>
>
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Patch based on a previous series by Shashank Sharma.
v2: Update contributors
v3: Refactor degamma/gamma LUTs load into a single function
v4: Remove unused variable
Signed-off-by: Shashank Sharma
Signed-off-by: Lionel Landwerlin
Signed-off-by: Kumar, Kiran S
Signed-off-by: Kausal Malladi
---
Patch based on a previous series by Shashank Sharma.
v2: Do not read GAMMA_MODE register to figure what mode we're in
v3: Program PREC_PAL_GC_MAX to clamp pixel values > 1.0
Add documentation on how the Broadcast RGB property is affected by CTM
v4: Update contributors
v5: Refactor degamma/
Patch based on a previous series by Shashank Sharma.
This introduces optional properties to enable color correction at the
pipe level. It relies on 3 transformations applied to every pixels
displayed. First a lookup into a degamma table, then a multiplication
of the rgb components by a 3x3 matrix
Implement Daniel Stone's recommendation to not read registers to infer
the hardware's state.
v2: Read GAMMA_MODE register value at init
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/intel_color.c | 17 +
drivers/gpu/drm/i915/intel_drv.h | 3 +++
2 files changed, 1
The moves a couple of functions programming the gamma LUT and CSC
units into their own file.
On generations prior to Haswell there is only a gamma LUT. From
haswell on there is also a new enhanced color correction unit that
isn't used yet. This is why we need to set the GAMMA_MODE register,
either
This series introduces pipe level color management through a set of properties
attached to the CRTC. It also provides an implementation for some Intel
platforms.
This series is based of a previous set of patches by Shashank Sharma.
Cheers,
Lionel
Lionel Landwerlin (5):
drm/i915: Extract out g
anything else you'd like? I'm going to mention the I provided
above too
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Reviewed-by: Stéphane Marchesin
On Tue, Feb 2, 2016 at 3:37 PM, Zach Reizner wrote:
> The prime fd to handle ioctl was not used with rockchip before. Support
> was added in order to support potential uses (e.g. zero-copy video
> decode, camera).
>
> Signed-off-by: Zach Reizner
> ---
> drivers
On Tue, Feb 23, 2016 at 01:11:24PM +0200, Tomi Valkeinen wrote:
>
>
> On 23/02/16 12:43, Archit Taneja wrote:
> >
> >
> > On 02/23/2016 02:48 PM, Tomi Valkeinen wrote:
> >>
> >> On 22/02/16 22:10, Rob Herring wrote:
> >>
> If we want all DSI host controllers to use a common binding to desc
happy to get this in.
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The defconfigs for the AXS boards were updated to
enable Designware I2S driver.
Signed-off-by: Jose Abreu
---
arch/arc/configs/axs101_defconfig | 1 +
arch/arc/configs/axs103_defconfig | 1 +
arch/arc/configs/axs103_smp_defconfig | 1 +
3 files changed, 3 insertions(+)
diff --git a/arch
HDMI audio support was added to the AXS board using an
I2S cpu driver and a custom platform driver.
The platform driver supports two channels @ 16 bits with
rates 32k, 44.1k and 48k. ALSA Simple audio card is used to
glue the cpu, platform and codec driver (adv7511).
Signed-off-by: Jose Abreu
--
The defconfigs for the AXS boards were updated so that
ALSA SoC is enabled and also the audio for the ADV7511
HDMI transmitter.
Signed-off-by: Jose Abreu
---
arch/arc/configs/axs101_defconfig | 3 +++
arch/arc/configs/axs103_defconfig | 5 +
arch/arc/configs/axs103_smp_defconfig | 5
ARC AXS10x platforms consist of a mainboard with several peripherals.
One of those peripherals is an HDMI output port controlled by ADV7511
transmitter.
This patch set adds audio for the ADV7511 transmitter and I2S audio for the
AXS10x platform.
Jose Abreu (4):
[adv7511] Add audio support
[a
Tomi
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uld be private to the
driver handling the device, except for some special cases like following
the graph.
Tomi
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Applied. thanks!
Alex
On Mon, Feb 22, 2016 at 9:21 PM, Zhu, Rex wrote:
>
> Reviewed-by: Rex Zhu
>
> Best Regards
> Rex Zhu
>
> -Original Message-
> From: Bradley Pankow [mailto:btpankow at gmail.com]
> Sent: Tuesday, February 23, 2016 9:12 AM
> To: Deucher, Alexander; Zhu, Rex; Zhou,
Hi Tomi,
Thank you for the patch.
On Friday 19 February 2016 11:47:37 Tomi Valkeinen wrote:
> The current driver uses non-blocking DMM fill when releasing memory.
> This gives us a small performance increase as we don't have to wait for
> the fill operation to finish.
>
> However, the driver doe
Hi Tomi,
Thank you for the patch.
On Friday 19 February 2016 11:47:36 Tomi Valkeinen wrote:
> We occasionally see DISPC sync-lost errors when enabling and disabling
> HDMI. Sometimes we get only a few, which get handled (ignored) by the
> driver, but sometimes there's a flood of the errors which
t lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
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On Tue, 12 Jan 2016 13:55:35 -0800
Joshua Clayton wrote:
Ping?
FYI The dts for the board using this panel is now in linux-next.
Is there something more I need to do to get it queued?
They are my first patches for the drm subsystem, so I may be
unfamiliar with the customs.
I just checked; the pa
e) is all about pin/signal
> numbers. Either simplify the binding to be lanes or describe the
> binding in terms of pins.
Perhaps "lane-pins" or something would be more descriptive. If we want
to make the description common, I could change the OMAP implementation
to accept the new property name too.
But, I'm not sure if a common description helps much. Any thoughts?
Tomi
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On 9 February 2016 at 17:50, Daniel Vetter wrote:
> On Fri, Feb 05, 2016 at 11:10:30AM +0800, Xinliang Liu wrote:
>> This patch cleans up the Makefile of drm root directory.
>> Make core and device drivers configuration list sorted Alphabetically.
>>
>> Signed-off-by: Xinliang Liu
>> Reviewed-by:
On 15 February 2016 at 19:04, Oded Gabbay wrote:
> On Sun, Feb 14, 2016 at 2:58 PM, Daniel Vetter wrote:
>> On Sun, Feb 14, 2016 at 11:16:52AM +0200, Oded Gabbay wrote:
>>> Following Daniel's request, I spent some time removing the hard requirement
>>> that radeon and amdgpu will always appear _a
On 15 February 2016 at 19:04, Oded Gabbay wrote:
> On Sun, Feb 14, 2016 at 2:58 PM, Daniel Vetter wrote:
>> On Sun, Feb 14, 2016 at 11:16:52AM +0200, Oded Gabbay wrote:
>>> Following Daniel's request, I spent some time removing the hard requirement
>>> that radeon and amdgpu will always appear _a
On 23.02.2016 04:32, Alex Deucher wrote:
> From: Christian König
>
> A fence is never later than itself. This caused a bunch of overhead for
> AMDGPU.
>
> v2: simplify check as suggested by Michel.
>
> Signed-off-by: Christian König
> Reviewed-by: Michel Dänzer
> Reviewed-by: Alex Deucher
Add ade, dsi and adv7533 DT nodes for hikey board.
Signed-off-by: Xinliang Liu
---
arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 40 +++
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 55 ++
2 files changed, 95 insertions(+)
diff --git a/arch/arm64/b
Add maintainer and reviewer for hisilicon DRM driver.
v5: None.
v4:
- Add Chen Feng as Designated reviewer.
v3: First version.
Signed-off-by: Xinliang Liu
---
MAINTAINERS | 10 ++
1 file changed, 10 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 4978dc19a4d2..b94ac713916a
Add support for external HDMI bridge.
v5: None.
v4: None.
v3:
- Fix a typo: s/exteranl/external.
v2:
- Remove abtraction layer.
Signed-off-by: Xinliang Liu
---
drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c | 52
1 file changed, 52 insertions(+)
diff --git a/drivers/
Add DesignWare dsi host driver for hi6220 SoC.
v5: None.
v4: None.
v3: None.
v2:
- Remove abtraction layer.
Signed-off-by: Xinliang Liu
---
drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c | 50
1 file changed, 50 insertions(+)
diff --git a/drivers/gpu/drm/hisilicon/ki
Add DesignWare MIPI DSI Host Controller v1.02 encoder driver
for hi6220 SoC.
v5: None.
v4: None.
v3:
- Rename file name to dw_drm_dsi.c
- Make encoder type as DRM_MODE_ENCODER_DSI.
- A few cleanup.
v2:
- Remove abtraction layer.
Signed-off-by: Xinliang Liu
Signed-off-by: Xinwei Kong
Signed-off-
Add cma Fbdev, Fbdev is legency and optional, you can enable/disable it by
configuring DRM_FBDEV_EMULATION.
Add hotplug.
v5: None.
v4: None.
v3: None.
v2:
- Use CONFIG_DRM_FBDEV_EMULATION instead of CONFIG_DRM_HISI_FBDEV.
Signed-off-by: Xinliang Liu
---
drivers/gpu/drm/hisilicon/kirin/kirin_drm
Add vblank irq handle.
v5: None.
v4: None.
v3:
- Remove hisi_get_crtc_from_index func.
- A few cleanup.
v2:
- Remove abtraction layer.
Signed-off-by: Xinliang Liu
---
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c | 62 +
drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c
Add plane funcs and helper funcs for ADE.
v5: None.
v4: None.
v3:
- A few cleanup.
v2:
- Remove abtraction layer.
Signed-off-by: Xinliang Liu
---
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c | 535 +++-
1 file changed, 534 insertions(+), 1 deletion(-)
diff --git a/driver
Add crtc funcs and helper funcs for ADE.
v5:
- Use syscon to access ADE media NOC QoS registers instread of directly
writing registers.
- Use reset controller to reset ADE instead of directly writing registers.
v4: None.
v3:
- Make ade as the master driver.
- Use port to connect with encoder.
-
Add kirin DRM master driver for hi6220 SoC which used in HiKey board.
Add dumb buffer feature.
Add prime dmabuf feature.
v5: None.
v4: None.
v3:
- Move and rename all the files to kirin sub-directory.
So that we could separate different seires SoCs' driver.
- Replace drm_platform_init, load, unl
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