Picked it up.
Thanks,
Inki Dae
2016ë
02ì 12ì¼ 22:31ì Chanho Park ì´(ê°) ì´ ê¸:
> This patch adds a exynos5420 driver data to support mic_bypass
> option to bypass the mic from display out path.
> The mic(Mobile image compressor) compresses RGB data from fimd
> and send the compressed data to the mipi dsi.
> The bypass option can be founded from system register and the bit
> is 11. The option bit has been introduced since exynos5420. The
> only difference between exynos5250 and exynos5420/exynos5422 is
> existence of the bit. Until the MIC is defined and enabled from
> device tree, the bypass mic will be default option.
>
> Cc: Inki Dae <inki.dae at samsung.com>
> Cc: Joonyoung Shim <jy0922.shim at samsung.com>
> Cc: Seung-Woo Kim <sw0312.kim at samsung.com>
> Signed-off-by: Chanho Park <chanho61.park at samsung.com>
> ---
> .../bindings/display/exynos/samsung-fimd.txt | 3 ++-
> drivers/gpu/drm/exynos/exynos_drm_fimd.c | 31
> +++++++++++++++++++++-
> 2 files changed, 32 insertions(+), 2 deletions(-)
>
> diff --git
> a/Documentation/devicetree/bindings/display/exynos/samsung-fimd.txt
> b/Documentation/devicetree/bindings/display/exynos/samsung-fimd.txt
> index 27c3ce0..c7c6b9a 100644
> --- a/Documentation/devicetree/bindings/display/exynos/samsung-fimd.txt
> +++ b/Documentation/devicetree/bindings/display/exynos/samsung-fimd.txt
> @@ -12,7 +12,8 @@ Required properties:
> "samsung,exynos3250-fimd"; /* for Exynos3250/3472 SoCs */
> "samsung,exynos4210-fimd"; /* for Exynos4 SoCs */
> "samsung,exynos4415-fimd"; /* for Exynos4415 SoC */
> - "samsung,exynos5250-fimd"; /* for Exynos5 SoCs */
> + "samsung,exynos5250-fimd"; /* for Exynos5250 SoCs */
> + "samsung,exynos5420-fimd"; /* for Exynos5420/5422/5800 SoCs */
>
> - reg: physical base address and length of the FIMD registers set.
>
> diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
> b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
> index 70194d0..41c3bb2 100644
> --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
> +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
> @@ -94,12 +94,14 @@ struct fimd_driver_data {
> unsigned int lcdblk_offset;
> unsigned int lcdblk_vt_shift;
> unsigned int lcdblk_bypass_shift;
> + unsigned int lcdblk_mic_bypass_shift;
>
> unsigned int has_shadowcon:1;
> unsigned int has_clksel:1;
> unsigned int has_limited_fmt:1;
> unsigned int has_vidoutcon:1;
> unsigned int has_vtsel:1;
> + unsigned int has_mic_bypass:1;
> };
>
> static struct fimd_driver_data s3c64xx_fimd_driver_data = {
> @@ -145,6 +147,18 @@ static struct fimd_driver_data exynos5_fimd_driver_data
> = {
> .has_vtsel = 1,
> };
>
> +static struct fimd_driver_data exynos5420_fimd_driver_data = {
> + .timing_base = 0x20000,
> + .lcdblk_offset = 0x214,
> + .lcdblk_vt_shift = 24,
> + .lcdblk_bypass_shift = 15,
> + .lcdblk_mic_bypass_shift = 11,
> + .has_shadowcon = 1,
> + .has_vidoutcon = 1,
> + .has_vtsel = 1,
> + .has_mic_bypass = 1,
> +};
> +
> struct fimd_context {
> struct device *dev;
> struct drm_device *drm_dev;
> @@ -184,6 +198,8 @@ static const struct of_device_id fimd_driver_dt_match[] =
> {
> .data = &exynos4415_fimd_driver_data },
> { .compatible = "samsung,exynos5250-fimd",
> .data = &exynos5_fimd_driver_data },
> + { .compatible = "samsung,exynos5420-fimd",
> + .data = &exynos5420_fimd_driver_data },
> {},
> };
> MODULE_DEVICE_TABLE(of, fimd_driver_dt_match);
> @@ -461,6 +477,18 @@ static void fimd_commit(struct exynos_drm_crtc *crtc)
> return;
> }
>
> + /* TODO: When MIC is enabled for display path, the lcdblk_mic_bypass
> + * bit should be cleared.
> + */
> + if (driver_data->has_mic_bypass && ctx->sysreg &&
> + regmap_update_bits(ctx->sysreg,
> + driver_data->lcdblk_offset,
> + 0x1 << driver_data->lcdblk_mic_bypass_shift,
> + 0x1 << driver_data->lcdblk_mic_bypass_shift)) {
> + DRM_ERROR("Failed to update sysreg for bypass mic.\n");
> + return;
> + }
> +
> /* setup horizontal and vertical display size. */
> val = VIDTCON2_LINEVAL(mode->vdisplay - 1) |
> VIDTCON2_HOZVAL(mode->hdisplay - 1) |
> @@ -861,7 +889,8 @@ static void fimd_dp_clock_enable(struct exynos_drm_crtc
> *crtc, bool enable)
> * clock. On these SoCs the bootloader may enable it but any
> * power domain off/on will reset it to disable state.
> */
> - if (ctx->driver_data != &exynos5_fimd_driver_data)
> + if (ctx->driver_data != &exynos5_fimd_driver_data ||
> + ctx->driver_data != &exynos5420_fimd_driver_data)
> return;
>
> val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE;
>
