On Wed, Jan 27, 2010 at 10:54, Tom Gross wrote:
> Johnathan, the custom FPGA firmware you describe sounds like it might
> be perfect for what we want to do, provided it's not impossible to
> demux the data stream.
It's straightforward. Just use gr.deinterleave(gr.sizeof_gr_complex)
after the us
thanks Johnathan and Eric, I'm glad I asked before spending too much
time trying to make this work! :-)
Johnathan, the custom FPGA firmware you describe sounds like it might
be perfect for what we want to do, provided it's not impossible to
demux the data stream. I haven't seen any usrp2 FPGA sou
On Wed, Jan 27, 2010 at 10:23, Johnathan Corgan
wrote:
> There is a custom USRP2 top-level FPGA build that creates two
> synchronous DDCs (they share a CORDIC NCO phase accumulator) in the
> usrp2/fpga/top/u2_rev3_2rx_iad directory.
I just realized that the Makefile for this build has not been
On Wed, Jan 27, 2010 at 10:05, Eric Blossom wrote:
> See comment above about there currently being only a single DDC in the
> FPGA. If you want two channels, amongst other things, you'll need to
> instantiate two DDCs, and add code that interleaves the samples from
> the two DDCs. You'll also h
On Tue, Jan 26, 2010 at 10:09:01PM -0500, Tom Gross wrote:
> I am in the process of hacking up the usrp2 host and firmware to
> support two receiver channels. I'm at the point where
> "start_rx_streaming" is being acknowledged for channel 1 but there is
> no data being returned for that channel.
I am in the process of hacking up the usrp2 host and firmware to
support two receiver channels. I'm at the point where
"start_rx_streaming" is being acknowledged for channel 1 but there is
no data being returned for that channel. I don't actually understand
yet where the receiver data is packaged
