On 08/04/2011 10:55 PM, Josh Blum wrote:
>
> It was never used. That rssi.v file is just there so people can ask
> about it every few weeks. Its probably one of the least interesting
> things in the library of verilog components.
>
>
Because, hey, otherwise you might get lonely, right? :-)
-
On 08/04/2011 07:12 PM, Marcus D. Leech wrote:
> On 08/04/2011 09:52 PM, Page Jack wrote:
>> Hi Colby,
>> I know cheaper in hardware, but now I don't understand how using IIR
>> filter can compute the RSSI?
>>
> Seems to me that the RSSI-in-FPGA stuff was not really fully baked,
> unless I'm mis
On 08/04/2011 09:52 PM, Page Jack wrote:
> Hi Colby,
> I know cheaper in hardware, but now I don't understand how using IIR
> filter can compute the RSSI?
>
Seems to me that the RSSI-in-FPGA stuff was not really fully baked,
unless I'm mistaken, the RSSI
function isn't used by any higher-level f
On 08/04/2011 09:52 PM, Page Jack wrote:
> Hi Colby,
> I know cheaper in hardware, but now I don't understand how using IIR
> filter can compute the RSSI?
>
>
The power estimate in a complex channel is computed as:
AVG(I**2 + Q**2)
An IIR filter is a simple way of approximating the AVG part of t
Hi Colby,
I know cheaper in hardware, but now I don't understand how using IIR filter
can compute the RSSI?
On Fri, Aug 5, 2011 at 9:18 AM, Colby Boyer wrote:
> Cheaper in hardware. You only need one adder.
>
>
> On Thu, Aug 4, 2011 at 6:13 PM, Page Jack wrote:
>
>> Hi Colby,
>> I don't underst
Cheaper in hardware. You only need one adder.
On Thu, Aug 4, 2011 at 6:13 PM, Page Jack wrote:
> Hi Colby,
> I don't understand why compute RSSI need an IIR filter? as I know the rssi
> can be compute
> like that: (sample[0]*sample[0]+...sample[i]*sample[i]) / (i+1)
>
>
> Regards!
>
>
> On Thu,
Hi Colby,
I don't understand why compute RSSI need an IIR filter? as I know the rssi
can be compute
like that: (sample[0]*sample[0]+...sample[i]*sample[i]) / (i+1)
Regards!
On Thu, Aug 4, 2011 at 2:44 PM, Colby Boyer wrote:
> On Wed, Aug 3, 2011 at 6:30 PM, Page Jack wrote:
>
>> the code belo
On Wed, Aug 3, 2011 at 6:30 PM, Page Jack wrote:
> the code below is in sdr_lib/rssi.v I don't understand especially this
> line: rssi_int <= #1 rssi_int + abs_adc - rssi_int[25:10];
>
> wire [11:0] abs_adc = adc[11] ? ~adc : adc;
>
>reg [25:0] rssi_int;
>always @(posedge clock)
>
the code below is in sdr_lib/rssi.v I don't understand especially this line:
rssi_int <= #1 rssi_int + abs_adc - rssi_int[25:10];
wire [11:0] abs_adc = adc[11] ? ~adc : adc;
reg [25:0] rssi_int;
always @(posedge clock)
if(reset | ~enable)
rssi_int <= #1 26'd0;
else
