On 08/04/2011 07:12 PM, Marcus D. Leech wrote:
> On 08/04/2011 09:52 PM, Page Jack wrote:
>> Hi Colby,
>> I know cheaper in hardware, but now I don't understand how using IIR
>> filter can compute the RSSI? 
>>
> Seems to me that the RSSI-in-FPGA stuff was not really fully baked,
> unless I'm mistaken, the RSSI
>   function isn't used by any higher-level functions in the USRP2/N2XXX
> implementations.
> 

It was never used. That rssi.v file is just there so people can ask
about it every few weeks. Its probably one of the least interesting
things in the library of verilog components.

> I always compute the signal strength at the final channel bandwidth, in
> software, whereas the RSSI in
>   the FPGA code seems to be running at the raw ADC bandwidth--which can
> produce wildly
>   different RSSI estimates than an estimate produced from your final
> channel bandwidth.
> 
> 
> 
> 

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