Cheaper in hardware. You only need one adder.

On Thu, Aug 4, 2011 at 6:13 PM, Page Jack <jack.page...@gmail.com> wrote:

> Hi Colby,
> I don't understand why compute RSSI need an IIR filter? as I know the rssi
> can be compute
> like that: (sample[0]*sample[0]+...sample[i]*sample[i]) / (i+1)
>
>
> Regards!
>
>
> On Thu, Aug 4, 2011 at 2:44 PM, Colby Boyer <colby.bo...@gmail.com> wrote:
>
>> On Wed, Aug 3, 2011 at 6:30 PM, Page Jack <jack.page...@gmail.com> wrote:
>>
>>> the code below is in sdr_lib/rssi.v I don't understand especially this
>>> line: rssi_int <= #1 rssi_int + abs_adc - rssi_int[25:10];
>>>
>>>   wire [11:0] abs_adc = adc[11] ? ~adc : adc;
>>>
>>>    reg [25:0]  rssi_int;
>>>    always @(posedge clock)
>>>      if(reset | ~enable)
>>>        rssi_int <= #1 26'd0;
>>>      else
>>>        rssi_int <= #1 rssi_int + abs_adc - rssi_int[25:10];
>>>
>>>    assign      rssi = rssi_int[25:10];
>>>
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>>>
>> It appears to be a clever way to implement a single pole IIR filter. Josh?
>>
>> If you recall an IIR is defined as y[n] = (1-alpha) * y[n-1] + x[n]
>>
>> Since multiplier are expensive in hardware, lets use a multiples of two so
>> you can bit shift, then add and subtract. :D In this case alpha is 2^-10
>>
>> --Colby
>>
>
>
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