Hi,
I was originally responsible for suggesting this change internally(more
specifically - to switch from Intel specific LPSS UART driver to EDK2 driver
which on inspection seemed to cover all relevant modes of operations of LPSS
UART).
First I would like to explain how exactly we are using th
1. Using SerialDxe instead of PciSioSerialDxe - from our perspective the main
idea is to avoid maintaining our own implementation of functions that actually
communicate with UART controller. To use SerialDxe we would have to still
maintain our own SerialPortLib that actually goes and sends data
Is the idea to refactor PciSioSerialDxe to extract functions that access the HW
and wrap it in the SerialPortLib instance? That solution would still save us
some maintenance cost. However exploring the idea further I see following
problems:
1. Relying on driver binding produces a fairly nice fl
Sorry, I didn't want to make an impression that I expected solution to be
delivered, I was merely trying to explain some of the complexity we are trying
to handle on our side and why we didn't went for SerialDxe and instead opted to
make PciSioSerialDxe work for our use case. Anyway thanks for t
d. I suspect it is a hardware problem.
Cc: Hao A Wu
Cc: Marcin Wojtas
Albecki, Mateusz (1):
MdeModulePkg/SdMmcPciHcDxe: Fix bus timing switch sequence
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 54 +++--
1 file changed, 5 insertions(+), 49 deletions(-)
SD specification recommends switching card bus timing before
switching bus timing in controller. Emmc driver used to do
this switch other way around. This commit adds controller
timing switch in EmmcSwitchBusTiming function to enforce this
order and removes all controller timing programing from
Emm
> -Original Message-
> From: Wu, Hao A
> Sent: Wednesday, September 25, 2019 5:34 AM
> To: Albecki, Mateusz ; devel@edk2.groups.io
> Cc: Marcin Wojtas
> Subject: RE: [PATCH 1/1] MdeModulePkg/SdMmcPciHcDxe: Fix bus timing
> switch sequence
>
> > -
> -Original Message-
> From: Wu, Hao A
> Sent: Thursday, September 26, 2019 3:36 AM
> To: Albecki, Mateusz ; devel@edk2.groups.io
> Cc: Marcin Wojtas
> Subject: RE: [PATCH 1/1] MdeModulePkg/SdMmcPciHcDxe: Fix bus timing
> switch sequence
>
> > -
eed. I suspect it is a hardware problem.
Tests performed on patch series v2:
-eMMC enumeration and OS boot in backwards compatible legacy timing.
Performed on single host controller and 2 eMMC devices(Samsung and SanDisk)
Cc: Hao A Wu
Cc: Marcin Wojtas
Albecki, Mateusz (3):
MdeModulePkg/S
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2218
SD specification recommends switching card bus timing before
switching bus timing in controller. Emmc driver used to do
this switch other way around. This commit adds controller
timing switch in EmmcSwitchBusTiming function to enforce this
o
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2218
There is a bug in current driver code that makes
it impossible for it to work with devices that
only work in legacy speed mode since the function
EmmcSwitchToHighSpeed will return with EFI_INVALID_ARGUMENT
for such bus mode. Since the logic
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2218
Stopping the SD clock before switching host controller
bus timing is only neccessary if preset value enable is
set in host controller. Code that performs switch to
HS200 doesn't check this condition right now and we also
don't do the SD cloc
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1140
Error detection function will now check if the command
failure has been caused by one of the errors that can
appear randomly on link(CRC error + end bit error). If
such an error has been a cause of failure, function will
return EFI_CRC_ERROR
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1140
To increase the resiliency driver will now attempt to
retry the commands that failed due to the CRC error up
to 5 times. This should address the problems with the commands
that fail due to random condition on links. This should also
help the
Driver used to reset the DAT lane on a current error which
is not required according to SD specification(it's not going
to help). This patch will reset the DAT lane only on DAT
lane specific errors.
Cc: Hao A Wu
Cc: Marcin Wojtas
Cc: Zhichao Gao
Cc: Liming Gao
Signed-off-by: Mateusz Albecki
performed:
-Boot eMMC in HS400
-Boot eMMC in HS400 with simulated CRC error on every first CMD13
Cc: Hao A Wu
Cc: Marcin Wojtas
Cc: Zhichao Gao
Cc: Liming Gao
Signed-off-by: Mateusz Albecki
Mateusz Albecki (4):
MdeModulePkg/SdMmcPciHcDxe: Fix DAT lane SW reset
MdeModulePkg/SdMmcPciHcDxe
This patch adds retries for async execution for commands that
failed due to the CRC errors.
Cc: Hao A Wu
Cc: Marcin Wojtas
Cc: Zhichao Gao
Cc: Liming Gao
Signed-off-by: Mateusz Albecki
---
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c | 6 --
1 file changed, 4 insertions(+), 2 dele
This patch series aims to refactor command processing to achieve following
1. Trace the failing TRB packets to see what commands are failing and for what
reasons
2. Get the response data even if data transfer timed out to allow easier
debugging
3. Fix the PIO mode which is currently completely b
To allow for easier debug of failing commands we
have added a capability to print TRB and command
packet when we start execution of the TRB(on
DEBUG_VERBOSE level) and when the TRB failed to
execute correctly(on DEBUG_ERROR level). Additionally
we will also print error interrupt status and interrup
Current driver does not support PIO transfer mode for
commands other then tuning. This change adds the code
to transfer PIO data.
Cc: Hao A Wu
Cc: Marcin Wojtas
Cc: Zhichao Gao
Cc: Liming Gao
Signed-off-by: Mateusz Albecki
---
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h | 3 +
MdeM
This patch refactors the way in which the driver will check
the data transfer completion. Data transfer related
functionalities have been moved to separate function.
Cc: Hao A Wu
Cc: Marcin Wojtas
Cc: Zhichao Gao
Cc: Liming Gao
Signed-off-by: Mateusz Albecki
---
MdeModulePkg/Bus/Pci/SdMmcPc
SdMmcPciHcDxe driver used to read response only after
command and data transfer completed. According to SDHCI
specification response data is ready after the command
complete status is set by the host controller. Getting
the response data early will help debugging the cases
when command completed bu
age-
> From: Wu, Hao A
> Sent: Wednesday, February 5, 2020 4:16 AM
> To: devel@edk2.groups.io; Albecki, Mateusz
> Cc: Marcin Wojtas ; Gao, Zhichao
> ; Gao, Liming
> Subject: RE: [edk2-devel] [PATCH 2/4] MdeModulePkg/SdMmcPciHcDxe:
> Read response on command completion
Hi,
As in the patch 2/4 section 3.7.1.2 recommends that we clear the transfer
complete(step 6) just after reading it(step 5).
Thanks,
Mateusz
> -Original Message-
> From: Wu, Hao A
> Sent: Wednesday, February 5, 2020 4:16 AM
> To: devel@edk2.groups.io; Albecki, Mateusz
fix
it in v2.
Thanks,
Mateusz
> -Original Message-
> From: Wu, Hao A
> Sent: Wednesday, February 5, 2020 4:16 AM
> To: devel@edk2.groups.io; Albecki, Mateusz
> Cc: Marcin Wojtas ; Gao, Zhichao
> ; Gao, Liming
> Subject: RE: [edk2-devel] [PATCH 4/4] MdeModulePkg/SdM
SdMmcPciHcDxe driver used to read response only after
command and data transfer completed. According to SDHCI
specification response data is ready after the command
complete status is set by the host controller. Getting
the response data early will help debugging the cases
when command completed bu
To allow for easier debug of failing commands we
have added a capability to print TRB and command
packet when we start execution of the TRB(on
DEBUG_VERBOSE level) and when the TRB failed to
execute correctly(on DEBUG_ERROR level). Additionally
we will also print error interrupt status and interrup
This patch series aims to refactor command processing to achieve following
- Trace the failing TRB packets to see what commands are failing and for what
reasons
- Get the response data even if data transfer timed out to allow easier
debugging
- Fix the PIO mode which is currently completely brok
This patch refactors the way in which the driver will check
the data transfer completion. Data transfer related
functionalities have been moved to separate function.
Cc: Hao A Wu
Cc: Marcin Wojtas
Cc: Zhichao Gao
Cc: Liming Gao
Signed-off-by: Mateusz Albecki
---
MdeModulePkg/Bus/Pci/SdMmcPc
Current driver does not support PIO transfer mode for
commands other then tuning. This change adds the code
to transfer PIO data.
Cc: Hao A Wu
Cc: Marcin Wojtas
Cc: Zhichao Gao
Cc: Liming Gao
Signed-off-by: Mateusz Albecki
---
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h | 3 +
MdeM
.
Regarding the push - I am fine with this change making it to master after the
stable tag.
Thanks,
Mateusz
> -Original Message-
> From: Wu, Hao A
> Sent: Thursday, February 20, 2020 1:40 AM
> To: Albecki, Mateusz ; devel@edk2.groups.io
> Cc: Marcin Wojtas ; Gao, Zhichao
,
Mateusz
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Albecki,
> Mateusz
> Sent: Thursday, February 20, 2020 1:36 PM
> To: Wu, Hao A ; devel@edk2.groups.io
> Cc: Marcin Wojtas ; Gao, Zhichao
> ; Gao, Liming
> Subject: Re: [edk2-devel] [PATCHv2 0/4] Md
This patch series aims to increase the reliability of the eMMC detection by
exectuing the SEND_STATUS after SWITCH command on the lower frequency. Currently
the driver will first switch the frequency to the new target and then execute
SEND_STATUS to see if SWITCH was a success. While this behavior
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1140
To avoid stability issues on some designs the driver
will now send SEND_STATUS at previous, lower, frequency
when upgrading the bus timing.
Cc: Hao A Wu
Cc: Marcin Wojtas
Cc: Zhichao Gao
Cc: Liming Gao
Signed-off-by: Mateusz Albecki
-
ove the extra check after I have found out that is not the case.
Thanks,
Mateusz
> -Original Message-
> From: Wu, Hao A
> Sent: Monday, February 24, 2020 8:01 AM
> To: Albecki, Mateusz ; devel@edk2.groups.io
> Cc: Marcin Wojtas ; Gao, Zhichao
> ; Gao, Liming
>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1140
To avoid stability issues on some designs the driver
will now send SEND_STATUS at previous, lower, frequency
when upgrading the bus timing.
Cc: Hao A Wu
Cc: Marcin Wojtas
Cc: Zhichao Gao
Cc: Liming Gao
Signed-off-by: Mateusz Albecki
-
This patch series aims to increase the reliability of the eMMC detection by
exectuing the SEND_STATUS after SWITCH command on the lower frequency.
Currently the driver will first switch the frequency to the new target and then
execute SEND_STATUS to see if SWITCH was a success. While this behavi
This patch refactors the way in which the driver will check
the data transfer completion. Data transfer related
functionalities have been moved to separate function.
Cc: Hao A Wu
Cc: Marcin Wojtas
Cc: Zhichao Gao
Cc: Liming Gao
Signed-off-by: Mateusz Albecki
---
MdeModulePkg/Bus/Pci/SdMmcPc
Driver code used to map memory for DMA transfer even if host doesn't
support DMA. This is causing memory corruption when driver transfers
data using PIO. This change refactors the code to skip call to
PciIo->Map for non DMA transfers.
Cc: Hao A Wu
Cc: Marcin Wojtas
Cc: Zhichao Gao
Cc: Liming Ga
This patch series aims to refactor command processing to achieve following
- Trace the failing TRB packets to see what commands are failing and for what
reasons
- Get the response data even if data transfer timed out to allow easier
debugging
- Fix the PIO mode which is currently completely brok
SdMmcPciHcDxe driver used to read response only after
command and data transfer completed. According to SDHCI
specification response data is ready after the command
complete status is set by the host controller. Getting
the response data early will help debugging the cases
when command completed bu
To allow for easier debug of failing commands we
have added a capability to print TRB and command
packet when we start execution of the TRB(on
DEBUG_VERBOSE level) and when the TRB failed to
execute correctly(on DEBUG_ERROR level). Additionally
we will also print error interrupt status and interrup
Current driver does not support PIO transfer mode for
commands other then tuning. This change adds the code
to transfer PIO data.
Cc: Hao A Wu
Cc: Marcin Wojtas
Cc: Zhichao Gao
Cc: Liming Gao
Signed-off-by: Mateusz Albecki
---
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h | 3 +
MdeM
The first patch refactors the SdMmcClockSupply function with a goal
of sending the EdkiiSdMmcSwitchClockFreq notification before we send the
CMD13 to check the switch status in eMMC init flow. This is required to
avoid sending the CMD13 on link that still has not been fixed by platform.
To avoid c
For eMMC modules we used to notify the platform about frequency
change only after sending CMD13 which meant that platform
might not get a chance to apply required post frequency
change fixes to get the clock stable. To fix this
notification has been moved to SdMmcHcClockSupply function
just after w
In SD card voltage switch flow we used to redo the
entire internal clock setup after voltage switch.
Since internal clock has already been setup this
is wasting time on polling the internal clock stable.
This commit changes it to only start the SD clock.
Cc: Hao A Wu
Cc: Marcin Wojtas
Cc: Zhicha
No problem with new subject from my side.
> -Original Message-
> From: Wu, Hao A
> Sent: Tuesday, December 24, 2019 3:52 AM
> To: Albecki, Mateusz ; devel@edk2.groups.io
> Cc: Marcin Wojtas ; Gao, Zhichao
> ; Gao, Liming ; Ard
> Biesheuvel
> Subject: RE: [PATCH
This patch adds retries for async execution for commands that
failed due to the CRC errors.
Cc: Hao A Wu
Cc: Marcin Wojtas
Cc: Zhichao Gao
Cc: Liming Gao
Signed-off-by: Mateusz Albecki
---
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c | 6 --
1 file changed, 4 insertions(+), 2 dele
HS400 with simulated CRC error on every first CMD13
Cc: Hao A Wu
Cc: Marcin Wojtas
Cc: Zhichao Gao
Cc: Liming Gao
Signed-off-by: Mateusz Albecki
Mateusz Albecki (3):
MdeModulePkg/SdMmcPciHcDxe: Refactor command error detection
MdeModulePkg/SdMmcPciHcDxe: Add retries for sync commands
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1140
Error detection function will now check if the command
failure has been caused by one of the errors that can
appear randomly on link(CRC error + end bit error). If
such an error has been a cause of failure function will
return EFI_CRC_ERROR
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1140
To increase the resiliency driver will now attempt to
retry the commands that failed due to the CRC error up
to 5 times. This should address the problems with the commands
that fail due to random condition on links. This should also
help the
lbecki, Mateusz
> Sent: Tuesday, January 7, 2020 12:06 PM
> To: devel@edk2.groups.io
> Cc: Albecki, Mateusz ; Wu, Hao A
> ; Marcin Wojtas ; Gao, Zhichao
> ; Gao, Liming
> Subject: [PATCH 0/3] MdeModulePkg/SdMmcPciHcDxe: Retry the
> commands that failed due to CRC error
>
> RE
Changed @rtval to @retval in SdMmcHcStartSdClock
function description.
Cc: Hao A Wu
Signed-off-by: Mateusz Albecki
---
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 2 +-
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git
8 AM
> To: Albecki, Mateusz ; devel@edk2.groups.io
> Cc: Marcin Wojtas ; Gao, Zhichao
> ; Gao, Liming
> Subject: RE: [PATCH 1/3] MdeModulePkg/SdMmcPciHcDxe: Refactor
> command error detection
>
> Hello Mateusz,
>
> Some inline comments below:
>
>
> > -
To cover additional host controller programming mentioned in the UFS
specification
we have added an additional protocol that allows the UEFI driver to give control
to platform driver. This allows the platform to perform any additional steps
needed for the stable operation.
Test coverage:
Tested o
https://bugzilla.tianocore.org/show_bug.cgi?id=1343
EDKII_UFS_HC_PLATFORM_PROTOCOL will allow the platform to inject
platform specific logic into standard UFS flows. Right now we
support callbacks pre and post host controller enable and pre
and post link startup. Provided callbacks allow the platf
https://bugzilla.tianocore.org/show_bug.cgi?id=1343
UfsExecUicCommand function has been refactored to allow
the caller to check the command results which is important
for commands such as UIC read.
Cc: Hao A Wu
Signed-off-by: Mateusz Albecki
---
MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.
https://bugzilla.tianocore.org/show_bug.cgi?id=1343
Private data has been refactored to use EDKII_UFS_HC_INFO structure
to store host controller capabilities and version
information. Getting host controller data has been moved
into single place and is done before host controller enable.
Cc: Hao A
https://bugzilla.tianocore.org/show_bug.cgi?id=1343
This commit adds EDKII_UFS_HC_PLATFORM_PROTOCOL implementation
in UfsPassThruDxe driver in version 1. Driver assumes that at
most one instance of the protocol exists in the system. Presence
of the protocol is not mandatory.
Cc: Hao A Wu
Signed-
Hi,
Sure I agree. That was my original intention and then I forgot to add goto
Error.
Thanks,
Mateusz
> -Original Message-
> From: Wu, Hao A
> Sent: Thursday, August 8, 2019 4:37 AM
> To: devel@edk2.groups.io; Albecki, Mateusz
> Subject: RE: [edk2-devel] [PATCH 3/
Hi,
Yes that is bug. It should be placed before return EFI_SUCCESS. I will fix it
in v2.
Thanks,
Mateusz
> -Original Message-
> From: Wu, Hao A
> Sent: Thursday, August 8, 2019 4:37 AM
> To: Albecki, Mateusz ; devel@edk2.groups.io
> Subject: RE: [PATCH 4/4] MdeModulePkg
https://bugzilla.tianocore.org/show_bug.cgi?id=1343
UfsExecUicCommand function has been refactored to allow
the caller to check the command results which is important
for commands such as UIC read.
Cc: Hao A Wu
Signed-off-by: Mateusz Albecki
---
MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.
To cover additional host controller programming mentioned in the UFS
specification we have added an additional protocol
that allows the UEFI driver to give control to platform driver. This allows the
platform to perform any additional
steps needed for the stable operation.
Changes in v2:
- UFS d
https://bugzilla.tianocore.org/show_bug.cgi?id=1343
Private data has been refactored to use EDKII_UFS_HC_INFO structure
to store host controller capabilities and version
information. Getting host controller data has been moved
into single place and is done before host controller enable.
Cc: Hao A
https://bugzilla.tianocore.org/show_bug.cgi?id=1343
EDKII_UFS_HC_PLATFORM_PROTOCOL will allow the platform to inject
platform specific logic into standard UFS flows. Right now we
support callbacks pre and post host controller enable and pre
and post link startup. We also allow the platform to over
https://bugzilla.tianocore.org/show_bug.cgi?id=1343
This commit adds EDKII_UFS_HC_PLATFORM_PROTOCOL implementation
in UfsPassThruDxe driver in version 1. Driver assumes that at
most one instance of the protocol exists in the system. Presence
of the protocol is not mandatory.
Cc: Hao A Wu
Signed-
Hi,
Please ignore this series. I have used wrong branch when generating patches. V3
will contain the fixes.
Thanks,
Mateusz
> -Original Message-
> From: Albecki, Mateusz
> Sent: Friday, August 9, 2019 2:21 PM
> To: devel@edk2.groups.io
> Cc: Albecki, Mateusz ; Wu, Hao
To cover additional host controller programming mentioned in the UFS
specification we have added an additional protocol that allows the UEFI driver
to give control to platform driver. This allows the platform to perform any
additional steps needed for the stable operation.
Changes in v3:
- UFS
https://bugzilla.tianocore.org/show_bug.cgi?id=1343
EDKII_UFS_HC_PLATFORM_PROTOCOL will allow the platform to inject
platform specific logic into standard UFS flows. Right now we
support callbacks pre and post host controller enable and pre
and post link startup. Provided callbacks allow the platf
https://bugzilla.tianocore.org/show_bug.cgi?id=1343
UfsExecUicCommand function has been refactored to allow
the caller to check the command results which is important
for commands such as UIC read.
Cc: Hao A Wu
Signed-off-by: Mateusz Albecki
---
MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.
https://bugzilla.tianocore.org/show_bug.cgi?id=1343
This commit adds EDKII_UFS_HC_PLATFORM_PROTOCOL implementation
in UfsPassThruDxe driver in version 1. Driver assumes that at
most one instance of the protocol exists in the system. Presence
of the protocol is not mandatory.
Cc: Hao A Wu
Signed-
https://bugzilla.tianocore.org/show_bug.cgi?id=1343
Private data has been refactored to use EDKII_UFS_HC_INFO structure
to store host controller capabilities and version
information. Getting host controller data has been moved
into single place and is done before host controller enable.
Cc: Hao A
Resending to group.
From: Wu, Hao A
Sent: Monday, June 10, 2019 5:18 AM
To: Albecki, Mateusz
Subject: RE: [PATCH 0/2] Add GetOperatingParam notify phase to SdMmcOverride
protocol
Hello Mateusz,
Thanks for the patch series and sorry for the delayed response.
One question first, I did not
Resending to group.
> -Original Message-
> From: Wu, Hao A
> Sent: Monday, June 10, 2019 5:19 AM
> To: Albecki, Mateusz
> Subject: RE: [PATCH 1/2] MdeModulePkg/SdMmcOverride: Add
> GetOperatingParam notify phase
>
> Thanks Mateusz,
>
> Please refer to the
-Original Message-
> From: Wu, Hao A
> Sent: Monday, June 10, 2019 5:19 AM
> To: Albecki, Mateusz
> Subject: RE: [PATCH 2/2] MdeModulePkg/SdMmcHcDxe: Implement revision
> 3 of SdMmcOverrideProtocol
>
> Hello Mateusz,
>
> Some inline comments below:
>
> &
bility and platform selection)
and update only SD case.
Thanks,
Mateusz
> -Original Message-
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Albecki, Mateusz
> Sent: Thursday, June 13, 2019 4:39 PM
> To: devel@edk2.groups.io
> Cc: Wu, Hao A
> Sub
e any host
programming.
Thanks,
Mateusz
> -Original Message-
> From: Wu, Hao A
> Sent: Friday, June 14, 2019 5:15 AM
> To: Albecki, Mateusz ; devel@edk2.groups.io;
> m...@semihalf.com
> Subject: RE: [PATCH 2/2] MdeModulePkg/SdMmcHcDxe: Implement revision
>
speed(non UHS-I)
with no Override protocol(legacy card used)
Cc: Hao A Wu
Albecki, Mateusz (1):
MdeModulePkg/SdMmcHcDxe: Implement revision 3 of SdMmcOverrideProtocol
Mateusz Albecki (1):
MdeModulePkg/SdMmcOverride: Add GetOperatingParam notify phase
MdeModulePkg/Bus/Pci/SdMmcPci
https://bugzilla.tianocore.org/show_bug.cgi?id=1882
The new notify phase allows platform to configure additional
bus paramters in addition to parameters that can already be configured
with capability override. Specifically we allow to configure bus width,
clock frequency and driver strength. If pl
From: "Albecki, Mateusz"
https://bugzilla.tianocore.org/show_bug.cgi?id=1882
Implement support for GetOperatingParamters notify phase
in SdMmcHcDxe driver. GetOperatingParameters notify phase
is signaled before we start card detection and initialization.
Code has been updated for bot
https://bugzilla.tianocore.org/show_bug.cgi?id=1882
The new notify phase allows platform to configure additional
bus paramters in addition to parameters that can already be configured
with capability override. Specifically we allow to configure bus width,
clock frequency and driver strength. If pl
d and high speed(non UHS-I)
with SdMmcOverride installed and UHS-I disabled in capability
- SD card enumeration in UEFI shell on default speed and high speed(non UHS-I)
with no Override protocol(legacy card used)
Cc: Hao A Wu
Albecki, Mateusz (1):
MdeModulePkg/SdMmcHcDxe: Implement revision
From: "Albecki, Mateusz"
https://bugzilla.tianocore.org/show_bug.cgi?id=1882
Implement support for GetOperatingParamters notify phase
in SdMmcHcDxe driver. GetOperatingParameters notify phase
is signaled before we start card detection and initialization.
Code has been updated for bot
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1341
Since UFS specification requirs the data buffer specified
in PRDT to be DWORD aligned in size we had a code in
UfsInitUtpPrdt that aligned the data buffer by rounding down
the buffer size to DWORD boundary. This meant that for SCSI
commands
In current implementation we are checking for device presence every
time we execute UIC command. To make UfsExecUicCommands more generic
checking device presence has been moved to UfsDeviceDetection.
Cc: Hao A Wu
Signed-off-by: Mateusz Albecki
---
.../Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c
Test info:
Tested device presence detection before and after change on real hardware. No
functional change in UFS detection.
> -Original Message-
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Albecki, Mateusz
> Sent: Friday, June 21, 2019 5:27 PM
Test info:
Tested UFS enumeration in EFI shell and it is passing on real HW with Samsung
device.
Tested read/write to UFS device in EFI shell.
> -Original Message-
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Albecki, Mateusz
> Sent: Friday, Jun
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1341
Since UFS specification requirs the data buffer specified
in PRDT to be DWORD aligned in size we had a code in
UfsInitUtpPrdt that aligned the data buffer by rounding down
the buffer size to DWORD boundary. This meant that for SCSI
commands
Fixed the review comments from v1. Test info is the same as on v1. UFS
enumeration is passing and I can see LUs enumerated in efi shell.
> -Original Message-
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Albecki, Mateusz
> Sent: Tuesday, June 25, 2
Replies inline
> -Original Message-
> From: Wu, Hao A
> Sent: Monday, June 24, 2019 10:46 AM
> To: Albecki, Mateusz ; devel@edk2.groups.io
> Subject: RE: [PATCH v3 2/2] MdeModulePkg/SdMmcHcDxe: Implement
> revision 3 of SdMmcOverrideProtocol
>
> > -Origina
10:15 AM
> To: Albecki, Mateusz ; devel@edk2.groups.io
> Subject: RE: [PATCH v3 1/2] MdeModulePkg/SdMmcOverride: Add
> GetOperatingParam notify phase
>
> > -Original Message-
> > From: Albecki, Mateusz
> > Sent: Friday, June 21, 2019 11:12 PM
> > To: deve
Hi,
No concerns from my side. I just didn't think ZeroMem would be useful there
since buffer doesn't contain any data from device at that point so I didn't add
it.
Thanks,
Mateusz
> -Original Message-
> From: Wu, Hao A
> Sent: Wednesday, June 26, 2019 2:19 A
speed(non UHS-I)
with SdMmcOverride installed and UHS-I disabled in capability
- SD card enumeration in UEFI shell on default speed and high speed(non UHS-I)
with no Override protocol(legacy card used)
Cc: Hao A Wu
Albecki, Mateusz (1):
MdeModulePkg/SdMmcHcDxe: Implement revision
From: "Albecki, Mateusz"
https://bugzilla.tianocore.org/show_bug.cgi?id=1882
Implement support for GetOperatingParamters notify phase
in SdMmcHcDxe driver. GetOperatingParameters notify phase
is signaled before we start card detection and initialization.
Code has been updated for bot
https://bugzilla.tianocore.org/show_bug.cgi?id=1882
The new notify phase allows platform to configure additional
bus paramters in addition to parameters that can already be configured
with capability override. Specifically we allow to configure bus width,
clock frequency and driver strength. If pl
.groups.io] On Behalf Of Marcin
Wojtas
Sent: Friday, June 28, 2019 9:42 AM
To: Wu, Hao A
Cc: Albecki, Mateusz ; Sumit Garg
; Ard Biesheuvel ;
edk2-devel-groups-io
Subject: Re: [edk2-devel] [PATCH v4 0/2] MdeModulePkg/SdMmcHcDxe: Implement
revision 3 of SdMmcOverrideProtocol
Hi Hao,
pt., 28 cze
ommands. Let me know what you
think.
Thanks,
Mateusz
-Original Message-
From: Wu, Hao A
Sent: Friday, April 12, 2019 8:35 AM
To: Albecki, Mateusz ; devel@edk2.groups.io
Cc: Ni, Ray
Subject: RE: [PATCH 3/3] MdeModulePkg/UfsPassThruDxe: Add UFS info protocol
Resend this one to the new maili
/sata_abort_completion)
- it should be noted that qemu doesn't really support trust protocol on SATA
drive but for the purposes of the test it should be enough.
Cc: Hao A Wu
Cc: Ray Ni
Signed-off-by: Mateusz Albecki
Mateusz Albecki (1):
MdeModulePkg/Ata: Fix command status reporting
.../Bu
Bugzilla: https://bugzilla.tianocore.org/show_bug.cgi?id=4016
AtaAtapiPassThru driver was reporting recovery status on failed command
packets which led to incorrect flows in upper layers and to SCT tests
fails. This commit will change the logic to report command status.
Cc: Hao A Wu
Cc: Ray Ni
This patch adds support for PEIMs in UefiDevicePathLib. Although this library
and DEVICE_PATH_PROTOCOL
itself was initially intended for DXE the use case of unlocking opal-locked
storage devices during S3
resume makes it useful in PEI.
As it is the change will break the users who will need to ch
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