This patch series aims to increase the reliability of the eMMC detection by exectuing the SEND_STATUS after SWITCH command on the lower frequency. Currently the driver will first switch the frequency to the new target and then execute SEND_STATUS to see if SWITCH was a success. While this behavior is not against the eMMC/SD specification it has been observed that on some designs switching to HS200 @200MHz will make the SEND_STATUS fail consitently with CRC error(5/5 times) while if we skip the SEND_STATUS and execute the clock tuning the link remains stable. My working theory (unconfirmed) is that CMD lane Tx path works fine so host is able to send command to the device (and that is why the clock tuning passes) but Rx path is broken so when device transmits response the CRC error is signaled(tuning command is a special case that doesn't send response on CMD). After the tuning is executed the CMD line seems to be working properly.
PATCHv2: Removed unneccessary check in EmmcIsFrequencySupportedOnBusTiming as the code that calls bus timing switch has already validated the target frequency and any frequency lower then that is also valid. Tests: - Several platforms that have been failing before(some of them with 100% repro rate) have been stress tested and are able to detect eMMC device every time Spec compliance: While the spec doesn't require or forbids the host from sending the SEND_STATUS at any point in cards operation (with the exception of busy polling the SWITCH change but we are not doing that anyway) the HS200 switch sequence in eMMC 5.1 specification section 6.6.2.2 indicates that host may send SEND_STATUS before changing the frequency. While it is not a hard requierment some eMMC vendors have indicated that the driver is at fault for not following the spec. After this patch the SEND_STATUS of every frequency upgrade path, including the switch from legacy timing -> HS200, will be sent before the frequency increase which will bring the driver closer to spec(although I don't think it can be said the driver violated it in the first place). Github https://github.com/malbecki/edk2/tree/emmc_stable_send_status Cc: Hao A Wu <hao.a...@intel.com> Cc: Marcin Wojtas <m...@semihalf.com> Cc: Zhichao Gao <zhichao....@intel.com> Cc: Liming Gao <liming....@intel.com> Mateusz Albecki (1): MdeModulePkg/SdMmcPciHcDxe: Send SEND_STATUS at lower frequency MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 88 ++++++++++++++++------ MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c | 2 +- MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h | 1 + MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 2 + 4 files changed, 69 insertions(+), 24 deletions(-) -- 2.14.1.windows.1 -------------------------------------------------------------------- Intel Technology Poland sp. z o.o. ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | Kapital zakladowy 200.000 PLN. Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego adresata i moze zawierac informacje poufne. W razie przypadkowego otrzymania tej wiadomosci, prosimy o powiadomienie nadawcy oraz trwale jej usuniecie; jakiekolwiek przegladanie lub rozpowszechnianie jest zabronione. This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). If you are not the intended recipient, please contact the sender and delete all copies; any review or distribution by others is strictly prohibited. -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#54788): https://edk2.groups.io/g/devel/message/54788 Mute This Topic: https://groups.io/mt/71534720/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
