REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4177
Because the Mbedlts 3.3.0 doesn't have SHA3 and Sm3, the SHA3 and Sm3
implementaion based on Openssl.
And the implementaion has passed build check.
Cc: Jiewen Yao
Cc: Yi Li
Signed-off-by: Wenxing Hou
---
CryptoPkg/Library/BaseCryptLibMb
Hi Yi,
Thanks for your feedback.
I have changed the code and sent the PATCH v2.
Please review the PATCH v2.
Thanks,
Wenxing
-Original Message-
From: Li, Yi1
Sent: Monday, April 22, 2024 3:43 PM
To: Hou, Wenxing ; devel@edk2.groups.io
Cc: Yao, Jiewen
Subject: RE: [PATCH] Add SHA3/SM
Reviewed-by: levi.yun
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Subject: [edk2-devel] [PATCH RESEND edk2-platfo
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> +EFI_STATUS
> +NorFlashWriteSingleBlock (
> + INNOR_FLASH_INSTANCE *Instance,
> + INEFI_LBA Lba,
> + INUINTN Offset,
> + IN OUTUINTN *NumBytes,
> + INUINT8 *Buffer
> + )
> +{
> + EFI_STATUS
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Subject: [edk2-devel] [PATCH RESEND edk2-platfo
On Sat, 2023-11-11 at 00:57 +0100, Laszlo Ersek wrote:
> NullMemoryTestDxe was included in the OVMF platforms in historical
> commit
> 999a815e9ff3 ("OvmfPkg: Add NullMemoryTestDxe driver", 2011-01-21).
> It
> produces gEfiGenericMemTestProtocolGuid. With LegacyBiosDxe gone, the
> only
> consumer o
Reviewed-by: G Edhaya Chandran
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On Wed, Apr 24, 2024 at 09:57:50AM +0800, Chao Li wrote:
> Hi Gerd and Ard,
>
> Can I submit the V2 this week? I want all OvmfPkg changes to be meged before
> the 202405 feature freeze.
Yea, go ahead, lets stick to the PCD approach, given that Ard seems to
not have objections to that ;)
take car
On Wed, Apr 24, 2024 at 03:56:56AM +, Wu, Jiaxin wrote:
> Hi Gerd,
>
> AMD version is not work for IA32X64 ovmf.
>
> I checked the detailed: CpuSaveState->x64 is always used for OVMF no matter
> IA32 or X64, while AMD is not, which is decided by the MSR EFER_ADDRESS LMA
> bit check.
Hmm, p
I am working on some changes to SbsaQemu and got some cleanups in
meantime.
First patch gets rid of setting Pcds for Timer interrupts. ArmPkg does
it for us so we do not have to.
Second changes DSDT nodes so iasl does not complain.
Marcin Juszkiewicz (2):
SbsaQemu: do not set Timer interrupts
IASL complained that DSDT is not optimal:
Dsdt.
83: Name (RBUF, ResourceTemplate() {
Remark 2173 - Creation of named objects within a method is highly
inefficient, use globals or method local variables instead ^
(\_SB.USB0._CRS)
Dsdt.
377: Name (RBUF, ResourceTemplate
Timer interrupts are set by ArmPkg.dec to recommended values.
We do not need to repeat it (and we missed HypVirtIntrNum one).
Signed-off-by: Marcin Juszkiewicz
---
Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 10 --
1 file changed, 10 deletions(-)
diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.d
Hi Stuart,
The below values are
+#define SHA1_DIGEST_SIZE 20
+#define SHA256_DIGEST_SIZE 32
+#define SHA384_DIGEST_SIZE 48
+#define SHA512_DIGEST_SIZE 64
+#define SM3_256_DIGEST_SIZE 32
already defined here:
edk2-master\MdePkg\Include\IndustryStandard\Tpm20.h
Can this file be included.
-=-=-=-=
Update: We have the struct itself define here:
https://github.com/tianocore/edk2/blob/master/MdePkg/Include/IndustryStandard/Tpm20.h#L904
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On Wed, Apr 24, 2024 at 13:32:33 +0200, Marcin Juszkiewicz wrote:
> I am working on some changes to SbsaQemu and got some cleanups in
> meantime.
>
> First patch gets rid of setting Pcds for Timer interrupts. ArmPkg does
> it for us so we do not have to.
>
> Second changes DSDT nodes so iasl does
On Tue, Apr 23, 2024 at 03:59:58PM -0500, Michael Roth wrote:
> For the most part, OVMF will clear the encryption bit for MMIO regions,
> but there is currently one known exception during SEC when the APIC
> base address is accessed via MMIO with the encryption bit set for
> SEV-ES/SEV-SNP guests.
Hi,
> > First, smram allocation doesn't work that way. Have a look at
> > OvmfPkg/SmmAccess. I guess that easily explains why this series
> > breaks S3 suspend.
>
> Oh? Could you explain a bit more for 1) how smram allocation works? 2) what's
> the possible reason break the S3? I haven't che
Hi,
> Transfer to 16bit OS waking vector - 991F0 > hang here!!!
That is the last ovmf message of a successful S3 resume, after that the
OS should have back control. Looks fine to me.
take care,
Gerd
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Hi Edhaya,
Yes, we could get rid of the TPM 2.0 definitions and include the MdePkg
definition, but it will require rework of TCG2.h to remove duplicate
definitions.
But, what is the general of philosophy of what source code edk2-test
should include from edk2? Since the purpose of edk2-test
On 4/24/24 06:54, Gerd Hoffmann wrote:
On Tue, Apr 23, 2024 at 03:59:58PM -0500, Michael Roth wrote:
For the most part, OVMF will clear the encryption bit for MMIO regions,
but there is currently one known exception during SEC when the APIC
base address is accessed via MMIO with the encryption b
Hi,
> > Ideally CpuPageTableLib should be used for this.
>
> CpuPageTableLib will need to be modified in order for it to be used at this
> (Sec) stage. In order to work in Sec - either the caller will have to supply
> a list of pages that can be used if pagetable entries need to be allocated
>
On Wed, Apr 24, 2024 at 01:54:01PM +0200, Gerd Hoffmann wrote:
> On Tue, Apr 23, 2024 at 03:59:58PM -0500, Michael Roth wrote:
> > For the most part, OVMF will clear the encryption bit for MMIO regions,
> > but there is currently one known exception during SEC when the APIC
> > base address is acce
Hi,
> > That is incompatible with 5-level paging. The current reset vector will
> > never turn on 5-level paging in case SEV is active because we have more
> > incompatibilities elsewhere (BaseMemEncryptSevLib IIRC). But still,
> > it's moving things into the wrong direction ...
>
> Tom had m
On Wed, 24 Apr 2024 at 13:19, Gerd Hoffmann wrote:
>
> On Wed, Apr 24, 2024 at 09:57:50AM +0800, Chao Li wrote:
> > Hi Gerd and Ard,
> >
> > Can I submit the V2 this week? I want all OvmfPkg changes to be meged before
> > the 202405 feature freeze.
>
> Yea, go ahead, lets stick to the PCD approach
On Wed, 24 Apr 2024 at 08:45, Yao, Jiewen wrote:
>
> Reviewed-by: Jiewen Yao
>
Thanks, I've queued this up.
> > -Original Message-
> > From: Gerd Hoffmann
> > Sent: Wednesday, April 24, 2024 2:00 PM
> > To: devel@edk2.groups.io
> > Cc: Oliver Steffen ; Gerd Hoffmann
> > ; Ard Biesheuv
On Tue, 23 Apr 2024 at 11:28, Gerd Hoffmann wrote:
>
> On Fri, Apr 19, 2024 at 11:21:46AM -0700, Adam Dunlap wrote:
> > Ensure that when a #VC exception happens, the instruction at the
> > instruction pointer matches the instruction that is expected given the
> > error code. This is to mitigate th
Thanks Ard.
I have submitted https://github.com/tianocore/edk2/pull/5595 3 hours ago.
But it seems the CI stops working...
> -Original Message-
> From: Ard Biesheuvel
> Sent: Thursday, April 25, 2024 12:27 AM
> To: Yao, Jiewen
> Cc: Gerd Hoffmann ; devel@edk2.groups.io; Oliver Steffen
On 4/24/24 09:45, Gerd Hoffmann wrote:
Hi,
Ideally CpuPageTableLib should be used for this.
CpuPageTableLib will need to be modified in order for it to be used at this
(Sec) stage. In order to work in Sec - either the caller will have to supply
a list of pages that can be used if pagetable
The more I dig in EDK2 during SbsaQemu work, the more I see duplicated
code.
Want to scan PCI bus to check for host bridges? Two or three
implementations exist. Want to calculate checksum of just created ACPI
table? AcpiPlatformChecksum() has several, incompatible with each other,
implementat
On Wed, 24 Apr 2024 at 18:36, Yao, Jiewen wrote:
>
> Thanks Ard.
>
> I have submitted https://github.com/tianocore/edk2/pull/5595 3 hours ago.
> But it seems the CI stops working...
>
OK, I have dropped my PR.
>
>
> > -Original Message-
> > From: Ard Biesheuvel
> > Sent: Thursday, Apr
From: Michael Kubacki
Fixes current CI CodeQL failures due to old CodeQL CLI version.
Updates CodeQL to work with the latest queries. Includes functional
and security fixes within the CodeQL CLI binary.
For more information on release details see:
https://github.com/github/codeql-cli-binaries/
Reviewed-by: joey.vage...@gmail.com
On Wed, Apr 24, 2024 at 10:37 AM wrote:
> From: Michael Kubacki
>
> Fixes current CI CodeQL failures due to old CodeQL CLI version.
>
> Updates CodeQL to work with the latest queries. Includes functional
> and security fixes within the CodeQL CLI binary.
>
>
Reviewed-by: Michael D Kinney
> -Original Message-
> From: mikub...@linux.microsoft.com
> Sent: Wednesday, April 24, 2024 10:37 AM
> To: devel@edk2.groups.io
> Cc: Feng, Bob C ; Joey Vagedes
> ; Liming Gao ; Kinney,
> Michael D ; Rebecca Cran
> ; Sean Brogan ; Chen,
> Christine
> Subj
Reviewed-by: Michael D Kinney
> -Original Message-
> From: Leif Lindholm
> Sent: Tuesday, April 23, 2024 7:40 AM
> To: devel@edk2.groups.io
> Cc: Ard Biesheuvel ; Kinney, Michael D
> ; Marcin Juszkiewicz
>
> Subject: [PATCH edk2-non-osi 1/1] Maintainers.txt: add maintainers for
> SbsaQe
This patch adds 2 new functions to read and write MSRs from specific CPUs.
rdmsr_ex and wrmsr_ex are the 2 new functions added into edk2module to provide
the read and write of CPU specific MSRs.
Jayaprakash N (1):
edk2-libc : add rdmsr_ex and wrmsr_ex to read/write msr from specific
cpus
.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4746
The rdmsr_ex and wrmsr_ex are extension APIs to the rdmsr and wrmsr APIs
supported in edk2 module. These extension APIs makes it possible to
read / write MSRs from specific processors. This fills an important gap in
reading / writing these r
Hi Mike,
I have sent an updated patch v2 for review which uses the MP Services protocol
API StarupThisAP() to read / write MSRs specific to CPU cores.
Please review and do the needful.
Regards,
JP
-Original Message-
From: devel@edk2.groups.io On Behalf Of Jayaprakash, N
Sent: Thursday,
W dniu 23.04.2024 o 12:36, Leif Lindholm via groups.io pisze:
QEMU v9 uses 1GHz frequency for generic timers as required for Arm v8.6+
cpu cores. TF-A was hardcoding 62.5MHz value which is used for older
designs. Now it will use value present in CNTFRQ_EL0 register (set by
QEMU).
Enable FEAT_ECV
Thanks for reviews. I've updated the PR
(https://github.com/tianocore/edk2/pull/5597) to include them.
Although it has not been 24 hours, I suggest we merge the patch soon to
ensure CI is unblocked. Please feel free to add the push tag or let me
know if you'd like me to.
Thanks,
Michael
On
Go ahead and add the push label.
Mike
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Michael
> Kubacki
> Sent: Wednesday, April 24, 2024 2:55 PM
> To: devel@edk2.groups.io
> Cc: Feng, Bob C ; Liming Gao
> ; Rebecca Cran ; Sean
> Brogan ; Chen, Christine
>
> Subject: Re:
Added. These two PRs seem to be the only ones already impacted by this:
- https://github.com/tianocore/edk2/pull/5596
- https://github.com/tianocore/edk2/pull/5582
Rebasing after https://github.com/tianocore/edk2/pull/5597 is completed
will resolve the CodeQL failures.
Thanks,
Michael
On 4/2
Hi Mike/Sean
Can someone look at the EDKII CI?
My PR has been blocked for 9 hours -
https://github.com/tianocore/edk2/pull/5595.
Thank you
Yao, Jiewen
> -Original Message-
> From: Ard Biesheuvel
> Sent: Thursday, April 25, 2024 1:05 AM
> To: Yao, Jiewen
> Cc: Gerd Hoffmann ; devel@ed
Hi Jiewen,
Michael Kubacki has been working on a CI issue and a change is being merged now.
Mike
> -Original Message-
> From: Yao, Jiewen
> Sent: Wednesday, April 24, 2024 3:57 PM
> To: devel@edk2.groups.io; Kinney, Michael D
> ; Sean Brogan
> Cc: Gerd Hoffmann ; Ard Biesheuvel ;
> Oli
Ah, thank you Mike.
Should I close/re-open my PR?
Or should I keep waiting?
Thank you
Yao, Jiewen
> -Original Message-
> From: Kinney, Michael D
> Sent: Thursday, April 25, 2024 7:01 AM
> To: Yao, Jiewen ; devel@edk2.groups.io; Sean Brogan
> ; Michael Kubacki
>
> Cc: Gerd Hoffmann ; Ar
That issue looks different in that CodeQL did not have a problem. You
can use the same PR, just rebase with master.
It looks like that had an issue triggering pipelines from GitHub which
might be fixed be rerunning after the push.
Thanks,
Michael
On 4/24/2024 7:08 PM, Yao, Jiewen wrote:
Ah,
*Reminder: TianoCore Bug Triage - APAC / NAMO*
*When:*
Wednesday, April 24, 2024
5:30pm to 6:30pm
(UTC-07:00) America/Los Angeles
*Where:*
https://teams.microsoft.com/l/meetup-join/19%3ameeting_OTk1YzJhN2UtOGQwNi00NjY4LWEwMTktY2JiODRlYTY1NmY0%40thread.v2/0?context=%7b%22Tid%22%3a%2246c98d88-e344-
Reviewed-By: Giri Mudusuru
From: devel@edk2.groups.io on behalf of Ellie Lewis via
groups.io
Sent: Tuesday, April 23, 2024 3:51 AM
To: devel@edk2.groups.io
Cc: Zhichao Gao
Subject: [EXTERNAL] [edk2-devel] [PATCH v1 1/1] ShellPkg/SmbiosView: Add Type
45 entry
Hi Everyone,
I'm working on a project with edk2, and these guys are trying to port edk2
to STM32MP25 platforms. I had no issue compiling and booting the image on
my device. Then I've come across an issue at very early stages of booting.
I was given a Synchronous Exception listed briefly below.
Sy
Bump the compile-time constant for maximum processor count from 64 to 128
in order to allow that many vCPUs to be brought online on Xen guests with
the default OVMF configuration.
Cc: Anthony Perard
Cc: Ard Biesheuvel
Cc: Gerd Hoffmann
Cc: Jiewen Yao
Signed-off-by: Alejandro Vallejo
---
Ovmf
Revision macros of PEI/DXE/MM specifications have been consolidated to a single
PI macro
Cc: Felix Polyudov
Cc: Dhanaraj V
Cc: Liming Gao
Signed-off-by: Sachin Ganesh
---
MdePkg/Include/Pi/PiDxeCis.h | 4 ++--
MdePkg/Include/Pi/PiMmCis.h | 6 +++---
MdePkg/Include/Pi/PiMultiPhase.h
Reviewed-By: Giri Mudusuru
From: devel@edk2.groups.io on behalf of Shenbagadevi R
via groups.io
Sent: Tuesday, April 23, 2024 4:59 AM
To: devel@edk2.groups.io ; Shenbagadevi R
Cc: gaolim...@byosoft.com.cn ; Sainadh Nagolu
; Sundaresan S ; Srinivasan Mani
; R
Reviewed-By: Giri Mudusuru
From: devel@edk2.groups.io on behalf of gaoliming via
groups.io
Sent: Tuesday, April 23, 2024 6:15 AM
To: 'Nong, Foster' ; devel@edk2.groups.io
; Kinney, Michael D ; 'Chris
Li'
Cc: Ni, Ray
Subject: [EXTERNAL] 回复: [edk2-devel] [PATC
The fault address is 0x0004AC14. Is that in the address range of the
GIC for this platform? What does that Physical address map to you on the
STM32MP25?
Thanks,
Andrew Fish
> On Apr 21, 2024, at 10:07 PM, Ba Gia Bao Phan
> wrote:
>
> Hi Everyone,
>
> I'm working on a project with e
> >
> > AMD version is not work for IA32X64 ovmf.
> >
> > I checked the detailed: CpuSaveState->x64 is always used for OVMF no
> matter IA32 or X64, while AMD is not, which is decided by the MSR
> EFER_ADDRESS LMA bit check.
>
> Hmm, probably because only PEI runs in 32-bit mode whereas DXE and SM
>
> > Transfer to 16bit OS waking vector - 991F0 > hang here!!!
>
> That is the last ovmf message of a successful S3 resume, after that the
> OS should have back control. Looks fine to me.
>
Great, got it.
Thanks,
Jiaxin
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Gerd,
Ha, it seems that Ard have already given the answer... I will adjust
according to Ard's suggestion and send the V2 today. :)
Thanks,
Chao
On 2024/4/24 19:19, Gerd Hoffmann wrote:
On Wed, Apr 24, 2024 at 09:57:50AM +0800, Chao Li wrote:
Hi Gerd and Ard,
Can I submit the V2 this week?
Hi Ard,
OK, let's go with HOBs and today I'm going to send the V2. :)
Thanks,
Chao
On 2024/4/25 00:23, Ard Biesheuvel wrote:
On Wed, 24 Apr 2024 at 13:19, Gerd Hoffmann wrote:
On Wed, Apr 24, 2024 at 09:57:50AM +0800, Chao Li wrote:
Hi Gerd and Ard,
Can I submit the V2 this week? I want al
>
> SmramInternal.c handles that. It creates two regions, one is a page at
> the start of SMRAM where S3 state is stored (and marked as allocated),
> one is all the rest.
>
Yes, the same logic is moved to the OvmfPkg/Library/PlatformInitLib/MemDetect.c:
//
// Create first SMRAM descrip
Thank you very much for the help.
https://github.com/tianocore/edk2/pull/5595 merged.
> -Original Message-
> From: Michael Kubacki
> Sent: Thursday, April 25, 2024 7:22 AM
> To: devel@edk2.groups.io; Yao, Jiewen ; Kinney, Michael
> D ; Sean Brogan
> Cc: Gerd Hoffmann ; Ard Biesheuvel ;
Patch1: Added three PCDs for QemuFwCfgLibMmio
Patch2: Sparate QemuFwCfgLibMmio.c into two files and default as DXE
stage library.
Patch3: Added QemuFwCfgMmiLib PEI version
Patch4: Rename QemuFwCfgLibMmio.inf to QemuFwCfgMmioDxeLib.inf and
enable it in AARCH64 and RISCV64.
V1 -> V2:
1. Use HOBs ins
Separate QemuFwCfgLibMmio.c into two files named QemuFwCfgLibMmio.c and
QemuFwCfgLibMmioDxe.c, added a new header named
QemuFwCfgLibMmioInternal.h for MMIO version.
Build-tested only (with "ArmVirtQemu.dsc and RiscVVirtQemu.dsc").
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4755
Cc: Ard B
Added the PEI stage library for QemuFwCfgMmioLib, which uses the FDT to
find the fw_cfg and parse it.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4755
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Gerd Hoffmann
Co-authored-by: Xianglai Li
Signed-off-by: Chao Li
---
.../Library/QemuFwCfgLib/Q
Added the HOB methods to load and store the QEMU firmware configure
address, data address and DMA address, which are not enabled during the
DXE stage.
Build-tested only (with "ArmVirtQemu.dsc and RiscVVirtQemu.dsc").
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4755
Cc: Ard Biesheuvel
Cc:
Enable QemuFwCfgMmioDxeLib.inf in ArmVirtQemu.dsc and
ArmVirtQemuKernel.dsc.
Build-tested only (with "ArmVirtQemu.dsc").
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4755
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Gerd Hoffmann
Cc: Leif Lindholm
Cc: Sami Mujawar
Signed-off-by: Chao Li
---
Copy QemuFwCfgLibMmio.inf to QemuFwCfgMmioDxeLib.inf,
QemuFwCfgLibMmio.inf will be deleted when all platforms switching is
completed.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4755
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Gerd Hoffmann
Signed-off-by: Chao Li
---
.../QemuFwCfgLib/QemuFw
Enable QemuFwCfgMmioDxeLib.inf in RiscVVirtQemu.dsc
Build-tested only (with "RiscVVirtQemu.dsc").
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4755
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Gerd Hoffmann
Cc: Sunil V L
Cc: Andrei Warkentin
Signed-off-by: Chao Li
---
OvmfPkg/RiscVVirt/Ris
All of platforms are switching to QemuFwCfgMmioDxeLib.inf, remove
QemuFwCfgLibMmio.inf now.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4755
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Gerd Hoffmann
Signed-off-by: Chao Li
---
.../Library/QemuFwCfgLib/QemuFwCfgLibMmio.inf | 51 --
The local variable 'WillReturn' was being used without prior
initialization in some code paths.
This patch ensures that 'WillReturn' is properly initialized
to prevent undefined behavior.
Cc: Liming Gao
Cc: Jiaxin Wu
Cc: Ray Ni
Cc: Laszlo Ersek
Signed-off-by: Zhiguang Liu
---
MdeModulePkg/C
The local variable 'WillReturn' was being used without prior
initialization in some code paths.
This patch ensures that 'WillReturn' is properly initialized
to prevent undefined behavior.
Cc: Liming Gao
Cc: Jiaxin Wu
Cc: Ray Ni
Cc: Laszlo Ersek
Cc: Ard Biesheuvel
Cc: Sami Mujawar
Signed-off-
Hi Stuart,
Thank you for the update. I understand the rationale.
It is also in-line with the independent protocol interface definition in
edk2-test.
Will approve the patch.
Reviewed-by: G Edhaya Chandran
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I checked the AMD64 Architecture Programmer's Manual and it says below:
--- AMD64 manual ---
SMM-revision Level—Bits 15:0. Specifies the version of SMM supported by the
processor. The SMM-revision level is of the form 0_xx64h, where xx starts with
00 and is incremented for later revisions to the
Reviewed-by: Ray Ni
Thanks,
Ray
From: Liu, Zhiguang
Sent: Thursday, April 25, 2024 12:40
To: devel@edk2.groups.io
Cc: Liu, Zhiguang ; Liming Gao
; Wu, Jiaxin ; Ni, Ray
; Laszlo Ersek
Subject: [PATCH 1/2] MdeModulePkg/SMM: Initialize 'WillReturn' variable
The
Reviewed-by: Ray Ni
Thanks,
Ray
From: Liu, Zhiguang
Sent: Thursday, April 25, 2024 12:40
To: devel@edk2.groups.io
Cc: Liu, Zhiguang ; Liming Gao
; Wu, Jiaxin ; Ni, Ray
; Laszlo Ersek ; Ard Biesheuvel
; Sami Mujawar
Subject: [PATCH 2/2] StandaloneMmPkg: Initi
-# Copyright (c) 2023, Intel Corporation. All rights reserved.
+# Copyright (c) 2024, Intel Corporation. All rights reserved.
Yuanhao, why did you change the copyright year from 2023 to 2024?
You can either leave it unchanged, or change it to "2023 - 2024".
# SPDX-License-Identifier: BSD-2-Clau
Ok！
From: Ni, Ray
Sent: Thursday, April 25, 2024 1:54 PM
To: Xie, Yuanhao ; devel@edk2.groups.io
Cc: Dong, Eric ; Kumar, Rahul R ;
Gerd Hoffmann ; Wu, Jiaxin
Subject: Re: [PATCH 1/1] UefiCpuPkg/SmmCpuSyncLib: Add MM_STANDALONE tag.
-# Copyright (c) 2023, Intel Corporation. All rights reserved
Looks good to me.
Reviewed-by: Yi Li
-Original Message-
From: Hou, Wenxing
Sent: Wednesday, April 24, 2024 4:25 PM
To: devel@edk2.groups.io
Cc: Yao, Jiewen ; Li, Yi1
Subject: [PATCH v2] Add SHA3/SM3 functions with openssl for Mbedtls
REF: https://bugzilla.tianocore.org/show_bug.cgi?
Hi,
> That means the SMMRevId is 0_xx64h for AMD64 processor. But I am not
> sure what the value is for AMD32 processor. Maybe 0 according to the
> OVMF logic.
The smm emulation in the linux kernel uses 0 and 0x64.
> But, I am very suspicious about the logic in AMD's version as below:
> --- AM
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